Merge tag 'drm-intel-gt-next-2024-04-26' of https://anongit.freedesktop.org/git/drm...

UAPI Changes:

- drm/i915/guc: Use context hints for GT frequency

    Allow user to provide a low latency context hint. When set, KMD
    sends a hint to GuC which results in special handling for this
    context. SLPC will ramp the GT frequency aggressively every time
    it switches to this context. The down freq threshold will also be
    lower so GuC will ramp down the GT freq for this context more slowly.
    We also disable waitboost for this context as that will interfere with
    the strategy.

    We need to enable the use of SLPC Compute strategy during init, but
    it will apply only to contexts that set this bit during context
    creation.

    Userland can check whether this feature is supported using a new param-
    I915_PARAM_HAS_CONTEXT_FREQ_HINT. This flag is true for all guc submission
    enabled platforms as they use SLPC for frequency management.

    The Mesa usage model for this flag is here -
    https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint

- drm/i915/gt: Enable only one CCS for compute workload

    Enable only one CCS engine by default with all the compute sices
    allocated to it.

    While generating the list of UABI engines to be exposed to the
    user, exclude any additional CCS engines beyond the first
    instance

    ***

    NOTE: This W/A will make all DG2 SKUs appear like single CCS SKUs by
    default to mitigate a hardware bug. All the EUs will still remain
    usable, and all the userspace drivers have been confirmed to be able
    to dynamically detect the change in number of CCS engines and adjust.

    For the smaller percent of applications that get perf benefit from
    letting the userspace driver dispatch across all 4 CCS engines we will
    be introducing a sysfs control as a later patch to choose 4 CCS each
    with 25% EUs (or 50% if 2 CCS).

    NOTE: A regression has been reported at

    https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895

    However Andi has been triaging the issue and we're closing in a fix
    to the gap in the W/A implementation:

    https://lists.freedesktop.org/archives/intel-gfx/2024-April/348747.html

Driver Changes:

- Add new and fix to existing workarounds: Wa_14018575942 (MTL),
  Wa_16019325821 (Gen12.70), Wa_14019159160 (MTL), Wa_16015675438,
  Wa_14020495402 (Gen12.70) (Tejas, John, Lucas)
- Fix UAF on destroy against retire race and remove two earlier
  partial fixes (Janusz)
- Limit the reserved VM space to only the platforms that need it (Andi)
- Reset queue_priority_hint on parking for execlist platforms (Chris)
- Fix gt reset with GuC submission is disabled (Nirmoy)
- Correct capture of EIR register on hang (John)

- Remove usage of the deprecated ida_simple_xx() API
- Refactor confusing __intel_gt_reset() (Nirmoy)
- Fix the fix for GuC reset lock confusion (John)
- Simplify/extend platform check for Wa_14018913170 (John)
- Replace dev_priv with i915 (Andi)
- Add and use gt_to_guc() wrapper (Andi)
- Remove bogus null check (Rodrigo, Dan)

. Selftest improvements (Janusz, Nirmoy, Daniele)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZitVBTvZmityDi7D@jlahtine-mobl.ger.corp.intel.com

diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/selftests/huge_pages.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/gen8_engine_cs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_engine_cs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_ggtt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.h
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_regs.h
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_reset.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_rps.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index d4e8daf9e6a9c5d747edcc4258b7bbb8a0635fac,71dc6f10a0371463781cffd108d9417c28e32cd0..68b6aa11bcf7db8efe0433ab39968dcc92369288
--- 1/drivers/gpu/drm/i915/gt/intel_workarounds.c
--- 2/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2800,9 -2960,7 +2804,6 @@@ general_render_compute_wa_init(struct i
                /* Wa_14015227452:dg2,pvc */
                wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
  
-               /* Wa_16015675438:dg2,pvc */
-               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
- 
 -      if (IS_DG2(i915)) {
                /*
                 * Wa_16011620976:dg2_g11
                 * Wa_22015475538:dg2

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc.c
index b85706aa4aff31da8040d239836a84f957a08ed6,a6440cfe4b9851ce9685338bf668e95a5b64c1e9..5e60a34692af80e45ba3adc06d8031d516de6b55
--- 1/drivers/gpu/drm/i915/gt/uc/intel_guc.c
--- 2/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@@ -315,11 -320,17 +320,12 @@@ static u32 guc_ctl_wa_flags(struct inte
        if (IS_DG2_G11(gt->i915))
                flags |= GUC_WA_CONTEXT_ISOLATION;
  
-       /* Wa_14018913170 */
-       if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0)) {
-               if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915))
-                       flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
-       }
 -      /* Wa_18020744125 */
 -      if (!RCS_MASK(gt))
 -              flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
 -
+       /*
+        * Wa_14018913170: Applicable to all platforms supported by i915 so
+        * don't bother testing for all X/Y/Z platforms explicitly.
+        */
 -      if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0)) {
++      if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0))
+               flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
 -      }
  
        return flags;
  }

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc.h
index be70c46604b49bf244e916d924738818dc2ec82d,b572fc10fd24d38f844c791bc19502d12f84cd1f..57b903132776725b38baf22a2662b5c6375021c8
--- 1/drivers/gpu/drm/i915/gt/uc/intel_guc.h
--- 2/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@@ -204,8 -204,12 +204,10 @@@ struct intel_guc 
        struct guc_mmio_reg *ads_regset;
        /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
        u32 ads_golden_ctxt_size;
+       /** @ads_waklv_size: size of workaround KLVs */
+       u32 ads_waklv_size;
        /** @ads_capture_size: size of register lists in the ADS used for error capture */
        u32 ads_capture_size;
 -      /** @ads_engine_usage_size: size of engine usage in the ADS */
 -      u32 ads_engine_usage_size;
  
        /** @lrc_desc_pool_v69: object allocated to hold the GuC LRC descriptor pool */
        struct i915_vma *lrc_desc_pool_v69;

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_driver.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_getparam.c
Simple merge

diff --cc include/uapi/drm/i915_drm.h
Simple merge