* simops.c: Fix more bugs in "add imm,an" and

        "add imm,dn".
Fixes a half-dozen (of several hundred :( c-torture failures.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 9c875bb2df2deeb0a9dd1e815fe7e10c598a9499..c3f3e375a1d40131aad76b8ca3e907921984eb1c 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,8 @@
+Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * simops.c: Fix more bugs in "add imm,an" and
+       "add imm,dn".
+
 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 
        * simops.c: Fix bugs in "movm" and "add imm,an".

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 20cd9761ab0fef0b92363832d5940c04bd08c7c2..e2f1ffded06616ab1c1500ad584d59822c8b286b 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -1034,10 +1034,10 @@ void OP_FAC00000 ()
   int z, c, n, v;
   unsigned long reg1, imm, value;
 
-  reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
+  reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
   imm = SEXT16 (insn & 0xffff);
   value = reg1 + imm;
-  State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
+  State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1056,10 +1056,10 @@ void OP_FCC00000 ()
   int z, c, n, v;
   unsigned long reg1, imm, value;
 
-  reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
+  reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
   imm = ((insn & 0xffff) << 16) | extension;
   value = reg1 + imm;
-  State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
+  State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1100,10 +1100,10 @@ void OP_FAD00000 ()
   int z, c, n, v;
   unsigned long reg1, imm, value;
 
-  reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
+  reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
   imm = SEXT16 (insn & 0xffff);
   value = reg1 + imm;
-  State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
+  State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);
@@ -1122,10 +1122,10 @@ void OP_FCD00000 ()
   int z, c, n, v;
   unsigned long reg1, imm, value;
 
-  reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
+  reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
   imm = ((insn & 0xffff) << 16) | extension;
   value = reg1 + imm;
-  State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
+  State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 
   z = (value == 0);
   n = (value & 0x80000000);