2008-11-04 Sterling Augustine <sterling@tensilica.com>

	* config/tc-xtensa.c (tinsn_check_arguments): Check for multiple
	writes to the same register.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 72df07b68eade635e3fbd7d1b08af8a94472aa7a..b5e42b9a949a02398a0190771b90ee20c550e40e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2008-11-04  Sterling Augustine  <sterling@tensilica.com>
+       
+       * config/tc-xtensa.c (tinsn_check_arguments): Check for multiple
+       writes to the same register.
+       
 2008-11-04  Sterling Augustine  <sterling@tensilica.com>
        
        * config/tc-xtensa.c (xtensa_j_opcode): New.

diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index 92e796c64653745f8307e4efc7149e2a59f0130a..f1ccd2833472a6aa9400a3f2c38a356ae19048de 100644 (file)
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -11457,6 +11457,12 @@ tinsn_check_arguments (const TInsn *insn)
 {
   xtensa_isa isa = xtensa_default_isa;
   xtensa_opcode opcode = insn->opcode;
+  xtensa_regfile t1_regfile, t2_regfile;
+  int t1_reg, t2_reg;
+  int t1_base_reg, t1_last_reg;
+  int t2_base_reg, t2_last_reg;
+  char t1_inout, t2_inout;
+  int i, j;
 
   if (opcode == XTENSA_UNDEFINED)
     {
@@ -11475,6 +11481,54 @@ tinsn_check_arguments (const TInsn *insn)
       as_bad (_("too many operands"));
       return TRUE;
     }
+
+  /* Check registers.  */
+  for (j = 0; j < insn->ntok; j++)
+    {
+      if (xtensa_operand_is_register (isa, insn->opcode, j) != 1)
+       continue;
+
+      t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j);
+      t2_base_reg = insn->tok[j].X_add_number;
+      t2_last_reg
+       = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j);
+
+      for (i = 0; i < insn->ntok; i++)
+       {
+         if (i == j)
+           continue;
+
+         if (xtensa_operand_is_register (isa, insn->opcode, i) != 1)
+           continue;
+
+         t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i);
+
+         if (t1_regfile != t2_regfile)
+           continue;
+
+         t1_inout = xtensa_operand_inout (isa, insn->opcode, i);
+         t2_inout = xtensa_operand_inout (isa, insn->opcode, j);
+
+         t1_base_reg = insn->tok[i].X_add_number;
+         t1_last_reg = (t1_base_reg
+                        + xtensa_operand_num_regs (isa, insn->opcode, i));
+
+         for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
+           {
+             for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
+               {
+                 if (t1_reg != t2_reg)
+                   continue;
+
+                 if (t1_inout != 'i' && t2_inout != 'i')
+                   {
+                     as_bad (_("multiple writes to the same register"));
+                     return TRUE;
+                   }
+               }
+           }
+       }
+    }
   return FALSE;
 }