+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * elfxx-mips.c (print_mips_ases): Add GINV extension.
+
2018-06-14 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/23267
fputs ("\n\tMIPS16e2 ASE", file);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", file);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", file);
if (mask == 0)
fprintf (file, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * readelf.c (print_mips_ases): Add GINV extension.
+
2018-06-14 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/23267
fputs ("\n\tMIPS16e2 ASE", stdout);
if (mask & AFL_ASE_CRC)
fputs ("\n\tCRC ASE", stdout);
+ if (mask & AFL_ASE_GINV)
+ fputs ("\n\tGINV ASE", stdout);
if (mask == 0)
fprintf (stdout, "\n\t%s", _("None"));
else if ((mask & ~AFL_ASE_MASK) != 0)
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * NEWS: Mention MIPS Global INValidate ASE support.
+ * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
+ (md_longopts): Likewise.
+ (mips_ases): Define availability for GINV.
+ (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
+ (md_show_usage): Add help for -mginv and -mno-ginv.
+ * doc/as.texinfo: Document -mginv, -mno-ginv.
+ * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
+ .set noginv.
+ * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
+ ASE.
+ * testsuite/gas/mips/ase-errors-2.s: Likewise.
+ * testsuite/gas/mips/ase-errors-1.l: Likewise.
+ * testsuite/gas/mips/ase-errors-2.l: Likewise.
+ * testsuite/gas/mips/ginv.d: New test.
+ * testsuite/gas/mips/ginv-err.d: New test.
+ * testsuite/gas/mips/ginv-err.l: New test stderr output.
+ * testsuite/gas/mips/ginv.s: New test source.
+ * testsuite/gas/mips/ginv-err.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
-*- text -*-
+* Add support for the MIPS Global INValidate (GINV) ASE.
+
* Add support for the MIPS Cyclic Redudancy Check (CRC) ASE.
* Add support for the Freescale S12Z architecture.
OPTION_NAN,
OPTION_ODD_SPREG,
OPTION_NO_ODD_SPREG,
+ OPTION_GINV,
+ OPTION_NO_GINV,
OPTION_END_OF_ENUM
};
{"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
{"mcrc", no_argument, NULL, OPTION_CRC},
{"mno-crc", no_argument, NULL, OPTION_NO_CRC},
+ {"mginv", no_argument, NULL, OPTION_GINV},
+ {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
/* Old-style architecture options. Don't add more of these. */
{"m4650", no_argument, NULL, OPTION_M4650},
OPTION_CRC, OPTION_NO_CRC,
6, 6, -1, -1,
-1 },
+
+ { "ginv", ASE_GINV, 0,
+ OPTION_GINV, OPTION_NO_GINV,
+ 6, 6, 6, 6,
+ -1 },
};
/* The set of ASEs that require -mfp64. */
ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
if (ase & ASE_CRC)
ext_ases |= AFL_ASE_CRC;
+ if (ase & ASE_GINV)
+ ext_ases |= AFL_ASE_GINV;
return ext_ases;
}
-mcrc generate CRC instructions\n\
-mno-crc do not generate CRC instructions\n"));
fprintf (stream, _("\
+-mginv generate Global INValidate (GINV) instructions\n\
+-mno-ginv do not generate Global INValidate instructions\n"));
+ fprintf (stream, _("\
-minsn32 only generate 32-bit microMIPS instructions\n\
-mno-insn32 generate all microMIPS instructions\n"));
fprintf (stream, _("\
[@b{-mmt}] [@b{-mno-mt}]
[@b{-mmcu}] [@b{-mno-mcu}]
[@b{-mcrc}] [@b{-mno-crc}]
+ [@b{-mginv}] [@b{-mno-ginv}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
Specific Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
Extension. This tells the assembler to accept CRC instructions.
@samp{-mno-crc} turns off this option.
+@item -mginv
+@itemx -mno-ginv
+Generate code for the Global INValidate (GINV) Application Specific
+Extension. This tells the assembler to accept GINV instructions.
+@samp{-mno-ginv} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
from the CRC Extension from that point on in the assembly. The
@code{.set nocrc} directive prevents CRC instructions from being accepted.
+@cindex MIPS Global INValidate (GINV) instruction generation override
+@kindex @code{.set ginv}
+@kindex @code{.set noginv}
+The directive @code{.set ginv} makes the assembler accept instructions
+from the GINV Extension from that point on in the assembly. The
+@code{.set noginv} directive prevents GINV instructions from being accepted.
+
Traditional MIPS assemblers do not support these directives.
@node MIPS Floating-Point
.*:108: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
.*:109: Warning: the `crc' extension requires MIPS32 revision 6 or greater
.*:112: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
+# ----------------------------------------------------------------------------
+.*:117: Warning: the `ginv' extension requires MIPS32 revision 6 or greater
+.*:120: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
.set nocrc
crc32b $4,$7,$4 # ERROR: crc not enabled
+ .set mips32r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ .set mips32r5 # ERROR: too low
+ ginvt $a0, 1 # OK
+ .set noginv
+ ginvi $a0 # ERROR: ginv not enabled
+
# There should be no errors after this.
.set fp=32
.set mips1
.*:93: Warning: the `crc' extension requires MIPS64 revision 6 or greater
.*:97: Error: opcode not supported.* `crc32b \$4,\$7,\$4'
.*:98: Error: opcode not supported.* `crc32d \$4,\$7,\$4'
+# ----------------------------------------------------------------------------
+.*:103: Warning: the `ginv' extension requires MIPS64 revision 6 or greater
+.*:106: Error: opcode not supported.* `ginvi \$a0'
+# ----------------------------------------------------------------------------
crc32b $4,$7,$4 # ERROR: crc not enabled
crc32d $4,$7,$4 # ERROR: crc not enabled
+ .set mips64r6
+ .set ginv # OK
+ ginvi $a0 # OK
+ .set mips64r5 # ERROR: too low
+ ginvt $a0,1 # OK
+ .set noginv
+ ginvi $a0 # ERROR: ginv not enabled
+
# There should be no errors after this.
.set fp=32
.set mips4
--- /dev/null
+#name: MIPS GINV instruction errors
+#as: -32 -mginv
+#error-output: ginv-err.l
--- /dev/null
+.*: Assembler messages:
+.*:3: Error: invalid operands `ginvi 2'
+.*:4: Error: invalid operands `ginvt 3,3'
+.*:5: Error: operand 2 out of range `ginvt \$4,4'
--- /dev/null
+ .text
+test:
+ ginvi 2
+ ginvt 3,3
+ ginvt $4,4
--- /dev/null
+#objdump: -pdr --prefix-addresses --show-raw-insn
+#name: MIPS GINV
+#as: -mginv -32
+
+# Test GINV instructions.
+
+.*: +file format .*mips.*
+#...
+ASEs:
+#...
+ GINV ASE
+#...
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7c40003d ginvi v0
+[0-9a-f]+ <[^>]*> 7c6000bd ginvt v1,0x0
+[0-9a-f]+ <[^>]*> 7c8001bd ginvt a0,0x1
+ \.\.\.
--- /dev/null
+ .text
+test:
+ ginvi $2
+ ginvt $3,0
+ ginvt $4,1
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
run_dump_test_arches "crc-err" [mips_arch_list_matching mips32r6]
run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6]
run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6]
+
+ run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6]
}
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
+ (AFL_ASE_MASK): Update to include AFL_ASE_GINV.
+ * opcode/mips.h: Document "+\" operand format.
+ (ASE_GINV): New macro.
+
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
#define AFL_ASE_MIPS16E2 0x00004000 /* MIPS16e2 ASE. */
#define AFL_ASE_CRC 0x00008000 /* CRC ASE. */
-#define AFL_ASE_MASK 0x0000ffff /* All ASEs. */
+#define AFL_ASE_RESERVED1 0x00010000 /* Reserved by MIPS Tech for WIP. */
+#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */
+#define AFL_ASE_MASK 0x0002ffff /* All ASEs. */
/* Values for the isa_ext word of an ABI flags structure. */
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
- "~!@#$%^&*|:'";"
+ "~!@#$%^&*|:'";\"
"ABCEFGHIJKLMNOPQRSTUVWXZ"
"abcdefghijklmnopqrstuvwxyz"
/* Cyclic redundancy check (CRC) ASE. */
#define ASE_CRC 0x00040000
#define ASE_CRC64 0x00080000
+/* Global INValidate Extension. */
+#define ASE_GINV 0x00100000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
+2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
+
+ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
+ mips64r6 descriptors.
+ (parse_mips_ase_option): Handle -Mginv option.
+ (print_mips_disassembler_options): Document -Mginv.
+ * mips-opc.c (decode_mips_operand) <+\>: New operand format.
+ (GINV): New macro.
+ (mips_opcodes): Define ginvi and ginvt.
+
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
ISA_MIPS32R6,
(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
- | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC),
+ | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
ISA_MIPS64R6,
(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
- | ASE_CRC64),
+ | ASE_CRC64 | ASE_GINV),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
return TRUE;
}
+ if (CONST_STRNEQ (option, "ginv"))
+ {
+ mips_ase |= ASE_GINV;
+ return TRUE;
+ }
+
return FALSE;
}
xpa Recognize the eXtended Physical Address (XPA)\n\
ASE instructions.\n"));
+ fprintf (stream, _("\n\
+ ginv Recognize the Global INValidate (GINV) ASe\n\
+ instructions.\n"));
+
fprintf (stream, _("\n\
gpr-names=ABI Print GPR names according to specified ABI.\n\
Default: based on binary being disassembled.\n"));
case '\'': BRANCH (26, 0, 2);
case '"': BRANCH (21, 0, 2);
case ';': SPECIAL (10, 16, SAME_RS_RT);
+ case '\\': BIT (2, 8, 0); /* (0 .. 3) */
}
break;
#define CRC ASE_CRC
#define CRC64 ASE_CRC64
+/* Global INValidate (GINV) support. */
+#define GINV ASE_GINV
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
{"crc32cw", "t,s,-d", 0x7c00018f, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC, 0 },
{"crc32cd", "t,s,-d", 0x7c0001cf, 0xfc00ffff, MOD_1|RD_2, 0, 0, CRC64, 0 },
+/* MIPS Global INValidate (GINV) ASE. */
+{"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 },
+{"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
projects / thirdparty / binutils-gdb.git / commitdiff
