Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7bb19080aa98ac69114a02ed67e20323b70a197e..7b5232667ebb07e083968c9df4026eea831c46d5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,55 @@
+2025-11-23  John David Anglin  <danglin@gcc.gnu.org>
+
+       * config/pa/pa64-linux.h (GLIBC_DYNAMIC_LINKER): Define.
+
+2025-11-23  John David Anglin  <danglin@gcc.gnu.org>
+
+       PR target/113932
+       PR target/113933
+       * config/pa/pa.opt (mlra): Default to LRA instead of reload.
+
+2025-11-23  John David Anglin  <danglin@gcc.gnu.org>
+
+       * config/pa/pa.cc (pa_print_operand): Use REG_POINTER
+       flag to select base and index registers on targets with
+       non-equivalent space registers.
+       (pa_legitimate_address_p): Don't allow scaled and unscaled
+       indexed addresses until reload is complete.  Allow any
+       register order in unscaled addresses as long as the
+       REG_POINTER flag is correctly set/unset in the base/index
+       registers.
+       * config/pa/predicates.md (mem_operand): Remove code to
+       delay creating move insns with unscaled indexed addresses
+       until CSE is not expected.
+       (move_src_operand): Likewise.
+
+2025-11-23  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+
+       * match.pd (1/x): Use fold_before_rtl_expansion_p.
+       (`(m1 CMP m2) * d`): Likewise.
+
+2025-11-23  Pan Li  <pan2.li@intel.com>
+
+       * match.pd: Remove unnecessary outer convert and add
+       c for the outer bit_ior.
+
+2025-11-23  Pan Li  <pan2.li@intel.com>
+
+       * match.pd: Add simplfy to fold outer convert of bit_op
+       to inner captures.
+
+2025-11-23  Kugan Vivekanandarajah  <kvivekananda@nvidia.com>
+
+       * ipa-split.cc (pass_split_functions::gate): Do not run when
+       flag_auto_profile.
+       (pass_feedback_split_functions::gate): Run when flag_auto_profile.
+
+2025-11-23  Kugan Vivekanandarajah  <kvivekananda@nvidia.com>
+
+       * tree-ssa-loop-im.cc (is_self_write): New.
+       (ref_indep_loop_p): Allow hoisting when aliasing references
+       form a self write pattern.
+
 2025-11-22  Jeff Law  <jlaw@ventanamicro.com>
 
        PR rtl-optimization/122701

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index aaefa8d123a967a51cfa6805e085ded8352f8049..0b7cf952dab088d6b0107569aeb3873b6796456a 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20251123
+20251124

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ebb818bbb2ca5ca598913aadab7ecb62db4d885b..ea79fd5d1d22b7e3bb0826703d17a2532f42ea63 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,24 @@
+2025-11-23  Pan Li  <pan2.li@intel.com>
+
+       * gcc.dg/tree-ssa/bit_op_cvt.1.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.2.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.3.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.4.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.5.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.6.c: New test.
+       * gcc.dg/tree-ssa/bit_op_cvt.h: New test.
+
+2025-11-23  Kugan Vivekanandarajah  <kvivekananda@nvidia.com>
+
+       * gcc.dg/vect/vect-licm-hoist-1.c: New.
+       * gcc.dg/vect/vect-licm-hoist-2.c: Likewise.
+
+2025-11-23  Sandra Loosemore  <sloosemore@baylibre.com>
+
+       * c-c++-common/gomp/delim-declare-variant-6.c (f3): Use "x86"
+       instead of "x86_64" in the arch selector, to match both 64- and
+       32-bit targets.
+
 2025-11-22  Nathaniel Shead  <nathanieloshead@gmail.com>
 
        PR c++/122636

diff --git a/libgm2/ChangeLog b/libgm2/ChangeLog
index f16c52552f36b8b192f229f36183b2bdc74a01ec..6dac0eab683a8e476baeb67e9687f186c3d2f3c9 100644 (file)
--- a/libgm2/ChangeLog
+++ b/libgm2/ChangeLog
@@ -1,3 +1,9 @@
+2025-11-23  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       PR modula2/122801
+       * configure: Regenerate.
+       * configure.ac (libtool_VERSION): Assign to 21:0:0.
+
 2025-11-03  Sam James  <sam@gentoo.org>
 
        * configure: Regenerate.