struct hw *me;
struct hw_event *pending;
+ /* The port levels which latch into ilat. */
+ bu32 plat;
+
/* Order after here is important -- matches hardware MMR layout. */
bu32 evt_override, imask, ipend, ilat, iprio;
};
HW_TRACE_READ ();
- dv_store_4 (dest, *valuep);
+ switch (mmr_off)
+ {
+ case mmr_offset(ilat):
+ dv_store_4 (dest, *valuep | cec->plat);
+ break;
+ default:
+ dv_store_4 (dest, *valuep);
+ break;
+ }
return nr_bytes;
}
int source_port, int level)
{
struct bfin_cec *cec = hw_data (me);
- _cec_raise (cec->cpu, cec, my_port);
+ bu32 bit = 1 << my_port;
+
+ if (level)
+ {
+ if (!(cec->plat & bit))
+ {
+ cec->plat |= bit;
+ _cec_raise (cec->cpu, cec, my_port);
+ }
+ }
+ else
+ cec->plat &= ~bit;
}
static void
if (irpten)
goto done; /* All interrupts are masked anyways. */
- ivg = __cec_get_ivg (cec->ilat & cec->imask);
+ ivg = __cec_get_ivg ((cec->plat | cec->ilat) & cec->imask);
if (ivg < 0)
goto done; /* Nothing latched. */