RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds mask instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	mask instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 2c80eeb13e54d9f5234c56fba6698fa1618f959a..03d8ede7c779c4ba40fba994b7aca0bdb18a568e 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1592,3 +1592,29 @@ Disassembly of section .text:
 [      ]+[0-9a-f]+:[   ]+c6861257[     ]+th.vfwredsum.vs[      ]+v4,v8,v12
 [      ]+[0-9a-f]+:[   ]+cc861257[     ]+th.vfwredosum.vs[     ]+v4,v8,v12,v0.t
 [      ]+[0-9a-f]+:[   ]+c4861257[     ]+th.vfwredsum.vs[      ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+66842257[     ]+th.vmcpy.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+6e422257[     ]+th.vmclr.m[   ]+v4
+[      ]+[0-9a-f]+:[   ]+7e422257[     ]+th.vmset.m[   ]+v4
+[      ]+[0-9a-f]+:[   ]+76842257[     ]+th.vmnot.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+66862257[     ]+th.vmand.mm[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+76862257[     ]+th.vmnand.mm[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+62862257[     ]+th.vmandnot.mm[       ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6e862257[     ]+th.vmxor.mm[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+6a862257[     ]+th.vmor.mm[   ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+7a862257[     ]+th.vmnor.mm[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+72862257[     ]+th.vmornot.mm[        ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+7e862257[     ]+th.vmxnor.mm[         ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+52c02557[     ]+th.vmpopc.m[  ]+a0,v12
+[      ]+[0-9a-f]+:[   ]+56c02557[     ]+th.vmfirst.m[         ]+a0,v12
+[      ]+[0-9a-f]+:[   ]+5a80a257[     ]+th.vmsbf.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+5a81a257[     ]+th.vmsif.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+5a812257[     ]+th.vmsof.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+5a882257[     ]+th.viota.m[   ]+v4,v8
+[      ]+[0-9a-f]+:[   ]+5a08a257[     ]+th.vid.v[     ]+v4
+[      ]+[0-9a-f]+:[   ]+50c02557[     ]+th.vmpopc.m[  ]+a0,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+54c02557[     ]+th.vmfirst.m[         ]+a0,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+5880a257[     ]+th.vmsbf.m[   ]+v4,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+5881a257[     ]+th.vmsif.m[   ]+v4,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+58812257[     ]+th.vmsof.m[   ]+v4,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+58882257[     ]+th.viota.m[   ]+v4,v8,v0.t
+[      ]+[0-9a-f]+:[   ]+5808a257[     ]+th.vid.v[     ]+v4,v0.t

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 71f83a25dc6eabf94ca0b9bd5992e6f91971bab1..1c1c27cb6d8c6f20dde006d1da4bcdc2fe7f6bea 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1656,3 +1656,33 @@
        th.vfwredsum.vs v4, v8, v12
        th.vfwredosum.vs v4, v8, v12, v0.t
        th.vfwredsum.vs v4, v8, v12, v0.t
+
+       # Aliases
+       th.vmcpy.m v4, v8
+       th.vmclr.m v4
+       th.vmset.m v4
+       th.vmnot.m v4, v8
+
+       th.vmand.mm v4, v8, v12
+       th.vmnand.mm v4, v8, v12
+       th.vmandnot.mm v4, v8, v12
+       th.vmxor.mm v4, v8, v12
+       th.vmor.mm v4, v8, v12
+       th.vmnor.mm v4, v8, v12
+       th.vmornot.mm v4, v8, v12
+       th.vmxnor.mm v4, v8, v12
+
+       th.vmpopc.m a0, v12
+       th.vmfirst.m a0, v12
+       th.vmsbf.m v4, v8
+       th.vmsif.m v4, v8
+       th.vmsof.m v4, v8
+       th.viota.m v4, v8
+       th.vid.v v4
+       th.vmpopc.m a0, v12, v0.t
+       th.vmfirst.m a0, v12, v0.t
+       th.vmsbf.m v4, v8, v0.t
+       th.vmsif.m v4, v8, v0.t
+       th.vmsof.m v4, v8, v0.t
+       th.viota.m v4, v8, v0.t
+       th.vid.v v4, v0.t

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2e5b4fe63eec526238544ca3802fef477fab96b1..9b4288c8ee22d10b4e4ef428d73e1d90b3d70622 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2945,6 +2945,20 @@
 #define MASK_TH_VFNCVTFXV 0xfc0ff07f
 #define MATCH_TH_VFNCVTFFV 0x880a1057
 #define MASK_TH_VFNCVTFFV 0xfc0ff07f
+#define MATCH_TH_VMPOPCM 0x50002057
+#define MASK_TH_VMPOPCM 0xfc0ff07f
+#define MATCH_TH_VMFIRSTM 0x54002057
+#define MASK_TH_VMFIRSTM 0xfc0ff07f
+#define MATCH_TH_VMSBFM 0x5800a057
+#define MASK_TH_VMSBFM 0xfc0ff07f
+#define MATCH_TH_VMSIFM 0x5801a057
+#define MASK_TH_VMSIFM 0xfc0ff07f
+#define MATCH_TH_VMSOFM 0x58012057
+#define MASK_TH_VMSOFM 0xfc0ff07f
+#define MATCH_TH_VIOTAM 0x58082057
+#define MASK_TH_VIOTAM 0xfc0ff07f
+#define MATCH_TH_VIDV 0x5808a057
+#define MASK_TH_VIDV 0xfdfff07f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 2dde9ca4a0a81dafd5821a6bfb4ef0d512b19323..b9b47cf849e7ffb6abaaa96ee2af37ffe51da988 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2860,6 +2860,25 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFREDMINVS, MASK_VFREDMINVS, match_opcode, 0},
 {"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDOSUMVS, MASK_VFWREDOSUMVS, match_opcode, 0},
 {"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VFWREDUSUMVS, MASK_VFWREDUSUMVS, match_opcode, 0},
+{"th.vmcpy.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMANDMM, MASK_VMANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmclr.m",    0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXORMM, MASK_VMXORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmset.m",    0, INSN_CLASS_XTHEADVECTOR, "Vv", MATCH_VMXNORMM, MASK_VMXNORMM, match_vd_eq_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmnot.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vu", MATCH_VMNANDMM, MASK_VMNANDMM, match_vs1_eq_vs2, INSN_ALIAS},
+{"th.vmand.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDMM, MASK_VMANDMM, match_opcode, 0},
+{"th.vmnand.mm",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNANDMM, MASK_VMNANDMM, match_opcode, 0},
+{"th.vmandnot.mm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMANDNMM, MASK_VMANDNMM, match_opcode, 0},
+{"th.vmxor.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXORMM, MASK_VMXORMM, match_opcode, 0},
+{"th.vmor.mm",    0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORMM, MASK_VMORMM, match_opcode, 0},
+{"th.vmnor.mm",   0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMNORMM, MASK_VMNORMM, match_opcode, 0},
+{"th.vmornot.mm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMORNMM, MASK_VMORNMM, match_opcode, 0},
+{"th.vmxnor.mm",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VMXNORMM, MASK_VMXNORMM, match_opcode, 0},
+{"th.vmpopc.m",   0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMPOPCM, MASK_TH_VMPOPCM, match_opcode, 0},
+{"th.vmfirst.m",  0, INSN_CLASS_XTHEADVECTOR, "d,VtVm", MATCH_TH_VMFIRSTM, MASK_TH_VMFIRSTM, match_opcode, 0},
+{"th.vmsbf.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSBFM, MASK_TH_VMSBFM, match_opcode, 0},
+{"th.vmsif.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSIFM, MASK_TH_VMSIFM, match_opcode, 0},
+{"th.vmsof.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0},
+{"th.viota.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0},
+{"th.vid.v",      0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },