RISC-V: Allow RVV intrinsic for more function target

In previous, we allowed the target(("arch=+v")) for a function with
rv64gc build.  This patch would like to support more arch options as
below:
* zve32x
* zve32f
* zve64x
* zve64f
* zve64d
* zvfhmin
* zvfh
* zvk*
* zvbb

For example, we have sample code as below.
vfloat32m1_t
__attribute__((target("arch=+zve64f")))
test_9 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
{
  return __riscv_vfadd_vv_f32m1 (a, b, vl);
}

It will generate the asm code when build with -O3 -march=rv64gc
test_9:
        vsetvli zero,a0,e32,m1,ta,ma
        vfadd.vv        v8,v8,v9
        ret

Meanwhile, this patch introduces more error handling for the target
attribute.  Take arch=+zve32x with vfloat32m1_t will have error message
"'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension".
And take arch=+zve32f with vfloat16m1_t will have error message
"'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension".

By default, all the RVV types includes the cmdline march will be
registered when include the riscv_vector.h.  And we have sorts of check
during args and return types.

Below test are passed for this patch:
* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New
	struct to hold all intrinisc related flags.
	(riscv_pragma_intrinsic_flags_pollute): New func to pollute
	the intrinsic flags and backup original flags.
	(riscv_pragma_intrinsic_flags_restore): New func to restore
	the flags from the backup intrinsic flags.
	(riscv_pragma_intrinsic): Pollute the flags and register all
	possible builtin types and functions, then restore and reinit.
	* config/riscv/riscv-protos.h (reinit_builtins): New func
	decl to reinit after flags pollution.
	(riscv_option_override): New extern func decl.
	* config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null):
	New func to register builtin types if null.
	(DEF_RVV_TYPE): Ditto.
	(DEF_RVV_TUPLE_TYPE): Ditto.
	(reinit_builtins): New func impl to reinit after flags pollution.
	(expand_builtin): Return
	target rtx after error_at.
	* config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
	func to tell one tree type is integer or not.
	(riscv_vector_float_type_p): New predicate func to tell one tree
	type is float or not.
	(riscv_vector_element_bitsize): New func to get the element bitsize
	of a vector tree type.
	(riscv_vector_required_min_vlen): New func to get the required min vlen
	of a vector tree type.
	(riscv_validate_vector_type): New func to validate the tree type
	is valid on flags.
	(riscv_return_value_is_vector_type_p): Leverage the func
	riscv_validate_vector_type to do the tree type validation.
	(riscv_arguments_is_vector_type_p): Ditto.
	(riscv_override_options_internal): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr109479-1.c: Adjust the existing test
	scenarios and add new error check tests.
	* gcc.target/riscv/rvv/base/pr109479-2.c: Ditto.
	* gcc.target/riscv/rvv/base/pr109479-3.c: Ditto.
	* gcc.target/riscv/rvv/base/pr109479-4.c: Diito.
	* gcc.target/riscv/rvv/base/pr109479-5.c: Diito.
	* gcc.target/riscv/rvv/base/pr109479-6.c: Diito.
	* gcc.target/riscv/rvv/base/user-10.c: Ditto.
	* gcc.target/riscv/rvv/base/user-12.c: Ditto.
	* gcc.target/riscv/rvv/base/user-13.c: Ditto.
	* gcc.target/riscv/rvv/base/user-14.c: Ditto.
	* gcc.target/riscv/rvv/base/user-15.c: Ditto.
	* gcc.target/riscv/rvv/base/user-2.c: Ditto.
	* gcc.target/riscv/rvv/base/user-3.c: Ditto.
	* gcc.target/riscv/rvv/base/user-5.c: Ditto.
	* gcc.target/riscv/rvv/base/user-6.c: Ditto.
	* gcc.target/riscv/rvv/base/user-9.c: Ditto.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 01314037461ed780d12f20e4410f1028ab97883d..43c8eecbb6fff360dc338b975404e705d1ac3c67 100644 (file)
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -34,6 +34,72 @@ along with GCC; see the file COPYING3.  If not see
 
 #define builtin_define(TXT) cpp_define (pfile, TXT)
 
+struct pragma_intrinsic_flags
+{
+  int intrinsic_target_flags;
+
+  int intrinsic_riscv_vector_elen_flags;
+  int intrinsic_riscv_zvl_flags;
+  int intrinsic_riscv_zvb_subext;
+  int intrinsic_riscv_zvk_subext;
+};
+
+static void
+riscv_pragma_intrinsic_flags_pollute (struct pragma_intrinsic_flags *flags)
+{
+  flags->intrinsic_target_flags = target_flags;
+  flags->intrinsic_riscv_vector_elen_flags = riscv_vector_elen_flags;
+  flags->intrinsic_riscv_zvl_flags = riscv_zvl_flags;
+  flags->intrinsic_riscv_zvb_subext = riscv_zvb_subext;
+  flags->intrinsic_riscv_zvk_subext = riscv_zvk_subext;
+
+  target_flags = target_flags
+    | MASK_VECTOR;
+
+  riscv_zvl_flags = riscv_zvl_flags
+    | MASK_ZVL32B
+    | MASK_ZVL64B
+    | MASK_ZVL128B;
+
+  riscv_vector_elen_flags = riscv_vector_elen_flags
+    | MASK_VECTOR_ELEN_32
+    | MASK_VECTOR_ELEN_64
+    | MASK_VECTOR_ELEN_FP_16
+    | MASK_VECTOR_ELEN_FP_32
+    | MASK_VECTOR_ELEN_FP_64;
+
+  riscv_zvb_subext = riscv_zvb_subext
+    | MASK_ZVBB
+    | MASK_ZVBC
+    | MASK_ZVKB;
+
+  riscv_zvk_subext = riscv_zvk_subext
+    | MASK_ZVKG
+    | MASK_ZVKNED
+    | MASK_ZVKNHA
+    | MASK_ZVKNHB
+    | MASK_ZVKSED
+    | MASK_ZVKSH
+    | MASK_ZVKN
+    | MASK_ZVKNC
+    | MASK_ZVKNG
+    | MASK_ZVKS
+    | MASK_ZVKSC
+    | MASK_ZVKSG
+    | MASK_ZVKT;
+}
+
+static void
+riscv_pragma_intrinsic_flags_restore (struct pragma_intrinsic_flags *flags)
+{
+  target_flags = flags->intrinsic_target_flags;
+
+  riscv_vector_elen_flags = flags->intrinsic_riscv_vector_elen_flags;
+  riscv_zvl_flags = flags->intrinsic_riscv_zvl_flags;
+  riscv_zvb_subext = flags->intrinsic_riscv_zvb_subext;
+  riscv_zvk_subext = flags->intrinsic_riscv_zvk_subext;
+}
+
 static int
 riscv_ext_version_value (unsigned major, unsigned minor)
 {
@@ -201,20 +267,20 @@ riscv_pragma_intrinsic (cpp_reader *)
   if (strcmp (name, "vector") == 0
       || strcmp (name, "xtheadvector") == 0)
     {
-      if (TARGET_VECTOR)
-       riscv_vector::handle_pragma_vector ();
-      else /* Indicates riscv_vector.h is included but v is missing in arch  */
-       {
-         /* To make the the rvv types and intrinsic API available for the
-            target("arch=+v") attribute,  we need to temporally enable the
-            TARGET_VECTOR, and disable it after all initialized.  */
-         target_flags |= MASK_VECTOR;
-
-         riscv_vector::init_builtins ();
-         riscv_vector::handle_pragma_vector ();
-
-         target_flags &= ~MASK_VECTOR;
-       }
+      struct pragma_intrinsic_flags backup_flags;
+
+      riscv_pragma_intrinsic_flags_pollute (&backup_flags);
+
+      riscv_option_override ();
+      init_adjust_machine_modes ();
+      riscv_vector::reinit_builtins ();
+      riscv_vector::handle_pragma_vector ();
+
+      riscv_pragma_intrinsic_flags_restore (&backup_flags);
+
+      /* Re-initialize after the flags are restored.  */
+      riscv_option_override ();
+      init_adjust_machine_modes ();
     }
   else
     error ("unknown %<#pragma riscv intrinsic%> option %qs", name);

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index b87355938052a3a0ca9107774bb3a683c85b74d9..4677d9c46cd2217911a9cddaea221efaf571fd1f 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -546,6 +546,7 @@ enum avl_type
 };
 /* Routines implemented in riscv-vector-builtins.cc.  */
 void init_builtins (void);
+void reinit_builtins (void);
 const char *mangle_builtin_type (const_tree);
 tree lookup_vector_type_attribute (const_tree);
 bool builtin_type_p (const_tree);
@@ -762,6 +763,7 @@ extern bool
 riscv_option_valid_attribute_p (tree, tree, tree, int);
 extern void
 riscv_override_options_internal (struct gcc_options *);
+extern void riscv_option_override (void);
 
 struct riscv_tune_param;
 /* Information about one micro-arch we know about.  */

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index db9246eed2d5955519ecd3096da3e36fe707e026..53ccea7889e2251ab8f4ea111ebfe6b65fe73552 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3123,6 +3123,36 @@ register_builtin_types ()
 #include "riscv-vector-builtins.def"
 }
 
+/* Similar as register_builtin_types but perform the registration if and
+   only if the element of abi_vector_type is NULL_TREE.  */
+static void
+register_builtin_types_on_null ()
+{
+  /* Get type node from get_typenode_from_name to prevent we have different type
+     node define in different target libraries, e.g. int32_t defined as
+     `long` in RV32/newlib-stdint, but `int` for RV32/glibc-stdint.h.
+     NOTE: uint[16|32|64]_type_node already defined in tree.h.  */
+  tree int8_type_node = get_typenode_from_name (INT8_TYPE);
+  tree uint8_type_node = get_typenode_from_name (UINT8_TYPE);
+  tree int16_type_node = get_typenode_from_name (INT16_TYPE);
+  tree int32_type_node = get_typenode_from_name (INT32_TYPE);
+  tree int64_type_node = get_typenode_from_name (INT64_TYPE);
+
+  machine_mode mode;
+#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE,         \
+                    ARGS...)                                                  \
+  mode = VECTOR_MODE##mode;                                                    \
+  if (abi_vector_types[VECTOR_TYPE_##NAME] == NULL_TREE)                       \
+    register_builtin_type (VECTOR_TYPE_##NAME, SCALAR_TYPE##_type_node, mode);
+
+#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, SCALAR_TYPE,  \
+                          NF, VECTOR_SUFFIX)                                  \
+  if (abi_vector_types[VECTOR_TYPE_##NAME] == NULL_TREE)                       \
+    register_tuple_type (VECTOR_TYPE_##NAME, VECTOR_TYPE_##SUBPART_TYPE,       \
+                        SCALAR_TYPE##_type_node, NF);
+#include "riscv-vector-builtins.def"
+}
+
 /* Register vector type TYPE under its risv_vector.h name.  */
 static void
 register_vector_type (vector_type_index type)
@@ -4419,6 +4449,22 @@ init_builtins ()
     handle_pragma_vector ();
 }
 
+/* Reinitialize builtins similar to init_builtins,  but only the null
+   builtin types will be registered.  */
+void
+reinit_builtins ()
+{
+  rvv_switcher rvv;
+
+  if (!TARGET_VECTOR)
+    return;
+
+  register_builtin_types_on_null ();
+
+  if (in_lto_p)
+    handle_pragma_vector ();
+}
+
 /* Implement TARGET_VERIFY_TYPE_CONTEXT for RVV types.  */
 bool
 verify_type_context (location_t loc, type_context_kind context, const_tree type,
@@ -4588,8 +4634,11 @@ expand_builtin (unsigned int code, tree exp, rtx target)
   registered_function &rfn = *(*registered_functions)[code];
 
   if (!TARGET_VECTOR)
-    error_at (EXPR_LOCATION (exp),
-             "built-in function %qE requires the V ISA extension", exp);
+    {
+      error_at (EXPR_LOCATION (exp),
+               "built-in function %qE requires the V ISA extension", exp);
+      return target;
+    }
 
   return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
 }

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fe9976bfffe980233b667b31ca2a42ab18bcfb17..2a71badfdc9fae5800cfab02711a8c4a831fdd72 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5459,6 +5459,152 @@ riscv_v_abi ()
   return v_abi;
 }
 
+static bool
+riscv_vector_int_type_p (const_tree type)
+{
+  machine_mode mode = TYPE_MODE (type);
+
+  if (VECTOR_MODE_P (mode))
+    return INTEGRAL_MODE_P (GET_MODE_INNER (mode));
+
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+  return strstr (name, "int") != NULL || strstr (name, "uint") != NULL;
+}
+
+static bool
+riscv_vector_float_type_p (const_tree type)
+{
+  machine_mode mode = TYPE_MODE (type);
+
+  if (VECTOR_MODE_P (mode))
+    return FLOAT_MODE_P (GET_MODE_INNER (mode));
+
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+  return strstr (name, "vfloat") != NULL;
+}
+
+static unsigned
+riscv_vector_element_bitsize (const_tree type)
+{
+  machine_mode mode = TYPE_MODE (type);
+
+  if (VECTOR_MODE_P (mode))
+    return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+
+  if (strstr (name, "bool") != NULL)
+    return 1;
+  else if (strstr (name, "int8") != NULL)
+    return 8;
+  else if (strstr (name, "int16") != NULL || strstr (name, "float16") != NULL)
+    return 16;
+  else if (strstr (name, "int32") != NULL || strstr (name, "float32") != NULL)
+    return 32;
+  else if (strstr (name, "int64") != NULL || strstr (name, "float64") != NULL)
+    return 64;
+
+  gcc_unreachable ();
+}
+
+static unsigned
+riscv_vector_required_min_vlen (const_tree type)
+{
+  machine_mode mode = TYPE_MODE (type);
+
+  if (riscv_v_ext_mode_p (mode))
+    return TARGET_MIN_VLEN;
+
+  unsigned element_bitsize = riscv_vector_element_bitsize (type);
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+
+  if (strstr (name, "bool64") != NULL)
+    return element_bitsize * 64;
+  else if (strstr (name, "bool32") != NULL)
+    return element_bitsize * 32;
+  else if (strstr (name, "bool16") != NULL)
+    return element_bitsize * 16;
+  else if (strstr (name, "bool8") != NULL)
+    return element_bitsize * 8;
+  else if (strstr (name, "bool4") != NULL)
+    return element_bitsize * 4;
+  else if (strstr (name, "bool2") != NULL)
+    return element_bitsize * 2;
+
+  if (strstr (name, "mf8") != NULL)
+    return element_bitsize * 8;
+  else if (strstr (name, "mf4") != NULL)
+    return element_bitsize * 4;
+  else if (strstr (name, "mf2") != NULL)
+    return element_bitsize * 2;
+
+  return element_bitsize;
+}
+
+static void
+riscv_validate_vector_type (const_tree type, const char *hint)
+{
+  gcc_assert (riscv_vector_type_p (type));
+
+  if (!TARGET_VECTOR)
+    {
+      error_at (input_location, "%s %qT requires the V ISA extension",
+               hint, type);
+      return;
+    }
+
+  unsigned element_bitsize = riscv_vector_element_bitsize (type);
+  bool int_type_p = riscv_vector_int_type_p (type);
+
+  if (int_type_p && element_bitsize == 64
+    && !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+               "%s %qT requires the zve64x, zve64f, zve64d or v ISA extension",
+               hint, type);
+      return;
+    }
+
+  bool float_type_p = riscv_vector_float_type_p (type);
+
+  if (float_type_p && element_bitsize == 16
+    && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+               "%s %qT requires the zvfhmin or zvfh ISA extension",
+               hint, type);
+      return;
+    }
+
+  if (float_type_p && element_bitsize == 32
+    && !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+               "%s %qT requires the zve32f, zve64f, zve64d or v ISA extension",
+               hint, type);
+      return;
+    }
+
+  if (float_type_p && element_bitsize == 64
+    && !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+               "%s %qT requires the zve64d or v ISA extension", hint, type);
+      return;
+    }
+
+  unsigned required_min_vlen = riscv_vector_required_min_vlen (type);
+
+  if (TARGET_MIN_VLEN < required_min_vlen)
+    {
+      error_at (
+       input_location,
+       "%s %qT requires the minimal vector length %qd but %qd is given",
+       hint, type, required_min_vlen, TARGET_MIN_VLEN);
+      return;
+    }
+}
+
 /* Return true if a function with type FNTYPE returns its value in
    RISC-V V registers.  */
 
@@ -5469,9 +5615,7 @@ riscv_return_value_is_vector_type_p (const_tree fntype)
 
   if (riscv_vector_type_p (return_type))
     {
-      if (!TARGET_VECTOR)
-       error_at (input_location,
-                 "return type %qT requires the V ISA extension", return_type);
+      riscv_validate_vector_type (return_type, "return type");
       return true;
     }
   else
@@ -5490,10 +5634,7 @@ riscv_arguments_is_vector_type_p (const_tree fntype)
       tree arg_type = TREE_VALUE (chain);
       if (riscv_vector_type_p (arg_type))
        {
-         if (!TARGET_VECTOR)
-           error_at (input_location,
-                     "argument type %qT requires the V ISA extension",
-                     arg_type);
+         riscv_validate_vector_type (arg_type, "argument type");
          return true;
        }
     }
@@ -9107,7 +9248,7 @@ riscv_override_options_internal (struct gcc_options *opts)
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
 
-static void
+void
 riscv_option_override (void)
 {
 #ifdef SUBTARGET_OVERRIDE_OPTIONS

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c
index a13cc12c5435714bd698d913c662e292a219a2a7..1bd7efe61f27fc359dc7a8ee79926b6c0a05521e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-1.c
@@ -3,11 +3,24 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__rvv_int64m1_t'} } */
-void foo1 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__rvv_uint64m1_t'} } */
-void foo2 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__rvv_int64m2_t'} } */
-void foo3 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2_t'} } */
-void foo4 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__rvv_int64m4_t'} } */
-void foo5 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__rvv_uint64m4_t'} } */
-void foo6 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__rvv_int64m8_t'} } */
-void foo7 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__rvv_uint64m8_t'} } */
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo0 () {__rvv_int64m1_t t;}
+void foo1 () {__rvv_uint64m1_t t;}
+void foo2 () {__rvv_int64m2_t t;}
+void foo3 () {__rvv_uint64m2_t t;}
+void foo4 () {__rvv_int64m4_t t;}
+void foo5 () {__rvv_uint64m4_t t;}
+void foo6 () {__rvv_int64m8_t t;}
+void foo7 () {__rvv_uint64m8_t t;}
+
+void new_foo0 (__rvv_int64m1_t t) { }  /* { dg-error {argument type '__rvv_int64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo1 (__rvv_uint64m1_t t) { } /* { dg-error {argument type '__rvv_uint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo2 (__rvv_int64m2_t t) { }  /* { dg-error {argument type '__rvv_int64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo3 (__rvv_uint64m2_t t) { } /* { dg-error {argument type '__rvv_uint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo4 (__rvv_int64m4_t t) { }  /* { dg-error {argument type '__rvv_int64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo5 (__rvv_uint64m4_t t) { } /* { dg-error {argument type '__rvv_uint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo6 (__rvv_int64m8_t t) { }  /* { dg-error {argument type '__rvv_int64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo7 (__rvv_uint64m8_t t) { } /* { dg-error {argument type '__rvv_uint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c
index dd6bcb0f54851567bd6147ff151cf847f48c0a08..ce6a62d1405f43175e29c7fe6f5e0ef8521f2750 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-2.c
@@ -3,11 +3,24 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {vint64m1_t t;} /* { dg-error {unknown type name 'vint64m1_t'} } */
-void foo1 () {vuint64m1_t t;} /* { dg-error {unknown type name 'vuint64m1_t'} } */
-void foo2 () {vint64m2_t t;} /* { dg-error {unknown type name 'vint64m2_t'} } */
-void foo3 () {vuint64m2_t t;} /* { dg-error {unknown type name 'vuint64m2_t'} } */
-void foo4 () {vint64m4_t t;} /* { dg-error {unknown type name 'vint64m4_t'} } */
-void foo5 () {vuint64m4_t t;} /* { dg-error {unknown type name 'vuint64m4_t'} } */
-void foo6 () {vint64m8_t t;} /* { dg-error {unknown type name 'vint64m8_t'} } */
-void foo7 () {vuint64m8_t t;} /* { dg-error {unknown type name 'vuint64m8_t'} } */
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo0 () {vint64m1_t t;}
+void foo1 () {vuint64m1_t t;}
+void foo2 () {vint64m2_t t;}
+void foo3 () {vuint64m2_t t;}
+void foo4 () {vint64m4_t t;}
+void foo5 () {vuint64m4_t t;}
+void foo6 () {vint64m8_t t;}
+void foo7 () {vuint64m8_t t;}
+
+void new_foo0 (vint64m1_t t) { }  /* { dg-error {argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo1 (vuint64m1_t t) { } /* { dg-error {argument type 'vuint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo2 (vint64m2_t t) { }  /* { dg-error {argument type 'vint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo3 (vuint64m2_t t) { } /* { dg-error {argument type 'vuint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo4 (vint64m4_t t) { }  /* { dg-error {argument type 'vint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo5 (vuint64m4_t t) { } /* { dg-error {argument type 'vuint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo6 (vint64m8_t t) { }  /* { dg-error {argument type 'vint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo7 (vuint64m8_t t) { } /* { dg-error {argument type 'vuint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c
index 01e86223da9f6c56e0b1ac801369621108598b49..5c0cd1b1f7f984aec9cf27ebd505d51f2a255dd2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-3.c
@@ -3,18 +3,38 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {__rvv_bool64_t t;} /* { dg-error {unknown type name '__rvv_bool64_t'} } */
-void foo1 () {__rvv_int8mf8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8_t'} } */
-void foo2 () {__rvv_uint8mf8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8_t'} } */
-void foo3 () {__rvv_int16mf4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4_t'} } */
-void foo4 () {__rvv_uint16mf4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4_t'} } */
-void foo5 () {__rvv_int32mf2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2_t'} } */
-void foo6 () {__rvv_uint32mf2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2_t'} } */
-void foo7 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__rvv_int64m1_t'} } */
-void foo8 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__rvv_uint64m1_t'} } */
-void foo9 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__rvv_int64m2_t'} } */
-void foo10 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2_t'} } */
-void foo11 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__rvv_int64m4_t'} } */
-void foo12 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__rvv_uint64m4_t'} } */
-void foo13 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__rvv_int64m8_t'} } */
-void foo14 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__rvv_uint64m8_t'} } */
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo0 () {__rvv_bool64_t t;}
+void foo1 () {__rvv_int8mf8_t t;}
+void foo2 () {__rvv_uint8mf8_t t;}
+void foo3 () {__rvv_int16mf4_t t;}
+void foo4 () {__rvv_uint16mf4_t t;}
+void foo5 () {__rvv_int32mf2_t t;}
+void foo6 () {__rvv_uint32mf2_t t;}
+void foo7 () {__rvv_int64m1_t t;}
+void foo8 () {__rvv_uint64m1_t t;}
+void foo9 () {__rvv_int64m2_t t;}
+void foo10 () {__rvv_uint64m2_t t;}
+void foo11 () {__rvv_int64m4_t t;}
+void foo12 () {__rvv_uint64m4_t t;}
+void foo13 () {__rvv_int64m8_t t;}
+void foo14 () {__rvv_uint64m8_t t;}
+
+void new_foo0 (__rvv_bool64_t t) { }    /* { dg-error {argument type '__rvv_bool64_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo1 (__rvv_int8mf8_t t) { }   /* { dg-error {argument type '__rvv_int8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo2 (__rvv_uint8mf8_t t) { }  /* { dg-error {argument type '__rvv_uint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo3 (__rvv_int16mf4_t t) { }  /* { dg-error {argument type '__rvv_int16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo4 (__rvv_uint16mf4_t t) { } /* { dg-error {argument type '__rvv_uint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo5 (__rvv_int32mf2_t t) { }  /* { dg-error {argument type '__rvv_int32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo6 (__rvv_uint32mf2_t t) { } /* { dg-error {argument type '__rvv_uint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo7 (__rvv_int64m1_t t) { }   /* { dg-error {argument type '__rvv_int64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo8 (__rvv_uint64m1_t t) { }  /* { dg-error {argument type '__rvv_uint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo9 (__rvv_int64m2_t t) { }   /* { dg-error {argument type '__rvv_int64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo10 (__rvv_uint64m2_t t) { } /* { dg-error {argument type '__rvv_uint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo11 (__rvv_int64m4_t t) { }  /* { dg-error {argument type '__rvv_int64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo12 (__rvv_uint64m4_t t) { } /* { dg-error {argument type '__rvv_uint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo13 (__rvv_int64m8_t t) { }  /* { dg-error {argument type '__rvv_int64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo14 (__rvv_uint64m8_t t) { } /* { dg-error {argument type '__rvv_uint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c
index 62385b8dcd1b8b945be0d5fb7c3dc551a6e4c022..48e1f278e706023d615967bb08d4504e56303607 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-4.c
@@ -3,18 +3,39 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {vbool64_t t;} /* { dg-error {unknown type name 'vbool64_t'} } */
-void foo1 () {vint8mf8_t t;} /* { dg-error {unknown type name 'vint8mf8_t'} } */
-void foo2 () {vuint8mf8_t t;} /* { dg-error {unknown type name 'vuint8mf8_t'} } */
-void foo3 () {vint16mf4_t t;} /* { dg-error {unknown type name 'vint16mf4_t'} } */
-void foo4 () {vuint16mf4_t t;} /* { dg-error {unknown type name 'vuint16mf4_t'} } */
-void foo5 () {vint32mf2_t t;} /* { dg-error {unknown type name 'vint32mf2_t'} } */
-void foo6 () {vuint32mf2_t t;} /* { dg-error {unknown type name 'vuint32mf2_t'} } */
-void foo7 () {vint64m1_t t;} /* { dg-error {unknown type name 'vint64m1_t'} } */
-void foo8 () {vuint64m1_t t;} /* { dg-error {unknown type name 'vuint64m1_t'} } */
-void foo9 () {vint64m2_t t;} /* { dg-error {unknown type name 'vint64m2_t'} } */
-void foo10 () {vuint64m2_t t;} /* { dg-error {unknown type name 'vuint64m2_t'} } */
-void foo11 () {vint64m4_t t;} /* { dg-error {unknown type name 'vint64m4_t'} } */
-void foo12 () {vuint64m4_t t;} /* { dg-error {unknown type name 'vuint64m4_t'} } */
-void foo13 () {vint64m8_t t;} /* { dg-error {unknown type name 'vint64m8_t'} } */
-void foo14 () {vuint64m8_t t;} /* { dg-error {unknown type name 'vuint64m8_t'} } */
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo0 () {vbool64_t t;}
+void foo1 () {vint8mf8_t t;}
+void foo2 () {vuint8mf8_t t;}
+void foo3 () {vint16mf4_t t;}
+void foo4 () {vuint16mf4_t t;}
+void foo5 () {vint32mf2_t t;}
+void foo6 () {vuint32mf2_t t;}
+void foo7 () {vint64m1_t t;}
+void foo8 () {vuint64m1_t t;}
+void foo9 () {vint64m2_t t;}
+void foo10 () {vuint64m2_t t;}
+void foo11 () {vint64m4_t t;}
+void foo12 () {vuint64m4_t t;}
+void foo13 () {vint64m8_t t;}
+void foo14 () {vuint64m8_t t;}
+
+void new_foo0 (vbool64_t t) { }    /* { dg-error {argument type 'vbool64_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo1 (vint8mf8_t t) { }   /* { dg-error {argument type 'vint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo2 (vuint8mf8_t t) { }  /* { dg-error {argument type 'vuint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo3 (vint16mf4_t t) { }  /* { dg-error {argument type 'vint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo4 (vuint16mf4_t t) { } /* { dg-error {argument type 'vuint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo5 (vint32mf2_t t) { }  /* { dg-error {argument type 'vint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo6 (vuint32mf2_t t) { } /* { dg-error {argument type 'vuint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_foo7 (vint64m1_t t) { }   /* { dg-error {argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo8 (vuint64m1_t t) { }  /* { dg-error {argument type 'vuint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo9 (vint64m2_t t) { }   /* { dg-error {argument type 'vint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo10 (vuint64m2_t t) { } /* { dg-error {argument type 'vuint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo11 (vint64m4_t t) { }  /* { dg-error {argument type 'vint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo12 (vuint64m4_t t) { } /* { dg-error {argument type 'vuint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo13 (vint64m8_t t) { }  /* { dg-error {argument type 'vint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo14 (vuint64m8_t t) { } /* { dg-error {argument type 'vuint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c
index 26a0a742965f2ddbc0feb6b6aa61ba720eec9354..af237f5d759e7389a4631e5fb178a3afcc8f2fa7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-5.c
@@ -3,6 +3,10 @@
 
 #include "riscv_vector.h"
 
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
 void foo0 () {__rvv_bool64_t t;}
 void foo1 () {__rvv_int8mf8_t t;}
 void foo2 () {__rvv_uint8mf8_t t;}
@@ -10,11 +14,28 @@ void foo3 () {__rvv_int16mf4_t t;}
 void foo4 () {__rvv_uint16mf4_t t;}
 void foo5 () {__rvv_int32mf2_t t;}
 void foo6 () {__rvv_uint32mf2_t t;}
-void foo7 () {__rvv_int64m1_t t;} /* { dg-error {unknown type name '__rvv_int64m1_t'} } */
-void foo8 () {__rvv_uint64m1_t t;} /* { dg-error {unknown type name '__rvv_uint64m1_t'} } */
-void foo9 () {__rvv_int64m2_t t;} /* { dg-error {unknown type name '__rvv_int64m2_t'} } */
-void foo10 () {__rvv_uint64m2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2_t'} } */
-void foo11 () {__rvv_int64m4_t t;} /* { dg-error {unknown type name '__rvv_int64m4_t'} } */
-void foo12 () {__rvv_uint64m4_t t;} /* { dg-error {unknown type name '__rvv_uint64m4_t'} } */
-void foo13 () {__rvv_int64m8_t t;} /* { dg-error {unknown type name '__rvv_int64m8_t'} } */
-void foo14 () {__rvv_uint64m8_t t;} /* { dg-error {unknown type name '__rvv_uint64m8_t'} } */
+void foo7 () {__rvv_int64m1_t t;}
+void foo8 () {__rvv_uint64m1_t t;}
+void foo9 () {__rvv_int64m2_t t;}
+void foo10 () {__rvv_uint64m2_t t;}
+void foo11 () {__rvv_int64m4_t t;}
+void foo12 () {__rvv_uint64m4_t t;}
+void foo13 () {__rvv_int64m8_t t;}
+void foo14 () {__rvv_uint64m8_t t;}
+
+void new_foo0 (__rvv_bool64_t t) { }
+void new_foo1 (__rvv_int8mf8_t t) { }
+void new_foo2 (__rvv_uint8mf8_t t) { }
+void new_foo3 (__rvv_int16mf4_t t) { }
+void new_foo4 (__rvv_uint16mf4_t t) { }
+void new_foo5 (__rvv_int32mf2_t t) { }
+void new_foo6 (__rvv_uint32mf2_t t) { }
+
+void new_foo7 (__rvv_int64m1_t t) { }   /* { dg-error {argument type '__rvv_int64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo8 (__rvv_uint64m1_t t) { }  /* { dg-error {argument type '__rvv_uint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo9 (__rvv_int64m2_t t) { }   /* { dg-error {argument type '__rvv_int64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo10 (__rvv_uint64m2_t t) { } /* { dg-error {argument type '__rvv_uint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo11 (__rvv_int64m4_t t) { }  /* { dg-error {argument type '__rvv_int64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo12 (__rvv_uint64m4_t t) { } /* { dg-error {argument type '__rvv_uint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo13 (__rvv_int64m8_t t) { }  /* { dg-error {argument type '__rvv_int64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo14 (__rvv_uint64m8_t t) { } /* { dg-error {argument type '__rvv_uint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c
index eb66f3ea2bd4d7967e34777c792c1fd4eaba3649..2779fbda053ea436d3ddfe3ec19e1fbc13358b5a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109479-6.c
@@ -10,11 +10,28 @@ void foo3 () {vint16mf4_t t;}
 void foo4 () {vuint16mf4_t t;}
 void foo5 () {vint32mf2_t t;}
 void foo6 () {vuint32mf2_t t;}
-void foo7 () {vint64m1_t t;} /* { dg-error {unknown type name 'vint64m1_t'} } */
-void foo8 () {vuint64m1_t t;} /* { dg-error {unknown type name 'vuint64m1_t'} } */
-void foo9 () {vint64m2_t t;} /* { dg-error {unknown type name 'vint64m2_t'} } */
-void foo10 () {vuint64m2_t t;} /* { dg-error {unknown type name 'vuint64m2_t'} } */
-void foo11 () {vint64m4_t t;} /* { dg-error {unknown type name 'vint64m4_t'} } */
-void foo12 () {vuint64m4_t t;} /* { dg-error {unknown type name 'vuint64m4_t'} } */
-void foo13 () {vint64m8_t t;} /* { dg-error {unknown type name 'vint64m8_t'} } */
-void foo14 () {vuint64m8_t t;} /* { dg-error {unknown type name 'vuint64m8_t'} } */
+void foo7 () {vint64m1_t t;}
+void foo8 () {vuint64m1_t t;}
+void foo9 () {vint64m2_t t;}
+void foo10 () {vuint64m2_t t;}
+void foo11 () {vint64m4_t t;}
+void foo12 () {vuint64m4_t t;}
+void foo13 () {vint64m8_t t;}
+void foo14 () {vuint64m8_t t;}
+
+void new_foo0 (vbool64_t t) { }
+void new_foo1 (vint8mf8_t t) { }
+void new_foo2 (vuint8mf8_t t) { }
+void new_foo3 (vint16mf4_t t) { }
+void new_foo4 (vuint16mf4_t t) { }
+void new_foo5 (vint32mf2_t t) { }
+void new_foo6 (vuint32mf2_t t) { }
+
+void new_foo7 (vint64m1_t t) { }   /* { dg-error {argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo8 (vuint64m1_t t) { }  /* { dg-error {argument type 'vuint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo9 (vint64m2_t t) { }   /* { dg-error {argument type 'vint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo10 (vuint64m2_t t) { } /* { dg-error {argument type 'vuint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo11 (vint64m4_t t) { }  /* { dg-error {argument type 'vint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo12 (vuint64m4_t t) { } /* { dg-error {argument type 'vuint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo13 (vint64m8_t t) { }  /* { dg-error {argument type 'vint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo14 (vuint64m8_t t) { } /* { dg-error {argument type 'vuint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c
new file mode 100644 (file)
index 0000000..3e68444
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+v,+zvfh")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c
new file mode 100644 (file)
index 0000000..df05307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c
@@ -0,0 +1,26 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve32x")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve32x")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c
new file mode 100644 (file)
index 0000000..51a9188
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c
@@ -0,0 +1,33 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve32f")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve32f")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve32f")))
+test_4 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c
new file mode 100644 (file)
index 0000000..994b1c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c
@@ -0,0 +1,33 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64x")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64x")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64x")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c
new file mode 100644 (file)
index 0000000..caa2a10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c
@@ -0,0 +1,40 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64f")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64f")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64f")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64f")))
+test_5 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c
new file mode 100644 (file)
index 0000000..72a2be6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c
@@ -0,0 +1,47 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64d")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64d")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64d")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64d")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64d")))
+test_5 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64d")))
+test_6 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c
new file mode 100644 (file)
index 0000000..dabdcf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v,+zvfhmin")))
+test_1 (vfloat16mf2_t a, size_t vl)
+{
+  return __riscv_vfwcvt_f_f_v_f32m1 (a, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
new file mode 100644 (file)
index 0000000..a064417
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
new file mode 100644 (file)
index 0000000..61d3fb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
new file mode 100644 (file)
index 0000000..bfc26f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
new file mode 100644 (file)
index 0000000..35a2924
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
new file mode 100644 (file)
index 0000000..e3aef33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
new file mode 100644 (file)
index 0000000..b5a894e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
new file mode 100644 (file)
index 0000000..7267fa3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
new file mode 100644 (file)
index 0000000..5a7c448
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
new file mode 100644 (file)
index 0000000..f1241cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
new file mode 100644 (file)
index 0000000..2738a29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
new file mode 100644 (file)
index 0000000..8610000
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
new file mode 100644 (file)
index 0000000..7eaa6ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
new file mode 100644 (file)
index 0000000..eb74e33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64d")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c
new file mode 100644 (file)
index 0000000..f68b462
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-30.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c
new file mode 100644 (file)
index 0000000..2f146cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-31.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+v")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c
new file mode 100644 (file)
index 0000000..737b5b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-32.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c
new file mode 100644 (file)
index 0000000..559e90e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-33.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zvfh")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c
new file mode 100644 (file)
index 0000000..91ee510
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-34.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+v")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c
new file mode 100644 (file)
index 0000000..ec184cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-35.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c
new file mode 100644 (file)
index 0000000..a37f67c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-36.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64d")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c
new file mode 100644 (file)
index 0000000..3d62027
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-37.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zvfh")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c
new file mode 100644 (file)
index 0000000..9b8a9cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-38.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
new file mode 100644 (file)
index 0000000..67469a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c
new file mode 100644 (file)
index 0000000..ce89391
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-40.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c
new file mode 100644 (file)
index 0000000..8836cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-41.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zve64d -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zvfh")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
new file mode 100644 (file)
index 0000000..57e542d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
new file mode 100644 (file)
index 0000000..7fb6b20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
new file mode 100644 (file)
index 0000000..ce6f97d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
new file mode 100644 (file)
index 0000000..dbf92a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
new file mode 100644 (file)
index 0000000..6d2e4e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c
new file mode 100644 (file)
index 0000000..94bbcb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-47.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+__attribute__((target("arch=+zvbb")))
+test_1 (vuint32m1_t a, vuint32m1_t b, size_t vl)
+{
+  return __riscv_vandn_vv_u32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c
new file mode 100644 (file)
index 0000000..054b763
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-48.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+__attribute__((target("arch=+zvknha")))
+test_1 (vuint32m1_t a, vuint32m1_t b, vuint32m1_t c, size_t vl)
+{
+  return __riscv_vsha2ch_vv_u32m1 (a, b, c, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c
new file mode 100644 (file)
index 0000000..b2e6658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-49.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m2_t
+__attribute__((target("arch=+zvksh")))
+test_1 (vuint32m2_t a, vuint32m2_t b, size_t vl)
+{
+  return __riscv_vsm3me_vv_u32m2 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c
new file mode 100644 (file)
index 0000000..8574cd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-50.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+__attribute__((target("arch=+zvkned")))
+test_1 (vuint32m1_t a, vuint32m1_t b, size_t vl)
+{
+  return __riscv_vaesdm_vv_u32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c
new file mode 100644 (file)
index 0000000..e27b4d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-51.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+__attribute__((target("arch=+zvkg")))
+test_1 (vuint32m1_t a, vuint32m1_t b, size_t vl)
+{
+  return __riscv_vgmul_vv_u32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c
new file mode 100644 (file)
index 0000000..2213c6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-52.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m2_t
+__attribute__((target("arch=+zvksed")))
+test_1 (vuint32m2_t a, vuint32m2_t b, size_t vl)
+{
+  return __riscv_vsm4r_vv_u32m2 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c
new file mode 100644 (file)
index 0000000..66901cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-53.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+__attribute__((target("arch=+zvknhb")))
+test_1 (vuint32m1_t a, vuint32m1_t b, vuint32m1_t c, size_t vl)
+{
+  return __riscv_vsha2ch_vv_u32m1 (a, b, c, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c
new file mode 100644 (file)
index 0000000..0764f40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c
@@ -0,0 +1,12 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c
index fdc28c77426d27b7c8ddd3cd70c79da61015df38..6bb9460d6d23602ed7467b15ce80aeccc46beaf9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c
@@ -193,14 +193,31 @@ void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
 void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
 void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
 void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void new_f_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c
index 332ff7627b6fc9e2d1f7d90f33fc587233225865..2f2c150eeb00e3a15907187acb48a98aa1cdb350 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c
@@ -3,20 +3,20 @@
 
 #include "riscv_vector.h"
 
-void f_vint8mf8x2_t () {vint8mf8x2_t t;} /* { dg-error {unknown type name 'vint8mf8x2_t'} } */
-void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} /* { dg-error {unknown type name 'vuint8mf8x2_t'} } */
-void f_vint8mf8x3_t () {vint8mf8x3_t t;} /* { dg-error {unknown type name 'vint8mf8x3_t'} } */
-void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} /* { dg-error {unknown type name 'vuint8mf8x3_t'} } */
-void f_vint8mf8x4_t () {vint8mf8x4_t t;} /* { dg-error {unknown type name 'vint8mf8x4_t'} } */
-void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} /* { dg-error {unknown type name 'vuint8mf8x4_t'} } */
-void f_vint8mf8x5_t () {vint8mf8x5_t t;} /* { dg-error {unknown type name 'vint8mf8x5_t'} } */
-void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} /* { dg-error {unknown type name 'vuint8mf8x5_t'} } */
-void f_vint8mf8x6_t () {vint8mf8x6_t t;} /* { dg-error {unknown type name 'vint8mf8x6_t'} } */
-void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} /* { dg-error {unknown type name 'vuint8mf8x6_t'} } */
-void f_vint8mf8x7_t () {vint8mf8x7_t t;} /* { dg-error {unknown type name 'vint8mf8x7_t'} } */
-void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} /* { dg-error {unknown type name 'vuint8mf8x7_t'} } */
-void f_vint8mf8x8_t () {vint8mf8x8_t t;} /* { dg-error {unknown type name 'vint8mf8x8_t'} } */
-void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} /* { dg-error {unknown type name 'vuint8mf8x8_t'} } */
+void f_vint8mf8x2_t () {vint8mf8x2_t t;}
+void f_vuint8mf8x2_t () {vuint8mf8x2_t t;}
+void f_vint8mf8x3_t () {vint8mf8x3_t t;}
+void f_vuint8mf8x3_t () {vuint8mf8x3_t t;}
+void f_vint8mf8x4_t () {vint8mf8x4_t t;}
+void f_vuint8mf8x4_t () {vuint8mf8x4_t t;}
+void f_vint8mf8x5_t () {vint8mf8x5_t t;}
+void f_vuint8mf8x5_t () {vuint8mf8x5_t t;}
+void f_vint8mf8x6_t () {vint8mf8x6_t t;}
+void f_vuint8mf8x6_t () {vuint8mf8x6_t t;}
+void f_vint8mf8x7_t () {vint8mf8x7_t t;}
+void f_vuint8mf8x7_t () {vuint8mf8x7_t t;}
+void f_vint8mf8x8_t () {vint8mf8x8_t t;}
+void f_vuint8mf8x8_t () {vuint8mf8x8_t t;}
 void f_vint8mf4x2_t () {vint8mf4x2_t t;}
 void f_vuint8mf4x2_t () {vuint8mf4x2_t t;}
 void f_vint8mf4x3_t () {vint8mf4x3_t t;}
@@ -67,20 +67,20 @@ void f_vint8m2x4_t () {vint8m2x4_t t;}
 void f_vuint8m2x4_t () {vuint8m2x4_t t;}
 void f_vint8m4x2_t () {vint8m4x2_t t;}
 void f_vuint8m4x2_t () {vuint8m4x2_t t;}
-void f_vint16mf4x2_t () {vint16mf4x2_t t;} /* { dg-error {unknown type name 'vint16mf4x2_t'} } */
-void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} /* { dg-error {unknown type name 'vuint16mf4x2_t'} } */
-void f_vint16mf4x3_t () {vint16mf4x3_t t;} /* { dg-error {unknown type name 'vint16mf4x3_t'} } */
-void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} /* { dg-error {unknown type name 'vuint16mf4x3_t'} } */
-void f_vint16mf4x4_t () {vint16mf4x4_t t;} /* { dg-error {unknown type name 'vint16mf4x4_t'} } */
-void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} /* { dg-error {unknown type name 'vuint16mf4x4_t'} } */
-void f_vint16mf4x5_t () {vint16mf4x5_t t;} /* { dg-error {unknown type name 'vint16mf4x5_t'} } */
-void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} /* { dg-error {unknown type name 'vuint16mf4x5_t'} } */
-void f_vint16mf4x6_t () {vint16mf4x6_t t;} /* { dg-error {unknown type name 'vint16mf4x6_t'} } */
-void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} /* { dg-error {unknown type name 'vuint16mf4x6_t'} } */
-void f_vint16mf4x7_t () {vint16mf4x7_t t;} /* { dg-error {unknown type name 'vint16mf4x7_t'} } */
-void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} /* { dg-error {unknown type name 'vuint16mf4x7_t'} } */
-void f_vint16mf4x8_t () {vint16mf4x8_t t;} /* { dg-error {unknown type name 'vint16mf4x8_t'} } */
-void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} /* { dg-error {unknown type name 'vuint16mf4x8_t'} } */
+void f_vint16mf4x2_t () {vint16mf4x2_t t;}
+void f_vuint16mf4x2_t () {vuint16mf4x2_t t;}
+void f_vint16mf4x3_t () {vint16mf4x3_t t;}
+void f_vuint16mf4x3_t () {vuint16mf4x3_t t;}
+void f_vint16mf4x4_t () {vint16mf4x4_t t;}
+void f_vuint16mf4x4_t () {vuint16mf4x4_t t;}
+void f_vint16mf4x5_t () {vint16mf4x5_t t;}
+void f_vuint16mf4x5_t () {vuint16mf4x5_t t;}
+void f_vint16mf4x6_t () {vint16mf4x6_t t;}
+void f_vuint16mf4x6_t () {vuint16mf4x6_t t;}
+void f_vint16mf4x7_t () {vint16mf4x7_t t;}
+void f_vuint16mf4x7_t () {vuint16mf4x7_t t;}
+void f_vint16mf4x8_t () {vint16mf4x8_t t;}
+void f_vuint16mf4x8_t () {vuint16mf4x8_t t;}
 void f_vint16mf2x2_t () {vint16mf2x2_t t;}
 void f_vuint16mf2x2_t () {vuint16mf2x2_t t;}
 void f_vint16mf2x3_t () {vint16mf2x3_t t;}
@@ -117,20 +117,20 @@ void f_vint16m2x4_t () {vint16m2x4_t t;}
 void f_vuint16m2x4_t () {vuint16m2x4_t t;}
 void f_vint16m4x2_t () {vint16m4x2_t t;}
 void f_vuint16m4x2_t () {vuint16m4x2_t t;}
-void f_vint32mf2x2_t () {vint32mf2x2_t t;} /* { dg-error {unknown type name 'vint32mf2x2_t'} } */
-void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} /* { dg-error {unknown type name 'vuint32mf2x2_t'} } */
-void f_vint32mf2x3_t () {vint32mf2x3_t t;} /* { dg-error {unknown type name 'vint32mf2x3_t'} } */
-void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} /* { dg-error {unknown type name 'vuint32mf2x3_t'} } */
-void f_vint32mf2x4_t () {vint32mf2x4_t t;} /* { dg-error {unknown type name 'vint32mf2x4_t'} } */
-void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} /* { dg-error {unknown type name 'vuint32mf2x4_t'} } */
-void f_vint32mf2x5_t () {vint32mf2x5_t t;} /* { dg-error {unknown type name 'vint32mf2x5_t'} } */
-void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} /* { dg-error {unknown type name 'vuint32mf2x5_t'} } */
-void f_vint32mf2x6_t () {vint32mf2x6_t t;} /* { dg-error {unknown type name 'vint32mf2x6_t'} } */
-void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} /* { dg-error {unknown type name 'vuint32mf2x6_t'} } */
-void f_vint32mf2x7_t () {vint32mf2x7_t t;} /* { dg-error {unknown type name 'vint32mf2x7_t'} } */
-void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} /* { dg-error {unknown type name 'vuint32mf2x7_t'} } */
-void f_vint32mf2x8_t () {vint32mf2x8_t t;} /* { dg-error {unknown type name 'vint32mf2x8_t'} } */
-void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} /* { dg-error {unknown type name 'vuint32mf2x8_t'} } */
+void f_vint32mf2x2_t () {vint32mf2x2_t t;}
+void f_vuint32mf2x2_t () {vuint32mf2x2_t t;}
+void f_vint32mf2x3_t () {vint32mf2x3_t t;}
+void f_vuint32mf2x3_t () {vuint32mf2x3_t t;}
+void f_vint32mf2x4_t () {vint32mf2x4_t t;}
+void f_vuint32mf2x4_t () {vuint32mf2x4_t t;}
+void f_vint32mf2x5_t () {vint32mf2x5_t t;}
+void f_vuint32mf2x5_t () {vuint32mf2x5_t t;}
+void f_vint32mf2x6_t () {vint32mf2x6_t t;}
+void f_vuint32mf2x6_t () {vuint32mf2x6_t t;}
+void f_vint32mf2x7_t () {vint32mf2x7_t t;}
+void f_vuint32mf2x7_t () {vuint32mf2x7_t t;}
+void f_vint32mf2x8_t () {vint32mf2x8_t t;}
+void f_vuint32mf2x8_t () {vuint32mf2x8_t t;}
 void f_vint32m1x2_t () {vint32m1x2_t t;}
 void f_vuint32m1x2_t () {vuint32m1x2_t t;}
 void f_vint32m1x3_t () {vint32m1x3_t t;}
@@ -153,54 +153,143 @@ void f_vint32m2x4_t () {vint32m2x4_t t;}
 void f_vuint32m2x4_t () {vuint32m2x4_t t;}
 void f_vint32m4x2_t () {vint32m4x2_t t;}
 void f_vuint32m4x2_t () {vuint32m4x2_t t;}
-void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */
-void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */
-void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */
-void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */
-void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */
-void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */
-void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */
-void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */
-void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */
-void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */
-void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */
-void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */
-void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */
-void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */
-void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */
-void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */
-void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */
-void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */
-void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */
-void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
-void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
-void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
-void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
-void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
-void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
-void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */
-void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */
-void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */
-void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */
-void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */
-void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */
-void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */
-void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */
-void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */
-void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */
-void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */
-void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */
-void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */
-void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */
-void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void f_vint64m1x2_t () {vint64m1x2_t t;}
+void f_vuint64m1x2_t () {vuint64m1x2_t t;}
+void f_vint64m1x3_t () {vint64m1x3_t t;}
+void f_vuint64m1x3_t () {vuint64m1x3_t t;}
+void f_vint64m1x4_t () {vint64m1x4_t t;}
+void f_vuint64m1x4_t () {vuint64m1x4_t t;}
+void f_vint64m1x5_t () {vint64m1x5_t t;}
+void f_vuint64m1x5_t () {vuint64m1x5_t t;}
+void f_vint64m1x6_t () {vint64m1x6_t t;}
+void f_vuint64m1x6_t () {vuint64m1x6_t t;}
+void f_vint64m1x7_t () {vint64m1x7_t t;}
+void f_vuint64m1x7_t () {vuint64m1x7_t t;}
+void f_vint64m1x8_t () {vint64m1x8_t t;}
+void f_vuint64m1x8_t () {vuint64m1x8_t t;}
+void f_vint64m2x2_t () {vint64m2x2_t t;}
+void f_vuint64m2x2_t () {vuint64m2x2_t t;}
+void f_vint64m2x3_t () {vint64m2x3_t t;}
+void f_vuint64m2x3_t () {vuint64m2x3_t t;}
+void f_vint64m2x4_t () {vint64m2x4_t t;}
+void f_vuint64m2x4_t () {vuint64m2x4_t t;}
+void f_vint64m4x2_t () {vint64m4x2_t t;}
+void f_vuint64m4x2_t () {vuint64m4x2_t t;}
+void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;}
+void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;}
+void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;}
+void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;}
+void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;}
+void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;}
+void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;}
+void f_vfloat32m1x2_t () {vfloat32m1x2_t t;}
+void f_vfloat32m1x3_t () {vfloat32m1x3_t t;}
+void f_vfloat32m1x4_t () {vfloat32m1x4_t t;}
+void f_vfloat32m1x5_t () {vfloat32m1x5_t t;}
+void f_vfloat32m1x6_t () {vfloat32m1x6_t t;}
+void f_vfloat32m1x7_t () {vfloat32m1x7_t t;}
+void f_vfloat32m1x8_t () {vfloat32m1x8_t t;}
+void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
+void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
+void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
+void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void new_f_vint8mf8x2_t (vint8mf8x2_t t) { }     /* { dg-error {argument type 'vint8mf8x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x2_t (vuint8mf8x2_t t) { }   /* { dg-error {argument type 'vuint8mf8x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x3_t (vint8mf8x3_t t) { }     /* { dg-error {argument type 'vint8mf8x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x3_t (vuint8mf8x3_t t) { }   /* { dg-error {argument type 'vuint8mf8x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x4_t (vint8mf8x4_t t) { }     /* { dg-error {argument type 'vint8mf8x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x4_t (vuint8mf8x4_t t) { }   /* { dg-error {argument type 'vuint8mf8x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x5_t (vint8mf8x5_t t) { }     /* { dg-error {argument type 'vint8mf8x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x5_t (vuint8mf8x5_t t) { }   /* { dg-error {argument type 'vuint8mf8x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x6_t (vint8mf8x6_t t) { }     /* { dg-error {argument type 'vint8mf8x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x6_t (vuint8mf8x6_t t) { }   /* { dg-error {argument type 'vuint8mf8x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x7_t (vint8mf8x7_t t) { }     /* { dg-error {argument type 'vint8mf8x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x7_t (vuint8mf8x7_t t) { }   /* { dg-error {argument type 'vuint8mf8x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x8_t (vint8mf8x8_t t) { }     /* { dg-error {argument type 'vint8mf8x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x8_t (vuint8mf8x8_t t) { }   /* { dg-error {argument type 'vuint8mf8x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x2_t (vint32mf2x2_t t) { }   /* { dg-error {argument type 'vint32mf2x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x2_t (vuint32mf2x2_t t) { } /* { dg-error {argument type 'vuint32mf2x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x3_t (vint32mf2x3_t t) { }   /* { dg-error {argument type 'vint32mf2x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x3_t (vuint32mf2x3_t t) { } /* { dg-error {argument type 'vuint32mf2x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x4_t (vint32mf2x4_t t) { }   /* { dg-error {argument type 'vint32mf2x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x4_t (vuint32mf2x4_t t) { } /* { dg-error {argument type 'vuint32mf2x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x5_t (vint32mf2x5_t t) { }   /* { dg-error {argument type 'vint32mf2x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x5_t (vuint32mf2x5_t t) { } /* { dg-error {argument type 'vuint32mf2x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x6_t (vint32mf2x6_t t) { }   /* { dg-error {argument type 'vint32mf2x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x6_t (vuint32mf2x6_t t) { } /* { dg-error {argument type 'vuint32mf2x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x7_t (vint32mf2x7_t t) { }   /* { dg-error {argument type 'vint32mf2x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x7_t (vuint32mf2x7_t t) { } /* { dg-error {argument type 'vuint32mf2x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x8_t (vint32mf2x8_t t) { }   /* { dg-error {argument type 'vint32mf2x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x8_t (vuint32mf2x8_t t) { } /* { dg-error {argument type 'vuint32mf2x8_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_f_vint64m1x2_t (vint64m1x2_t t) { }   /* { dg-error {argument type 'vint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x2_t (vuint64m1x2_t t) { } /* { dg-error {argument type 'vuint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x3_t (vint64m1x3_t t) { }   /* { dg-error {argument type 'vint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x3_t (vuint64m1x3_t t) { } /* { dg-error {argument type 'vuint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x4_t (vint64m1x4_t t) { }   /* { dg-error {argument type 'vint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x4_t (vuint64m1x4_t t) { } /* { dg-error {argument type 'vuint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x5_t (vint64m1x5_t t) { }   /* { dg-error {argument type 'vint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x5_t (vuint64m1x5_t t) { } /* { dg-error {argument type 'vuint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x6_t (vint64m1x6_t t) { }   /* { dg-error {argument type 'vint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x6_t (vuint64m1x6_t t) { } /* { dg-error {argument type 'vuint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x7_t (vint64m1x7_t t) { }   /* { dg-error {argument type 'vint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x7_t (vuint64m1x7_t t) { } /* { dg-error {argument type 'vuint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x8_t (vint64m1x8_t t) { }   /* { dg-error {argument type 'vint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x8_t (vuint64m1x8_t t) { } /* { dg-error {argument type 'vuint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x2_t (vint64m2x2_t t) { }   /* { dg-error {argument type 'vint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x2_t (vuint64m2x2_t t) { } /* { dg-error {argument type 'vuint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x3_t (vint64m2x3_t t) { }   /* { dg-error {argument type 'vint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x3_t (vuint64m2x3_t t) { } /* { dg-error {argument type 'vuint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x4_t (vint64m2x4_t t) { }   /* { dg-error {argument type 'vint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x4_t (vuint64m2x4_t t) { } /* { dg-error {argument type 'vuint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m4x2_t (vint64m4x2_t t) { }   /* { dg-error {argument type 'vint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m4x2_t (vuint64m4x2_t t) { } /* { dg-error {argument type 'vuint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat32mf2x2_t (vfloat32mf2x2_t t) { } /* { dg-error {argument type 'vfloat32mf2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x3_t (vfloat32mf2x3_t t) { } /* { dg-error {argument type 'vfloat32mf2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x4_t (vfloat32mf2x4_t t) { } /* { dg-error {argument type 'vfloat32mf2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x5_t (vfloat32mf2x5_t t) { } /* { dg-error {argument type 'vfloat32mf2x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x6_t (vfloat32mf2x6_t t) { } /* { dg-error {argument type 'vfloat32mf2x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x7_t (vfloat32mf2x7_t t) { } /* { dg-error {argument type 'vfloat32mf2x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x8_t (vfloat32mf2x8_t t) { } /* { dg-error {argument type 'vfloat32mf2x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat32m1x2_t (vfloat32m1x2_t t) { } /* { dg-error {argument type 'vfloat32m1x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x3_t (vfloat32m1x3_t t) { } /* { dg-error {argument type 'vfloat32m1x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x4_t (vfloat32m1x4_t t) { } /* { dg-error {argument type 'vfloat32m1x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x5_t (vfloat32m1x5_t t) { } /* { dg-error {argument type 'vfloat32m1x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x6_t (vfloat32m1x6_t t) { } /* { dg-error {argument type 'vfloat32m1x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x7_t (vfloat32m1x7_t t) { } /* { dg-error {argument type 'vfloat32m1x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x8_t (vfloat32m1x8_t t) { } /* { dg-error {argument type 'vfloat32m1x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x2_t (vfloat32m2x2_t t) { } /* { dg-error {argument type 'vfloat32m2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x3_t (vfloat32m2x3_t t) { } /* { dg-error {argument type 'vfloat32m2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x4_t (vfloat32m2x4_t t) { } /* { dg-error {argument type 'vfloat32m2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m4x2_t (vfloat32m4x2_t t) { } /* { dg-error {argument type 'vfloat32m4x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c
index ed180749cb614664ee2eecc064aaaa8c05449197..967eeece274470678c4098910e4583ce68afd1b4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c
@@ -153,54 +153,108 @@ void f_vint32m2x4_t () {vint32m2x4_t t;}
 void f_vuint32m2x4_t () {vuint32m2x4_t t;}
 void f_vint32m4x2_t () {vint32m4x2_t t;}
 void f_vuint32m4x2_t () {vuint32m4x2_t t;}
-void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */
-void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */
-void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */
-void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */
-void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */
-void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */
-void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */
-void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */
-void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */
-void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */
-void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */
-void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */
-void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */
-void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */
-void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */
-void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */
-void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */
-void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */
-void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */
-void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
-void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
-void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
-void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
-void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
-void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
-void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */
-void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */
-void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */
-void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */
-void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */
-void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */
-void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */
-void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */
-void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */
-void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */
-void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */
-void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */
-void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */
-void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */
-void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+void f_vint64m1x2_t () {vint64m1x2_t t;}
+void f_vuint64m1x2_t () {vuint64m1x2_t t;}
+void f_vint64m1x3_t () {vint64m1x3_t t;}
+void f_vuint64m1x3_t () {vuint64m1x3_t t;}
+void f_vint64m1x4_t () {vint64m1x4_t t;}
+void f_vuint64m1x4_t () {vuint64m1x4_t t;}
+void f_vint64m1x5_t () {vint64m1x5_t t;}
+void f_vuint64m1x5_t () {vuint64m1x5_t t;}
+void f_vint64m1x6_t () {vint64m1x6_t t;}
+void f_vuint64m1x6_t () {vuint64m1x6_t t;}
+void f_vint64m1x7_t () {vint64m1x7_t t;}
+void f_vuint64m1x7_t () {vuint64m1x7_t t;}
+void f_vint64m1x8_t () {vint64m1x8_t t;}
+void f_vuint64m1x8_t () {vuint64m1x8_t t;}
+void f_vint64m2x2_t () {vint64m2x2_t t;}
+void f_vuint64m2x2_t () {vuint64m2x2_t t;}
+void f_vint64m2x3_t () {vint64m2x3_t t;}
+void f_vuint64m2x3_t () {vuint64m2x3_t t;}
+void f_vint64m2x4_t () {vint64m2x4_t t;}
+void f_vuint64m2x4_t () {vuint64m2x4_t t;}
+void f_vint64m4x2_t () {vint64m4x2_t t;}
+void f_vuint64m4x2_t () {vuint64m4x2_t t;}
+void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;}
+void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;}
+void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;}
+void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;}
+void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;}
+void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;}
+void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;}
+void f_vfloat32m1x2_t () {vfloat32m1x2_t t;}
+void f_vfloat32m1x3_t () {vfloat32m1x3_t t;}
+void f_vfloat32m1x4_t () {vfloat32m1x4_t t;}
+void f_vfloat32m1x5_t () {vfloat32m1x5_t t;}
+void f_vfloat32m1x6_t () {vfloat32m1x6_t t;}
+void f_vfloat32m1x7_t () {vfloat32m1x7_t t;}
+void f_vfloat32m1x8_t () {vfloat32m1x8_t t;}
+void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
+void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
+void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
+void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void new_f_vint64m1x2_t (vint64m1x2_t t) { }   /* { dg-error {argument type 'vint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x2_t (vuint64m1x2_t t) { } /* { dg-error {argument type 'vuint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x3_t (vint64m1x3_t t) { }   /* { dg-error {argument type 'vint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x3_t (vuint64m1x3_t t) { } /* { dg-error {argument type 'vuint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x4_t (vint64m1x4_t t) { }   /* { dg-error {argument type 'vint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x4_t (vuint64m1x4_t t) { } /* { dg-error {argument type 'vuint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x5_t (vint64m1x5_t t) { }   /* { dg-error {argument type 'vint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x5_t (vuint64m1x5_t t) { } /* { dg-error {argument type 'vuint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x6_t (vint64m1x6_t t) { }   /* { dg-error {argument type 'vint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x6_t (vuint64m1x6_t t) { } /* { dg-error {argument type 'vuint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x7_t (vint64m1x7_t t) { }   /* { dg-error {argument type 'vint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x7_t (vuint64m1x7_t t) { } /* { dg-error {argument type 'vuint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x8_t (vint64m1x8_t t) { }   /* { dg-error {argument type 'vint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x8_t (vuint64m1x8_t t) { } /* { dg-error {argument type 'vuint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x2_t (vint64m2x2_t t) { }   /* { dg-error {argument type 'vint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x2_t (vuint64m2x2_t t) { } /* { dg-error {argument type 'vuint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x3_t (vint64m2x3_t t) { }   /* { dg-error {argument type 'vint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x3_t (vuint64m2x3_t t) { } /* { dg-error {argument type 'vuint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x4_t (vint64m2x4_t t) { }   /* { dg-error {argument type 'vint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x4_t (vuint64m2x4_t t) { } /* { dg-error {argument type 'vuint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m4x2_t (vint64m4x2_t t) { }   /* { dg-error {argument type 'vint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m4x2_t (vuint64m4x2_t t) { } /* { dg-error {argument type 'vuint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat32mf2x2_t (vfloat32mf2x2_t t) { } /* { dg-error {argument type 'vfloat32mf2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x3_t (vfloat32mf2x3_t t) { } /* { dg-error {argument type 'vfloat32mf2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x4_t (vfloat32mf2x4_t t) { } /* { dg-error {argument type 'vfloat32mf2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x5_t (vfloat32mf2x5_t t) { } /* { dg-error {argument type 'vfloat32mf2x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x6_t (vfloat32mf2x6_t t) { } /* { dg-error {argument type 'vfloat32mf2x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x7_t (vfloat32mf2x7_t t) { } /* { dg-error {argument type 'vfloat32mf2x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32mf2x8_t (vfloat32mf2x8_t t) { } /* { dg-error {argument type 'vfloat32mf2x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat32m1x2_t (vfloat32m1x2_t t) { } /* { dg-error {argument type 'vfloat32m1x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x3_t (vfloat32m1x3_t t) { } /* { dg-error {argument type 'vfloat32m1x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x4_t (vfloat32m1x4_t t) { } /* { dg-error {argument type 'vfloat32m1x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x5_t (vfloat32m1x5_t t) { } /* { dg-error {argument type 'vfloat32m1x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x6_t (vfloat32m1x6_t t) { } /* { dg-error {argument type 'vfloat32m1x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x7_t (vfloat32m1x7_t t) { } /* { dg-error {argument type 'vfloat32m1x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m1x8_t (vfloat32m1x8_t t) { } /* { dg-error {argument type 'vfloat32m1x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x2_t (vfloat32m2x2_t t) { } /* { dg-error {argument type 'vfloat32m2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x3_t (vfloat32m2x3_t t) { } /* { dg-error {argument type 'vfloat32m2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m2x4_t (vfloat32m2x4_t t) { } /* { dg-error {argument type 'vfloat32m2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat32m4x2_t (vfloat32m4x2_t t) { } /* { dg-error {argument type 'vfloat32m4x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_f_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c
index 70e0989b6e14f02f6acd940f9cce9e0e7192af13..b868f3141635d79212a97ce614095a3d770b3bfb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c
@@ -3,20 +3,20 @@
 
 #include "riscv_vector.h"
 
-void f_vint8mf8x2_t () {vint8mf8x2_t t;} /* { dg-error {unknown type name 'vint8mf8x2_t'} } */
-void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} /* { dg-error {unknown type name 'vuint8mf8x2_t'} } */
-void f_vint8mf8x3_t () {vint8mf8x3_t t;} /* { dg-error {unknown type name 'vint8mf8x3_t'} } */
-void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} /* { dg-error {unknown type name 'vuint8mf8x3_t'} } */
-void f_vint8mf8x4_t () {vint8mf8x4_t t;} /* { dg-error {unknown type name 'vint8mf8x4_t'} } */
-void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} /* { dg-error {unknown type name 'vuint8mf8x4_t'} } */
-void f_vint8mf8x5_t () {vint8mf8x5_t t;} /* { dg-error {unknown type name 'vint8mf8x5_t'} } */
-void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} /* { dg-error {unknown type name 'vuint8mf8x5_t'} } */
-void f_vint8mf8x6_t () {vint8mf8x6_t t;} /* { dg-error {unknown type name 'vint8mf8x6_t'} } */
-void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} /* { dg-error {unknown type name 'vuint8mf8x6_t'} } */
-void f_vint8mf8x7_t () {vint8mf8x7_t t;} /* { dg-error {unknown type name 'vint8mf8x7_t'} } */
-void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} /* { dg-error {unknown type name 'vuint8mf8x7_t'} } */
-void f_vint8mf8x8_t () {vint8mf8x8_t t;} /* { dg-error {unknown type name 'vint8mf8x8_t'} } */
-void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} /* { dg-error {unknown type name 'vuint8mf8x8_t'} } */
+void f_vint8mf8x2_t () {vint8mf8x2_t t;}
+void f_vuint8mf8x2_t () {vuint8mf8x2_t t;}
+void f_vint8mf8x3_t () {vint8mf8x3_t t;}
+void f_vuint8mf8x3_t () {vuint8mf8x3_t t;}
+void f_vint8mf8x4_t () {vint8mf8x4_t t;}
+void f_vuint8mf8x4_t () {vuint8mf8x4_t t;}
+void f_vint8mf8x5_t () {vint8mf8x5_t t;}
+void f_vuint8mf8x5_t () {vuint8mf8x5_t t;}
+void f_vint8mf8x6_t () {vint8mf8x6_t t;}
+void f_vuint8mf8x6_t () {vuint8mf8x6_t t;}
+void f_vint8mf8x7_t () {vint8mf8x7_t t;}
+void f_vuint8mf8x7_t () {vuint8mf8x7_t t;}
+void f_vint8mf8x8_t () {vint8mf8x8_t t;}
+void f_vuint8mf8x8_t () {vuint8mf8x8_t t;}
 void f_vint8mf4x2_t () {vint8mf4x2_t t;}
 void f_vuint8mf4x2_t () {vuint8mf4x2_t t;}
 void f_vint8mf4x3_t () {vint8mf4x3_t t;}
@@ -67,20 +67,20 @@ void f_vint8m2x4_t () {vint8m2x4_t t;}
 void f_vuint8m2x4_t () {vuint8m2x4_t t;}
 void f_vint8m4x2_t () {vint8m4x2_t t;}
 void f_vuint8m4x2_t () {vuint8m4x2_t t;}
-void f_vint16mf4x2_t () {vint16mf4x2_t t;} /* { dg-error {unknown type name 'vint16mf4x2_t'} } */
-void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} /* { dg-error {unknown type name 'vuint16mf4x2_t'} } */
-void f_vint16mf4x3_t () {vint16mf4x3_t t;} /* { dg-error {unknown type name 'vint16mf4x3_t'} } */
-void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} /* { dg-error {unknown type name 'vuint16mf4x3_t'} } */
-void f_vint16mf4x4_t () {vint16mf4x4_t t;} /* { dg-error {unknown type name 'vint16mf4x4_t'} } */
-void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} /* { dg-error {unknown type name 'vuint16mf4x4_t'} } */
-void f_vint16mf4x5_t () {vint16mf4x5_t t;} /* { dg-error {unknown type name 'vint16mf4x5_t'} } */
-void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} /* { dg-error {unknown type name 'vuint16mf4x5_t'} } */
-void f_vint16mf4x6_t () {vint16mf4x6_t t;} /* { dg-error {unknown type name 'vint16mf4x6_t'} } */
-void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} /* { dg-error {unknown type name 'vuint16mf4x6_t'} } */
-void f_vint16mf4x7_t () {vint16mf4x7_t t;} /* { dg-error {unknown type name 'vint16mf4x7_t'} } */
-void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} /* { dg-error {unknown type name 'vuint16mf4x7_t'} } */
-void f_vint16mf4x8_t () {vint16mf4x8_t t;} /* { dg-error {unknown type name 'vint16mf4x8_t'} } */
-void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} /* { dg-error {unknown type name 'vuint16mf4x8_t'} } */
+void f_vint16mf4x2_t () {vint16mf4x2_t t;}
+void f_vuint16mf4x2_t () {vuint16mf4x2_t t;}
+void f_vint16mf4x3_t () {vint16mf4x3_t t;}
+void f_vuint16mf4x3_t () {vuint16mf4x3_t t;}
+void f_vint16mf4x4_t () {vint16mf4x4_t t;}
+void f_vuint16mf4x4_t () {vuint16mf4x4_t t;}
+void f_vint16mf4x5_t () {vint16mf4x5_t t;}
+void f_vuint16mf4x5_t () {vuint16mf4x5_t t;}
+void f_vint16mf4x6_t () {vint16mf4x6_t t;}
+void f_vuint16mf4x6_t () {vuint16mf4x6_t t;}
+void f_vint16mf4x7_t () {vint16mf4x7_t t;}
+void f_vuint16mf4x7_t () {vuint16mf4x7_t t;}
+void f_vint16mf4x8_t () {vint16mf4x8_t t;}
+void f_vuint16mf4x8_t () {vuint16mf4x8_t t;}
 void f_vint16mf2x2_t () {vint16mf2x2_t t;}
 void f_vuint16mf2x2_t () {vuint16mf2x2_t t;}
 void f_vint16mf2x3_t () {vint16mf2x3_t t;}
@@ -117,20 +117,20 @@ void f_vint16m2x4_t () {vint16m2x4_t t;}
 void f_vuint16m2x4_t () {vuint16m2x4_t t;}
 void f_vint16m4x2_t () {vint16m4x2_t t;}
 void f_vuint16m4x2_t () {vuint16m4x2_t t;}
-void f_vint32mf2x2_t () {vint32mf2x2_t t;} /* { dg-error {unknown type name 'vint32mf2x2_t'} } */
-void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} /* { dg-error {unknown type name 'vuint32mf2x2_t'} } */
-void f_vint32mf2x3_t () {vint32mf2x3_t t;} /* { dg-error {unknown type name 'vint32mf2x3_t'} } */
-void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} /* { dg-error {unknown type name 'vuint32mf2x3_t'} } */
-void f_vint32mf2x4_t () {vint32mf2x4_t t;} /* { dg-error {unknown type name 'vint32mf2x4_t'} } */
-void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} /* { dg-error {unknown type name 'vuint32mf2x4_t'} } */
-void f_vint32mf2x5_t () {vint32mf2x5_t t;} /* { dg-error {unknown type name 'vint32mf2x5_t'} } */
-void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} /* { dg-error {unknown type name 'vuint32mf2x5_t'} } */
-void f_vint32mf2x6_t () {vint32mf2x6_t t;} /* { dg-error {unknown type name 'vint32mf2x6_t'} } */
-void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} /* { dg-error {unknown type name 'vuint32mf2x6_t'} } */
-void f_vint32mf2x7_t () {vint32mf2x7_t t;} /* { dg-error {unknown type name 'vint32mf2x7_t'} } */
-void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} /* { dg-error {unknown type name 'vuint32mf2x7_t'} } */
-void f_vint32mf2x8_t () {vint32mf2x8_t t;} /* { dg-error {unknown type name 'vint32mf2x8_t'} } */
-void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} /* { dg-error {unknown type name 'vuint32mf2x8_t'} } */
+void f_vint32mf2x2_t () {vint32mf2x2_t t;}
+void f_vuint32mf2x2_t () {vuint32mf2x2_t t;}
+void f_vint32mf2x3_t () {vint32mf2x3_t t;}
+void f_vuint32mf2x3_t () {vuint32mf2x3_t t;}
+void f_vint32mf2x4_t () {vint32mf2x4_t t;}
+void f_vuint32mf2x4_t () {vuint32mf2x4_t t;}
+void f_vint32mf2x5_t () {vint32mf2x5_t t;}
+void f_vuint32mf2x5_t () {vuint32mf2x5_t t;}
+void f_vint32mf2x6_t () {vint32mf2x6_t t;}
+void f_vuint32mf2x6_t () {vuint32mf2x6_t t;}
+void f_vint32mf2x7_t () {vint32mf2x7_t t;}
+void f_vuint32mf2x7_t () {vuint32mf2x7_t t;}
+void f_vint32mf2x8_t () {vint32mf2x8_t t;}
+void f_vuint32mf2x8_t () {vuint32mf2x8_t t;}
 void f_vint32m1x2_t () {vint32m1x2_t t;}
 void f_vuint32m1x2_t () {vuint32m1x2_t t;}
 void f_vint32m1x3_t () {vint32m1x3_t t;}
@@ -153,35 +153,35 @@ void f_vint32m2x4_t () {vint32m2x4_t t;}
 void f_vuint32m2x4_t () {vuint32m2x4_t t;}
 void f_vint32m4x2_t () {vint32m4x2_t t;}
 void f_vuint32m4x2_t () {vuint32m4x2_t t;}
-void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */
-void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */
-void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */
-void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */
-void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */
-void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */
-void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */
-void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */
-void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */
-void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */
-void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */
-void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */
-void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */
-void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */
-void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */
-void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */
-void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */
-void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */
-void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */
-void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
-void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
-void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
-void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
-void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
-void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
-void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */
-void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */
-void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */
-void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */
+void f_vint64m1x2_t () {vint64m1x2_t t;}
+void f_vuint64m1x2_t () {vuint64m1x2_t t;}
+void f_vint64m1x3_t () {vint64m1x3_t t;}
+void f_vuint64m1x3_t () {vuint64m1x3_t t;}
+void f_vint64m1x4_t () {vint64m1x4_t t;}
+void f_vuint64m1x4_t () {vuint64m1x4_t t;}
+void f_vint64m1x5_t () {vint64m1x5_t t;}
+void f_vuint64m1x5_t () {vuint64m1x5_t t;}
+void f_vint64m1x6_t () {vint64m1x6_t t;}
+void f_vuint64m1x6_t () {vuint64m1x6_t t;}
+void f_vint64m1x7_t () {vint64m1x7_t t;}
+void f_vuint64m1x7_t () {vuint64m1x7_t t;}
+void f_vint64m1x8_t () {vint64m1x8_t t;}
+void f_vuint64m1x8_t () {vuint64m1x8_t t;}
+void f_vint64m2x2_t () {vint64m2x2_t t;}
+void f_vuint64m2x2_t () {vuint64m2x2_t t;}
+void f_vint64m2x3_t () {vint64m2x3_t t;}
+void f_vuint64m2x3_t () {vuint64m2x3_t t;}
+void f_vint64m2x4_t () {vint64m2x4_t t;}
+void f_vuint64m2x4_t () {vuint64m2x4_t t;}
+void f_vint64m4x2_t () {vint64m4x2_t t;}
+void f_vuint64m4x2_t () {vuint64m4x2_t t;}
+void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;}
+void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;}
+void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;}
+void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;}
+void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;}
+void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;}
+void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;}
 void f_vfloat32m1x2_t () {vfloat32m1x2_t t;}
 void f_vfloat32m1x3_t () {vfloat32m1x3_t t;}
 void f_vfloat32m1x4_t () {vfloat32m1x4_t t;}
@@ -193,14 +193,107 @@ void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
 void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
 void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
 void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void new_f_vint8mf8x2_t (vint8mf8x2_t t) { }   /* { dg-error {argument type 'vint8mf8x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x2_t (vuint8mf8x2_t t) { } /* { dg-error {argument type 'vuint8mf8x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x3_t (vint8mf8x3_t t) { }   /* { dg-error {argument type 'vint8mf8x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x3_t (vuint8mf8x3_t t) { } /* { dg-error {argument type 'vuint8mf8x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x4_t (vint8mf8x4_t t) { }   /* { dg-error {argument type 'vint8mf8x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x4_t (vuint8mf8x4_t t) { } /* { dg-error {argument type 'vuint8mf8x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x5_t (vint8mf8x5_t t) { }   /* { dg-error {argument type 'vint8mf8x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x5_t (vuint8mf8x5_t t) { } /* { dg-error {argument type 'vuint8mf8x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x6_t (vint8mf8x6_t t) { }   /* { dg-error {argument type 'vint8mf8x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x6_t (vuint8mf8x6_t t) { } /* { dg-error {argument type 'vuint8mf8x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x7_t (vint8mf8x7_t t) { }   /* { dg-error {argument type 'vint8mf8x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x7_t (vuint8mf8x7_t t) { } /* { dg-error {argument type 'vuint8mf8x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint8mf8x8_t (vint8mf8x8_t t) { }   /* { dg-error {argument type 'vint8mf8x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint8mf8x8_t (vuint8mf8x8_t t) { } /* { dg-error {argument type 'vuint8mf8x8_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_f_vint16mf4x2_t (vint16mf4x2_t t) { }   /* { dg-error {argument type 'vint16mf4x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x2_t (vuint16mf4x2_t t) { } /* { dg-error {argument type 'vuint16mf4x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x3_t (vint16mf4x3_t t) { }   /* { dg-error {argument type 'vint16mf4x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x3_t (vuint16mf4x3_t t) { } /* { dg-error {argument type 'vuint16mf4x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x4_t (vint16mf4x4_t t) { }   /* { dg-error {argument type 'vint16mf4x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x4_t (vuint16mf4x4_t t) { } /* { dg-error {argument type 'vuint16mf4x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x5_t (vint16mf4x5_t t) { }   /* { dg-error {argument type 'vint16mf4x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x5_t (vuint16mf4x5_t t) { } /* { dg-error {argument type 'vuint16mf4x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x6_t (vint16mf4x6_t t) { }   /* { dg-error {argument type 'vint16mf4x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x6_t (vuint16mf4x6_t t) { } /* { dg-error {argument type 'vuint16mf4x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x7_t (vint16mf4x7_t t) { }   /* { dg-error {argument type 'vint16mf4x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x7_t (vuint16mf4x7_t t) { } /* { dg-error {argument type 'vuint16mf4x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint16mf4x8_t (vint16mf4x8_t t) { }   /* { dg-error {argument type 'vint16mf4x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint16mf4x8_t (vuint16mf4x8_t t) { } /* { dg-error {argument type 'vuint16mf4x8_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_f_vint32mf2x2_t (vint32mf2x2_t t) { }   /* { dg-error {argument type 'vint32mf2x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x2_t (vuint32mf2x2_t t) { } /* { dg-error {argument type 'vuint32mf2x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x3_t (vint32mf2x3_t t) { }   /* { dg-error {argument type 'vint32mf2x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x3_t (vuint32mf2x3_t t) { } /* { dg-error {argument type 'vuint32mf2x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x4_t (vint32mf2x4_t t) { }   /* { dg-error {argument type 'vint32mf2x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x4_t (vuint32mf2x4_t t) { } /* { dg-error {argument type 'vuint32mf2x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x5_t (vint32mf2x5_t t) { }   /* { dg-error {argument type 'vint32mf2x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x5_t (vuint32mf2x5_t t) { } /* { dg-error {argument type 'vuint32mf2x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x6_t (vint32mf2x6_t t) { }   /* { dg-error {argument type 'vint32mf2x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x6_t (vuint32mf2x6_t t) { } /* { dg-error {argument type 'vuint32mf2x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x7_t (vint32mf2x7_t t) { }   /* { dg-error {argument type 'vint32mf2x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x7_t (vuint32mf2x7_t t) { } /* { dg-error {argument type 'vuint32mf2x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vint32mf2x8_t (vint32mf2x8_t t) { }   /* { dg-error {argument type 'vint32mf2x8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vuint32mf2x8_t (vuint32mf2x8_t t) { } /* { dg-error {argument type 'vuint32mf2x8_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_f_vint64m1x2_t (vint64m1x2_t t) { }   /* { dg-error {argument type 'vint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x2_t (vuint64m1x2_t t) { } /* { dg-error {argument type 'vuint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x3_t (vint64m1x3_t t) { }   /* { dg-error {argument type 'vint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x3_t (vuint64m1x3_t t) { } /* { dg-error {argument type 'vuint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x4_t (vint64m1x4_t t) { }   /* { dg-error {argument type 'vint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x4_t (vuint64m1x4_t t) { } /* { dg-error {argument type 'vuint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x5_t (vint64m1x5_t t) { }   /* { dg-error {argument type 'vint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x5_t (vuint64m1x5_t t) { } /* { dg-error {argument type 'vuint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x6_t (vint64m1x6_t t) { }   /* { dg-error {argument type 'vint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x6_t (vuint64m1x6_t t) { } /* { dg-error {argument type 'vuint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x7_t (vint64m1x7_t t) { }   /* { dg-error {argument type 'vint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x7_t (vuint64m1x7_t t) { } /* { dg-error {argument type 'vuint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x8_t (vint64m1x8_t t) { }   /* { dg-error {argument type 'vint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x8_t (vuint64m1x8_t t) { } /* { dg-error {argument type 'vuint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x2_t (vint64m2x2_t t) { }   /* { dg-error {argument type 'vint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x2_t (vuint64m2x2_t t) { } /* { dg-error {argument type 'vuint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x3_t (vint64m2x3_t t) { }   /* { dg-error {argument type 'vint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x3_t (vuint64m2x3_t t) { } /* { dg-error {argument type 'vuint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x4_t (vint64m2x4_t t) { }   /* { dg-error {argument type 'vint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x4_t (vuint64m2x4_t t) { } /* { dg-error {argument type 'vuint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m4x2_t (vint64m4x2_t t) { }   /* { dg-error {argument type 'vint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m4x2_t (vuint64m4x2_t t) { } /* { dg-error {argument type 'vuint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat32mf2x2_t (vfloat32mf2x2_t t) { } /* { dg-error {argument type 'vfloat32mf2x2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x3_t (vfloat32mf2x3_t t) { } /* { dg-error {argument type 'vfloat32mf2x3_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x4_t (vfloat32mf2x4_t t) { } /* { dg-error {argument type 'vfloat32mf2x4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x5_t (vfloat32mf2x5_t t) { } /* { dg-error {argument type 'vfloat32mf2x5_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x6_t (vfloat32mf2x6_t t) { } /* { dg-error {argument type 'vfloat32mf2x6_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x7_t (vfloat32mf2x7_t t) { } /* { dg-error {argument type 'vfloat32mf2x7_t' requires the minimal vector length '64' but '32' is given} } */
+void new_f_vfloat32mf2x8_t (vfloat32mf2x8_t t) { } /* { dg-error {argument type 'vfloat32mf2x8_t' requires the minimal vector length '64' but '32' is given} } */
+
+void new_f_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c
index 2a615f808162abcfd4d9e35df06ab6aed3fbd78c..094b7efdef447e888b3475392aebbbb01ba54db5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c
@@ -153,28 +153,28 @@ void f_vint32m2x4_t () {vint32m2x4_t t;}
 void f_vuint32m2x4_t () {vuint32m2x4_t t;}
 void f_vint32m4x2_t () {vint32m4x2_t t;}
 void f_vuint32m4x2_t () {vuint32m4x2_t t;}
-void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */
-void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */
-void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */
-void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */
-void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */
-void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */
-void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */
-void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */
-void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */
-void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */
-void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */
-void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */
-void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */
-void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */
-void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */
-void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */
-void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */
-void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */
-void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */
-void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */
-void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */
-void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */
+void f_vint64m1x2_t () {vint64m1x2_t t;}
+void f_vuint64m1x2_t () {vuint64m1x2_t t;}
+void f_vint64m1x3_t () {vint64m1x3_t t;}
+void f_vuint64m1x3_t () {vuint64m1x3_t t;}
+void f_vint64m1x4_t () {vint64m1x4_t t;}
+void f_vuint64m1x4_t () {vuint64m1x4_t t;}
+void f_vint64m1x5_t () {vint64m1x5_t t;}
+void f_vuint64m1x5_t () {vuint64m1x5_t t;}
+void f_vint64m1x6_t () {vint64m1x6_t t;}
+void f_vuint64m1x6_t () {vuint64m1x6_t t;}
+void f_vint64m1x7_t () {vint64m1x7_t t;}
+void f_vuint64m1x7_t () {vuint64m1x7_t t;}
+void f_vint64m1x8_t () {vint64m1x8_t t;}
+void f_vuint64m1x8_t () {vuint64m1x8_t t;}
+void f_vint64m2x2_t () {vint64m2x2_t t;}
+void f_vuint64m2x2_t () {vuint64m2x2_t t;}
+void f_vint64m2x3_t () {vint64m2x3_t t;}
+void f_vuint64m2x3_t () {vuint64m2x3_t t;}
+void f_vint64m2x4_t () {vint64m2x4_t t;}
+void f_vuint64m2x4_t () {vuint64m2x4_t t;}
+void f_vint64m4x2_t () {vint64m4x2_t t;}
+void f_vuint64m4x2_t () {vuint64m4x2_t t;}
 void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;}
 void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;}
 void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;}
@@ -193,14 +193,54 @@ void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
 void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
 void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
 void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void new_f_vint64m1x2_t (vint64m1x2_t t) { }   /* { dg-error {argument type 'vint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x2_t (vuint64m1x2_t t) { } /* { dg-error {argument type 'vuint64m1x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x3_t (vint64m1x3_t t) { }   /* { dg-error {argument type 'vint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x3_t (vuint64m1x3_t t) { } /* { dg-error {argument type 'vuint64m1x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x4_t (vint64m1x4_t t) { }   /* { dg-error {argument type 'vint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x4_t (vuint64m1x4_t t) { } /* { dg-error {argument type 'vuint64m1x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x5_t (vint64m1x5_t t) { }   /* { dg-error {argument type 'vint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x5_t (vuint64m1x5_t t) { } /* { dg-error {argument type 'vuint64m1x5_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x6_t (vint64m1x6_t t) { }   /* { dg-error {argument type 'vint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x6_t (vuint64m1x6_t t) { } /* { dg-error {argument type 'vuint64m1x6_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x7_t (vint64m1x7_t t) { }   /* { dg-error {argument type 'vint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x7_t (vuint64m1x7_t t) { } /* { dg-error {argument type 'vuint64m1x7_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m1x8_t (vint64m1x8_t t) { }   /* { dg-error {argument type 'vint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m1x8_t (vuint64m1x8_t t) { } /* { dg-error {argument type 'vuint64m1x8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x2_t (vint64m2x2_t t) { }   /* { dg-error {argument type 'vint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x2_t (vuint64m2x2_t t) { } /* { dg-error {argument type 'vuint64m2x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x3_t (vint64m2x3_t t) { }   /* { dg-error {argument type 'vint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x3_t (vuint64m2x3_t t) { } /* { dg-error {argument type 'vuint64m2x3_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m2x4_t (vint64m2x4_t t) { }   /* { dg-error {argument type 'vint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m2x4_t (vuint64m2x4_t t) { } /* { dg-error {argument type 'vuint64m2x4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vint64m4x2_t (vint64m4x2_t t) { }   /* { dg-error {argument type 'vint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_f_vuint64m4x2_t (vuint64m4x2_t t) { } /* { dg-error {argument type 'vuint64m4x2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+
+void new_f_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void new_f_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
index 92f4ee02d208a14f1e0f0444c3c413ee57cd4cc1..6e08f522d9f42fc24937f053de4a81dc27499245 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-2.c
@@ -54,12 +54,27 @@ void foo47 () {vint64m4_t t;}
 void foo48 () {vuint64m4_t t;}
 void foo49 () {vint64m8_t t;}
 void foo50 () {vuint64m8_t t;}
-void foo57 () {vfloat32mf2_t t;} /* { dg-error {unknown type name 'vfloat32mf2_t'} } */
-void foo58 () {vfloat32m1_t t;} /* { dg-error {unknown type name 'vfloat32m1_t'} } */
-void foo59 () {vfloat32m2_t t;} /* { dg-error {unknown type name 'vfloat32m2_t'} } */
-void foo60 () {vfloat32m4_t t;} /* { dg-error {unknown type name 'vfloat32m4_t'} } */
-void foo61 () {vfloat32m8_t t;} /* { dg-error {unknown type name 'vfloat32m8_t'} } */
-void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
-void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
-void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
-void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo57 () {vfloat32mf2_t t;}
+void foo58 () {vfloat32m1_t t;}
+void foo59 () {vfloat32m2_t t;}
+void foo60 () {vfloat32m4_t t;}
+void foo61 () {vfloat32m8_t t;}
+void foo62 () {vfloat64m1_t t;}
+void foo63 () {vfloat64m2_t t;}
+void foo64 () {vfloat64m4_t t;}
+void foo65 () {vfloat64m8_t t;}
+
+void new_foo57 (vfloat32mf2_t t) { } /* { dg-error {argument type 'vfloat32mf2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo58 (vfloat32m1_t t) { }  /* { dg-error {argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo59 (vfloat32m2_t t) { }  /* { dg-error {argument type 'vfloat32m2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo60 (vfloat32m4_t t) { }  /* { dg-error {argument type 'vfloat32m4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo61 (vfloat32m8_t t) { }  /* { dg-error {argument type 'vfloat32m8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo62 (vfloat64m1_t t) { }  /* { dg-error {argument type 'vfloat64m1_t' requires the zve64d or v ISA extension} } */
+void new_foo63 (vfloat64m2_t t) { }  /* { dg-error {argument type 'vfloat64m2_t' requires the zve64d or v ISA extension} } */
+void new_foo64 (vfloat64m4_t t) { }  /* { dg-error {argument type 'vfloat64m4_t' requires the zve64d or v ISA extension} } */
+void new_foo65 (vfloat64m8_t t) { }  /* { dg-error {argument type 'vfloat64m8_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
index 3a42572186305a44a45ab719b80a8e8821f7bf55..4fb40233509468f3fcc410f602ef1c8596778d06 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-3.c
@@ -59,7 +59,17 @@ void foo58 () {vfloat32m1_t t;}
 void foo59 () {vfloat32m2_t t;}
 void foo60 () {vfloat32m4_t t;}
 void foo61 () {vfloat32m8_t t;}
-void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
-void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
-void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
-void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo62 () {vfloat64m1_t t;}
+void foo63 () {vfloat64m2_t t;}
+void foo64 () {vfloat64m4_t t;}
+void foo65 () {vfloat64m8_t t;}
+
+void new_foo62 (vfloat64m1_t t) { } /* { dg-error {argument type 'vfloat64m1_t' requires the zve64d or v ISA extension} } */
+void new_foo63 (vfloat64m2_t t) { } /* { dg-error {argument type 'vfloat64m2_t' requires the zve64d or v ISA extension} } */
+void new_foo64 (vfloat64m4_t t) { } /* { dg-error {argument type 'vfloat64m4_t' requires the zve64d or v ISA extension} } */
+void new_foo65 (vfloat64m8_t t) { } /* { dg-error {argument type 'vfloat64m8_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
index de850e5e10dbd668ee188eb554fa514e4628620d..28b3ae708f527ebf63259537097e316b6f5d689d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-5.c
@@ -3,15 +3,15 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {vbool64_t t;} /* { dg-error {unknown type name 'vbool64_t'} } */
+void foo0 () {vbool64_t t;}
 void foo1 () {vbool32_t t;}
 void foo2 () {vbool16_t t;}
 void foo3 () {vbool8_t t;}
 void foo4 () {vbool4_t t;}
 void foo5 () {vbool2_t t;}
 void foo6 () {vbool1_t t;}
-void foo7 () {vint8mf8_t t;} /* { dg-error {unknown type name 'vint8mf8_t'} } */
-void foo8 () {vuint8mf8_t t;} /* { dg-error {unknown type name 'vuint8mf8_t'} } */
+void foo7 () {vint8mf8_t t;}
+void foo8 () {vuint8mf8_t t;}
 void foo9 () {vint8mf4_t t;}
 void foo10 () {vuint8mf4_t t;}
 void foo11 () {vint8mf2_t t;}
@@ -24,8 +24,8 @@ void foo17 () {vint8m4_t t;}
 void foo18 () {vuint8m4_t t;}
 void foo19 () {vint8m8_t t;}
 void foo20 () {vuint8m8_t t;}
-void foo21 () {vint16mf4_t t;} /* { dg-error {unknown type name 'vint16mf4_t'} } */
-void foo22 () {vuint16mf4_t t;} /* { dg-error {unknown type name 'vuint16mf4_t'} } */
+void foo21 () {vint16mf4_t t;}
+void foo22 () {vuint16mf4_t t;}
 void foo23 () {vint16mf2_t t;}
 void foo24 () {vuint16mf2_t t;}
 void foo25 () {vint16m1_t t;}
@@ -36,8 +36,8 @@ void foo29 () {vint16m4_t t;}
 void foo30 () {vuint16m4_t t;}
 void foo31 () {vint16m8_t t;}
 void foo32 () {vuint16m8_t t;}
-void foo33 () {vint32mf2_t t;} /* { dg-error {unknown type name 'vint32mf2_t'} } */
-void foo34 () {vuint32mf2_t t;} /* { dg-error {unknown type name 'vuint32mf2_t'} } */
+void foo33 () {vint32mf2_t t;}
+void foo34 () {vuint32mf2_t t;}
 void foo35 () {vint32m1_t t;}
 void foo36 () {vuint32m1_t t;}
 void foo37 () {vint32m2_t t;}
@@ -46,20 +46,50 @@ void foo39 () {vint32m4_t t;}
 void foo40 () {vuint32m4_t t;}
 void foo41 () {vint32m8_t t;}
 void foo42 () {vuint32m8_t t;}
-void foo43 () {vint64m1_t t;} /* { dg-error {unknown type name 'vint64m1_t'} } */
-void foo44 () {vuint64m1_t t;} /* { dg-error {unknown type name 'vuint64m1_t'} } */
-void foo45 () {vint64m2_t t;} /* { dg-error {unknown type name 'vint64m2_t'} } */
-void foo46 () {vuint64m2_t t;} /* { dg-error {unknown type name 'vuint64m2_t'} } */
-void foo47 () {vint64m4_t t;} /* { dg-error {unknown type name 'vint64m4_t'} } */
-void foo48 () {vuint64m4_t t;} /* { dg-error {unknown type name 'vuint64m4_t'} } */
-void foo49 () {vint64m8_t t;} /* { dg-error {unknown type name 'vint64m8_t'} } */
-void foo50 () {vuint64m8_t t;} /* { dg-error {unknown type name 'vuint64m8_t'} } */
-void foo57 () {vfloat32mf2_t t;} /* { dg-error {unknown type name 'vfloat32mf2_t'} } */
-void foo58 () {vfloat32m1_t t;} /* { dg-error {unknown type name 'vfloat32m1_t'} } */
-void foo59 () {vfloat32m2_t t;} /* { dg-error {unknown type name 'vfloat32m2_t'} } */
-void foo60 () {vfloat32m4_t t;} /* { dg-error {unknown type name 'vfloat32m4_t'} } */
-void foo61 () {vfloat32m8_t t;} /* { dg-error {unknown type name 'vfloat32m8_t'} } */
-void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
-void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
-void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
-void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
+void foo43 () {vint64m1_t t;}
+void foo44 () {vuint64m1_t t;}
+void foo45 () {vint64m2_t t;}
+void foo46 () {vuint64m2_t t;}
+void foo47 () {vint64m4_t t;}
+void foo48 () {vuint64m4_t t;}
+void foo49 () {vint64m8_t t;}
+void foo50 () {vuint64m8_t t;}
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo57 () {vfloat32mf2_t t;}
+void foo58 () {vfloat32m1_t t;}
+void foo59 () {vfloat32m2_t t;}
+void foo60 () {vfloat32m4_t t;}
+void foo61 () {vfloat32m8_t t;}
+void foo62 () {vfloat64m1_t t;}
+void foo63 () {vfloat64m2_t t;}
+void foo64 () {vfloat64m4_t t;}
+void foo65 () {vfloat64m8_t t;}
+
+void new_foo0 (vbool64_t t)  { }     /* { dg-error {argument type 'vbool64_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo7 (vint8mf8_t t)  { }    /* { dg-error {argument type 'vint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo8 (vuint8mf8_t t)  { }   /* { dg-error {argument type 'vuint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo21 (vint16mf4_t t) { }   /* { dg-error {argument type 'vint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo22 (vuint16mf4_t t) { }  /* { dg-error {argument type 'vuint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo33 (vint32mf2_t t) { }   /* { dg-error {argument type 'vint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo34 (vuint32mf2_t t) { }  /* { dg-error {argument type 'vuint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo43 (vint64m1_t t) { }    /* { dg-error {argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo44 (vuint64m1_t t) { }   /* { dg-error {argument type 'vuint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo45 (vint64m2_t t) { }    /* { dg-error {argument type 'vint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo46 (vuint64m2_t t) { }   /* { dg-error {argument type 'vuint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo47 (vint64m4_t t) { }    /* { dg-error {argument type 'vint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo48 (vuint64m4_t t) { }   /* { dg-error {argument type 'vuint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo49 (vint64m8_t t) { }    /* { dg-error {argument type 'vint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo50 (vuint64m8_t t) { }   /* { dg-error {argument type 'vuint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo57 (vfloat32mf2_t t) { } /* { dg-error {argument type 'vfloat32mf2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo58 (vfloat32m1_t t) { }  /* { dg-error {argument type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo59 (vfloat32m2_t t) { }  /* { dg-error {argument type 'vfloat32m2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo60 (vfloat32m4_t t) { }  /* { dg-error {argument type 'vfloat32m4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo61 (vfloat32m8_t t) { }  /* { dg-error {argument type 'vfloat32m8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void new_foo62 (vfloat64m1_t t) { }  /* { dg-error {argument type 'vfloat64m1_t' requires the zve64d or v ISA extension} } */
+void new_foo63 (vfloat64m2_t t) { }  /* { dg-error {argument type 'vfloat64m2_t' requires the zve64d or v ISA extension} } */
+void new_foo64 (vfloat64m4_t t) { }  /* { dg-error {argument type 'vfloat64m4_t' requires the zve64d or v ISA extension} } */
+void new_foo65 (vfloat64m8_t t) { }  /* { dg-error {argument type 'vfloat64m8_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
index 1d79b6b8eacb223dd48905486076c9ac8959ac35..e48ee39199267921fd4ea6cabf73fd79186631e8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-6.c
@@ -3,15 +3,15 @@
 
 #include "riscv_vector.h"
 
-void foo0 () {vbool64_t t;} /* { dg-error {unknown type name 'vbool64_t'} } */
+void foo0 () {vbool64_t t;}
 void foo1 () {vbool32_t t;}
 void foo2 () {vbool16_t t;}
 void foo3 () {vbool8_t t;}
 void foo4 () {vbool4_t t;}
 void foo5 () {vbool2_t t;}
 void foo6 () {vbool1_t t;}
-void foo7 () {vint8mf8_t t;} /* { dg-error {unknown type name 'vint8mf8_t'} } */
-void foo8 () {vuint8mf8_t t;} /* { dg-error {unknown type name 'vuint8mf8_t'} } */
+void foo7 () {vint8mf8_t t;}
+void foo8 () {vuint8mf8_t t;}
 void foo9 () {vint8mf4_t t;}
 void foo10 () {vuint8mf4_t t;}
 void foo11 () {vint8mf2_t t;}
@@ -24,8 +24,8 @@ void foo17 () {vint8m4_t t;}
 void foo18 () {vuint8m4_t t;}
 void foo19 () {vint8m8_t t;}
 void foo20 () {vuint8m8_t t;}
-void foo21 () {vint16mf4_t t;} /* { dg-error {unknown type name 'vint16mf4_t'} } */
-void foo22 () {vuint16mf4_t t;} /* { dg-error {unknown type name 'vuint16mf4_t'} } */
+void foo21 () {vint16mf4_t t;}
+void foo22 () {vuint16mf4_t t;}
 void foo23 () {vint16mf2_t t;}
 void foo24 () {vuint16mf2_t t;}
 void foo25 () {vint16m1_t t;}
@@ -36,8 +36,13 @@ void foo29 () {vint16m4_t t;}
 void foo30 () {vuint16m4_t t;}
 void foo31 () {vint16m8_t t;}
 void foo32 () {vuint16m8_t t;}
-void foo33 () {vint32mf2_t t;} /* { dg-error {unknown type name 'vint32mf2_t'} } */
-void foo34 () {vuint32mf2_t t;} /* { dg-error {unknown type name 'vuint32mf2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void foo33 () {vint32mf2_t t;}
+void foo34 () {vuint32mf2_t t;}
 void foo35 () {vint32m1_t t;}
 void foo36 () {vuint32m1_t t;}
 void foo37 () {vint32m2_t t;}
@@ -46,20 +51,41 @@ void foo39 () {vint32m4_t t;}
 void foo40 () {vuint32m4_t t;}
 void foo41 () {vint32m8_t t;}
 void foo42 () {vuint32m8_t t;}
-void foo43 () {vint64m1_t t;} /* { dg-error {unknown type name 'vint64m1_t'} } */
-void foo44 () {vuint64m1_t t;} /* { dg-error {unknown type name 'vuint64m1_t'} } */
-void foo45 () {vint64m2_t t;} /* { dg-error {unknown type name 'vint64m2_t'} } */
-void foo46 () {vuint64m2_t t;} /* { dg-error {unknown type name 'vuint64m2_t'} } */
-void foo47 () {vint64m4_t t;} /* { dg-error {unknown type name 'vint64m4_t'} } */
-void foo48 () {vuint64m4_t t;} /* { dg-error {unknown type name 'vuint64m4_t'} } */
-void foo49 () {vint64m8_t t;} /* { dg-error {unknown type name 'vint64m8_t'} } */
-void foo50 () {vuint64m8_t t;} /* { dg-error {unknown type name 'vuint64m8_t'} } */
-void foo57 () {vfloat32mf2_t t;} /* { dg-error {unknown type name 'vfloat32mf2_t'} } */
+void foo43 () {vint64m1_t t;}
+void foo44 () {vuint64m1_t t;}
+void foo45 () {vint64m2_t t;}
+void foo46 () {vuint64m2_t t;}
+void foo47 () {vint64m4_t t;}
+void foo48 () {vuint64m4_t t;}
+void foo49 () {vint64m8_t t;}
+void foo50 () {vuint64m8_t t;}
+void foo57 () {vfloat32mf2_t t;}
 void foo58 () {vfloat32m1_t t;}
 void foo59 () {vfloat32m2_t t;}
 void foo60 () {vfloat32m4_t t;}
 void foo61 () {vfloat32m8_t t;}
-void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
-void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
-void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
-void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
+void foo62 () {vfloat64m1_t t;}
+void foo63 () {vfloat64m2_t t;}
+void foo64 () {vfloat64m4_t t;}
+void foo65 () {vfloat64m8_t t;}
+
+void new_foo0 (vbool64_t t) { }      /* { dg-error {argument type 'vbool64_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo7 (vint8mf8_t t) { }     /* { dg-error {argument type 'vint8mf8_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo8 (vuint8mf8_t t) { }    /* { dg-error {argument type 'vuint8mf8_t' requires the minimal vector length '64' but '32'} } */
+void new_foo21 (vint16mf4_t t) { }   /* { dg-error {argument type 'vint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo22 (vuint16mf4_t t) { }  /* { dg-error {argument type 'vuint16mf4_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo33 (vint32mf2_t t) {}    /* { dg-error {argument type 'vint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo34 (vuint32mf2_t t) { }  /* { dg-error {argument type 'vuint32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo43 (vint64m1_t t) { }    /* { dg-error {argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo44 (vuint64m1_t t) { }   /* { dg-error {argument type 'vuint64m1_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo45 (vint64m2_t t) { }    /* { dg-error {argument type 'vint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo46 (vuint64m2_t t) { }   /* { dg-error {argument type 'vuint64m2_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo47 (vint64m4_t t) { }    /* { dg-error {argument type 'vint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo48 (vuint64m4_t t) { }   /* { dg-error {argument type 'vuint64m4_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo49 (vint64m8_t t) { }    /* { dg-error {argument type 'vint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo50 (vuint64m8_t t) { }   /* { dg-error {argument type 'vuint64m8_t' requires the zve64x, zve64f, zve64d or v ISA extension} } */
+void new_foo57 (vfloat32mf2_t t) { } /* { dg-error {argument type 'vfloat32mf2_t' requires the minimal vector length '64' but '32' is given} } */
+void new_foo62 (vfloat64m1_t t) { }  /* { dg-error {argument type 'vfloat64m1_t' requires the zve64d or v ISA extension} } */
+void new_foo63 (vfloat64m2_t t) { }  /* { dg-error {argument type 'vfloat64m2_t' requires the zve64d or v ISA extension} } */
+void new_foo64 (vfloat64m4_t t) { }  /* { dg-error {argument type 'vfloat64m4_t' requires the zve64d or v ISA extension} } */
+void new_foo65 (vfloat64m8_t t) { }  /* { dg-error {argument type 'vfloat64m8_t' requires the zve64d or v ISA extension} } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c
index 98a7d391d4e853e326ffd600a6ba3193f7dbd473..57ede32a400766f4586a95726cf5206a703ba126 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c
@@ -175,32 +175,67 @@ void f_vint64m2x4_t () {vint64m2x4_t t;}
 void f_vuint64m2x4_t () {vuint64m2x4_t t;}
 void f_vint64m4x2_t () {vint64m4x2_t t;}
 void f_vuint64m4x2_t () {vuint64m4x2_t t;}
-void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */
-void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */
-void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
-void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */
-void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */
-void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */
-void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */
-void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */
-void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */
-void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */
-void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */
-void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */
-void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */
-void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */
-void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */
-void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */
-void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */
-void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */
-void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */
-void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */
-void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */
-void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */
-void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */
-void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */
-void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */
-void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */
-void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */
-void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */
-void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */
+
+/* To support target attribute, the vfloat*m*x*_t need to be registered
+   in advance.  We add type and args/return value check during the
+   set current function but cannot cover below cases.  It is the same
+   behavior compared to aarch64 sve.  */
+void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;}
+void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;}
+void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;}
+void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;}
+void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;}
+void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;}
+void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;}
+void f_vfloat32m1x2_t () {vfloat32m1x2_t t;}
+void f_vfloat32m1x3_t () {vfloat32m1x3_t t;}
+void f_vfloat32m1x4_t () {vfloat32m1x4_t t;}
+void f_vfloat32m1x5_t () {vfloat32m1x5_t t;}
+void f_vfloat32m1x6_t () {vfloat32m1x6_t t;}
+void f_vfloat32m1x7_t () {vfloat32m1x7_t t;}
+void f_vfloat32m1x8_t () {vfloat32m1x8_t t;}
+void f_vfloat32m2x2_t () {vfloat32m2x2_t t;}
+void f_vfloat32m2x3_t () {vfloat32m2x3_t t;}
+void f_vfloat32m2x4_t () {vfloat32m2x4_t t;}
+void f_vfloat32m4x2_t () {vfloat32m4x2_t t;}
+void f_vfloat64m1x2_t () {vfloat64m1x2_t t;}
+void f_vfloat64m1x3_t () {vfloat64m1x3_t t;}
+void f_vfloat64m1x4_t () {vfloat64m1x4_t t;}
+void f_vfloat64m1x5_t () {vfloat64m1x5_t t;}
+void f_vfloat64m1x6_t () {vfloat64m1x6_t t;}
+void f_vfloat64m1x7_t () {vfloat64m1x7_t t;}
+void f_vfloat64m1x8_t () {vfloat64m1x8_t t;}
+void f_vfloat64m2x2_t () {vfloat64m2x2_t t;}
+void f_vfloat64m2x3_t () {vfloat64m2x3_t t;}
+void f_vfloat64m2x4_t () {vfloat64m2x4_t t;}
+void f_vfloat64m4x2_t () {vfloat64m4x2_t t;}
+
+void f_arg_vfloat32mf2x2_t (vfloat32mf2x2_t t) { } /* { dg-error {argument type 'vfloat32mf2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x3_t (vfloat32mf2x3_t t) { } /* { dg-error {argument type 'vfloat32mf2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x4_t (vfloat32mf2x4_t t) { } /* { dg-error {argument type 'vfloat32mf2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x5_t (vfloat32mf2x5_t t) { } /* { dg-error {argument type 'vfloat32mf2x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x6_t (vfloat32mf2x6_t t) { } /* { dg-error {argument type 'vfloat32mf2x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x7_t (vfloat32mf2x7_t t) { } /* { dg-error {argument type 'vfloat32mf2x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32mf2x8_t (vfloat32mf2x8_t t) { } /* { dg-error {argument type 'vfloat32mf2x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x2_t (vfloat32m1x2_t t) { } /* { dg-error {argument type 'vfloat32m1x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x3_t (vfloat32m1x3_t t) { } /* { dg-error {argument type 'vfloat32m1x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x4_t (vfloat32m1x4_t t) { } /* { dg-error {argument type 'vfloat32m1x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x5_t (vfloat32m1x5_t t) { } /* { dg-error {argument type 'vfloat32m1x5_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x6_t (vfloat32m1x6_t t) { } /* { dg-error {argument type 'vfloat32m1x6_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x7_t (vfloat32m1x7_t t) { } /* { dg-error {argument type 'vfloat32m1x7_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m1x8_t (vfloat32m1x8_t t) { } /* { dg-error {argument type 'vfloat32m1x8_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m2x2_t (vfloat32m2x2_t t) { } /* { dg-error {argument type 'vfloat32m2x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m2x3_t (vfloat32m2x3_t t) { } /* { dg-error {argument type 'vfloat32m2x3_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m2x4_t (vfloat32m2x4_t t) { } /* { dg-error {argument type 'vfloat32m2x4_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat32m4x2_t (vfloat32m4x2_t t) { } /* { dg-error {argument type 'vfloat32m4x2_t' requires the zve32f, zve64f, zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x2_t (vfloat64m1x2_t t) { } /* { dg-error {argument type 'vfloat64m1x2_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x3_t (vfloat64m1x3_t t) { } /* { dg-error {argument type 'vfloat64m1x3_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x4_t (vfloat64m1x4_t t) { } /* { dg-error {argument type 'vfloat64m1x4_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x5_t (vfloat64m1x5_t t) { } /* { dg-error {argument type 'vfloat64m1x5_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x6_t (vfloat64m1x6_t t) { } /* { dg-error {argument type 'vfloat64m1x6_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x7_t (vfloat64m1x7_t t) { } /* { dg-error {argument type 'vfloat64m1x7_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m1x8_t (vfloat64m1x8_t t) { } /* { dg-error {argument type 'vfloat64m1x8_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m2x2_t (vfloat64m2x2_t t) { } /* { dg-error {argument type 'vfloat64m2x2_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m2x3_t (vfloat64m2x3_t t) { } /* { dg-error {argument type 'vfloat64m2x3_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m2x4_t (vfloat64m2x4_t t) { } /* { dg-error {argument type 'vfloat64m2x4_t' requires the zve64d or v ISA extension} } */
+void f_arg_vfloat64m4x2_t (vfloat64m4x2_t t) { } /* { dg-error {argument type 'vfloat64m4x2_t' requires the zve64d or v ISA extension} } */