SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided. In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.
The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15. Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound. The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound. This in turn required adding
an extra bit to the field.
else if ((detail->data[0].i & -detail->data[0].i) == detail->data[0].i)
handler (_("expected a list of %d registers at operand %d -- `%s'"),
get_log2 (detail->data[0].i), idx + 1, str);
+ else if (detail->data[0].i == 0x14)
+ handler (_("expected a list of %d or %d registers at"
+ " operand %d -- `%s'"),
+ 2, 4, idx + 1, str);
else
handler (_("invalid number of registers in the list"
" at operand %d -- `%s'"), idx + 1, str);
if (detail->data[0].i == (1 << 1))
handler (_("the register list must have a stride of %d"
" at operand %d -- `%s'"), 1, idx + 1, str);
+ else if (detail->data[0].i == 0x12 || detail->data[0].i == 0x102)
+ handler (_("the register list must have a stride of %d or %d"
+ " at operand %d -- `%s`"), 1,
+ detail->data[0].i == 0x12 ? 4 : 8, idx + 1, str);
else
handler (_("invalid register stride at operand %d -- `%s'"),
idx + 1, str);
case AARCH64_OPND_SVE_PNg4_10:
case AARCH64_OPND_SVE_PNn:
case AARCH64_OPND_SVE_PNt:
+ case AARCH64_OPND_SME_PNg3:
reg_type = REG_TYPE_PN;
goto vector_reg;
case AARCH64_OPND_SME_Zdnx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
+ case AARCH64_OPND_SME_Ztx2_STRIDED:
+ case AARCH64_OPND_SME_Ztx4_STRIDED:
reg_type = REG_TYPE_Z;
goto vector_reg_list;
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-2-invalid.s
+#error_output: sme2-2-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1b 0,pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1b {z0\.b-z1\.b},0,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,0'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b-z2\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z2\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z1\.b},p8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8/m,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8\.b,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn7/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[w0\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[xzr\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-18,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-15,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#13,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#15,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#16,mul vl\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z4\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z2\.b-z5\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z3\.b-z6\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z3\.b},p8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8/m,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8\.b,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn0/z,\[x0\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn7/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[w0\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[xzr\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#4\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-36,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-31,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-30,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-29,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-14,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-3,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-2,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#2,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#3,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#25,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#26,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#27,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#29,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#30,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#31,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#32,mul vl\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z8\.b,z16\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z2\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z3\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z4\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z5\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z6\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z7\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z9\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z15\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z16\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z23\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z24\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z31\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z16\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z9\.b,z17\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z10\.b,z18\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z11\.b,z19\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z12\.b,z20\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z13\.b,z21\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z14\.b,z22\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z15\.b,z23\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z24\.b,z0\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z25\.b,z1\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z26\.b,z2\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z27\.b,z3\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z28\.b,z4\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z29\.b,z5\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z30\.b,z6\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z31\.b,z7\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z8\.b,z0\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.h,z8\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z8\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z8\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `ld1b {z0,z8},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z8\.b},p8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[w0\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[xzr\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-17,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-15,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#13,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#15,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#16,mul vl\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z4\.b,z8\.b,z12\.b,z16\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z5\.b,z9\.b,z13\.b,z17\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z6\.b,z10\.b,z14\.b,z18\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z7\.b,z11\.b,z15\.b,z19\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z12\.b,z16\.b,z20\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z9\.b,z13\.b,z17\.b,z21\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z10\.b,z14\.b,z18\.b,z22\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z11\.b,z15\.b,z19\.b,z23\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z12\.b,z16\.b,z20\.b,z24\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z13\.b,z17\.b,z21\.b,z25\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z14\.b,z18\.b,z22\.b,z26\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z15\.b,z19\.b,z23\.b,z27\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z20\.b,z24\.b,z28\.b,z0\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z2\.b,z4\.b,z6\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z3\.b,z6\.b,z9\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z8\.b,z16\.b,z24\.b},pn8/z,\[x0\]`
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z4\.b,z5\.b,z6\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z9\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z1\.b,z3\.b,z7\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.h,z4\.h,z8\.b,z12\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},p8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[w0\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[xzr\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-1\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-64,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-36,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-31,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-3,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-2,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#1,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#2,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#3,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#25,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#26,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#27,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#29,mul vl\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#32,mul vl\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b-z2\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z2\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z1\.b},p8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8/m,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8\.b,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn0/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn7/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[w0,w1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[xzr,x1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[sp,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,w1,sxtw\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,w1,uxtw\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z4\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z2\.b-z5\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z3\.b-z6\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z3\.b},p8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8/m,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8\.b,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn0/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn7/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[w0,w1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[xzr,x1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[sp,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,w1,sxtw\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,w1,uxtw\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z2\.b},pn8/z,\[x0,x1\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z3\.b},pn8/z,\[x0,x1\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z4\.b},pn8/z,\[x0,x1\]`
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z16\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z24\.b,z0\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z8\.b,z0\.b},pn8/z,\[x0,x1\]`
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z8\.h},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z8\.b},p8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[w0,w30\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[xzr,xzr\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z4\.b,z8\.b,z12\.b,z16\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z20\.b,z24\.b,z28\.b,z0\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},p8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[w0,w30\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[xzr,xzr\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#1\]'
--- /dev/null
+ ld1b 0, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, 0, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, 0
+
+ ld1b { z0.b }, pn8/z, [x0]
+ ld1b { z0.b - z2.b }, pn8/z, [x0]
+ ld1b { z1.b - z2.b }, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, p8/z, [x0]
+ ld1b { z0.b - z1.b }, pn8, [x0]
+ ld1b { z0.b - z1.b }, pn8/m, [x0]
+ ld1b { z0.b - z1.b }, pn8.b, [x0]
+ ld1b { z0.b - z1.b }, pn7/z, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, [w0]
+ ld1b { z0.b - z1.b }, pn8/z, [xzr]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-32, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-18, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-15, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-1, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #1, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #13, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #15, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #16, mul vl]
+
+ ld1b { z1.b - z4.b }, pn8/z, [x0]
+ ld1b { z2.b - z5.b }, pn8/z, [x0]
+ ld1b { z3.b - z6.b }, pn8/z, [x0]
+ ld1b { z0.b - z3.b }, p8/z, [x0]
+ ld1b { z0.b - z3.b }, pn8, [x0]
+ ld1b { z0.b - z3.b }, pn8/m, [x0]
+ ld1b { z0.b - z3.b }, pn8.b, [x0]
+ ld1b { z0.b - z3.b }, pn0/z, [x0]
+ ld1b { z0.b - z3.b }, pn7/z, [x0]
+ ld1b { z0.b - z3.b }, pn8/z, [w0]
+ ld1b { z0.b - z3.b }, pn8/z, [xzr]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #4]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-36, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-31, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-30, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-29, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-14, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-3, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-2, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-1, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #1, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #2, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #3, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #14, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #25, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #26, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #27, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #29, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #30, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #31, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #32, mul vl]
+
+ ld1b { z0.b, z8.b, z16.s }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.s }, pn8/z, [x0]
+
+ ld1b { z0.b, z2.b }, pn8/z, [x0]
+ ld1b { z0.b, z3.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b }, pn8/z, [x0]
+ ld1b { z0.b, z5.b }, pn8/z, [x0]
+ ld1b { z0.b, z6.b }, pn8/z, [x0]
+ ld1b { z0.b, z7.b }, pn8/z, [x0]
+ ld1b { z0.b, z9.b }, pn8/z, [x0]
+ ld1b { z0.b, z15.b }, pn8/z, [x0]
+ ld1b { z0.b, z16.b }, pn8/z, [x0]
+ ld1b { z0.b, z23.b }, pn8/z, [x0]
+ ld1b { z0.b, z24.b }, pn8/z, [x0]
+ ld1b { z0.b, z31.b }, pn8/z, [x0]
+ ld1b { z8.b, z16.b }, pn8/z, [x0]
+ ld1b { z9.b, z17.b }, pn8/z, [x0]
+ ld1b { z10.b, z18.b }, pn8/z, [x0]
+ ld1b { z11.b, z19.b }, pn8/z, [x0]
+ ld1b { z12.b, z20.b }, pn8/z, [x0]
+ ld1b { z13.b, z21.b }, pn8/z, [x0]
+ ld1b { z14.b, z22.b }, pn8/z, [x0]
+ ld1b { z15.b, z23.b }, pn8/z, [x0]
+ ld1b { z24.b, z0.b }, pn8/z, [x0]
+ ld1b { z25.b, z1.b }, pn8/z, [x0]
+ ld1b { z26.b, z2.b }, pn8/z, [x0]
+ ld1b { z27.b, z3.b }, pn8/z, [x0]
+ ld1b { z28.b, z4.b }, pn8/z, [x0]
+ ld1b { z29.b, z5.b }, pn8/z, [x0]
+ ld1b { z30.b, z6.b }, pn8/z, [x0]
+ ld1b { z31.b, z7.b }, pn8/z, [x0]
+ ld1b { z8.b, z0.b }, pn8/z, [x0]
+ ld1b { z0.h, z8.b }, pn8/z, [x0]
+ ld1b { z0.b, z8.h }, pn8/z, [x0]
+ ld1b { z0.h, z8.h }, pn8/z, [x0]
+ ld1b { z0, z8 }, pn8/z, [x0]
+ ld1b { z0.b, z8.b }, p8/z, [x0]
+ ld1b { z0.b, z8.b }, pn8/z, [w0]
+ ld1b { z0.b, z8.b }, pn8/z, [xzr]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-16]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-1]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-32, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-17, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-15, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-1, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #13, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #15, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #16, mul vl]
+
+ ld1b { z4.b, z8.b, z12.b, z16.b }, pn8/z, [x0]
+ ld1b { z5.b, z9.b, z13.b, z17.b }, pn8/z, [x0]
+ ld1b { z6.b, z10.b, z14.b, z18.b }, pn8/z, [x0]
+ ld1b { z7.b, z11.b, z15.b, z19.b }, pn8/z, [x0]
+ ld1b { z8.b, z12.b, z16.b, z20.b }, pn8/z, [x0]
+ ld1b { z9.b, z13.b, z17.b, z21.b }, pn8/z, [x0]
+ ld1b { z10.b, z14.b, z18.b, z22.b }, pn8/z, [x0]
+ ld1b { z11.b, z15.b, z19.b, z23.b }, pn8/z, [x0]
+ ld1b { z12.b, z16.b, z20.b, z24.b }, pn8/z, [x0]
+ ld1b { z13.b, z17.b, z21.b, z25.b }, pn8/z, [x0]
+ ld1b { z14.b, z18.b, z22.b, z26.b }, pn8/z, [x0]
+ ld1b { z15.b, z19.b, z23.b, z27.b }, pn8/z, [x0]
+ ld1b { z20.b, z24.b, z28.b, z0.b }, pn8/z, [x0]
+ ld1b { z0.b, z2.b, z4.b, z6.b }, pn8/z, [x0]
+ ld1b { z0.b, z3.b, z6.b, z9.b }, pn8/z, [x0]
+ ld1b { z0.b, z8.b, z16.b, z24.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z5.b, z6.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z9.b }, pn8/z, [x0]
+ ld1b { z0.b, z1.b, z3.b, z7.b }, pn8/z, [x0]
+ ld1b { z0.h, z4.h, z8.b, z12.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.h, z12.h }, pn8/z, [x0]
+ ld1b { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, p8/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [w0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [xzr]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-64, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-36, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-31, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-3, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-2, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-1, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #1, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #2, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #3, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #25, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #26, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #27, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #29, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #32, mul vl]
+
+ ld1b { z0.b - z2.b }, pn8/z, [x0, x1]
+ ld1b { z1.b - z2.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, p8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/m, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8.b, [x0, x1]
+ ld1b { z0.b - z1.b }, pn0/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn7/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [w0, w1]
+ ld1b { z0.b - z1.b }, pn8/z, [xzr, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [sp, sp]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #2]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #3]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #4]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, w1, sxtw]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, w1, uxtw]
+
+ ld1b { z1.b - z4.b }, pn8/z, [x0, x1]
+ ld1b { z2.b - z5.b }, pn8/z, [x0, x1]
+ ld1b { z3.b - z6.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, p8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/m, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8.b, [x0, x1]
+ ld1b { z0.b - z3.b }, pn0/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn7/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [w0, w1]
+ ld1b { z0.b - z3.b }, pn8/z, [xzr, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [sp, sp]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #1]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #2]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #3]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #4]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, w1, sxtw]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, w1, uxtw]
+
+ ld1b { z0.b, z2.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z3.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z4.b }, pn8/z, [x0, x1]
+ ld1b { z8.b, z16.b }, pn8/z, [x0, x1]
+ ld1b { z24.b, z0.b }, pn8/z, [x0, x1]
+ ld1b { z8.b, z0.b }, pn8/z, [x0, x1]
+ ld1b { z0.h, z8.h }, pn8/z, [x0, x1]
+ ld1b { z0.b, z8.b }, p8/z, [x0, x1]
+ ld1b { z0.b, z8.b }, pn8/z, [w0, w30]
+ ld1b { z0.b, z8.b }, pn8/z, [xzr, xzr]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, sp]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #1]
+
+ ld1b { z4.b, z8.b, z12.b, z16.b }, pn8/z, [x0, x1]
+ ld1b { z20.b, z24.b, z28.b, z0.b }, pn8/z, [x0, x1]
+ ld1b { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, p8/z, [x0, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [w0, w30]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [xzr, xzr]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, sp]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #1]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-2.s
+#error_output: sme2-2-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z1\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z30\.b-z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z12\.b-z13\.b},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z3\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z28\.b-z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z8\.b-z11\.b},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z8\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z9\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z10\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z4\.b,z12\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z6\.b,z14\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z7\.b,z15\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z24\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z25\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z26\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z27\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z20\.b,z28\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z21\.b,z29\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z22\.b,z30\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z23\.b,z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z1\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z30\.b-z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z14\.b-z15\.b},pn9/z,\[x26,x3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z3\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z28\.b-z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z8\.b-z11\.b},pn11/z,\[x27,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z8\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z9\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z10\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z4\.b,z12\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z6\.b,z14\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z7\.b,z15\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z24\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z25\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z26\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z27\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z20\.b,z28\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z21\.b,z29\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z22\.b,z30\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z23\.b,z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn14/z,\[x15,x24\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11/z,\[x4,x6\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z1\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z30\.b-z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z12\.b-z13\.b},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z3\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z28\.b-z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z8\.b-z11\.b},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z8\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z9\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z10\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z4\.b,z12\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z6\.b,z14\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z7\.b,z15\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z24\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z25\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z26\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z27\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z20\.b,z28\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z21\.b,z29\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z22\.b,z30\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z23\.b,z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z1\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z30\.b-z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z14\.b-z15\.b},pn9/z,\[x26,x3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z3\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z28\.b-z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z8\.b-z11\.b},pn11/z,\[x27,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z8\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z9\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z10\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z4\.b,z12\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z6\.b,z14\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z7\.b,z15\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z24\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z25\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z26\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z27\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z20\.b,z28\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z21\.b,z29\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z22\.b,z30\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z23\.b,z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn14/z,\[x15,x24\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11/z,\[x4,x6\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z1\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z30\.b-z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z12\.b-z13\.b},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z3\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z28\.b-z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z8\.b-z11\.b},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z8\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z9\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z10\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z4\.b,z12\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z6\.b,z14\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z7\.b,z15\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z24\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z25\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z26\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z27\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z20\.b,z28\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z21\.b,z29\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z22\.b,z30\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z23\.b,z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z1\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z30\.b-z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z14\.b-z15\.b},pn9,\[x26,x3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z3\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z28\.b-z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z8\.b-z11\.b},pn11,\[x27,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z8\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z9\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z10\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z4\.b,z12\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z6\.b,z14\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z7\.b,z15\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z24\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z25\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z26\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z27\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z20\.b,z28\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z21\.b,z29\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z22\.b,z30\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z23\.b,z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn14,\[x15,x24\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11,\[x4,x6\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z1\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z30\.b-z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z12\.b-z13\.b},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z3\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z28\.b-z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z8\.b-z11\.b},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z8\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z9\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z10\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z4\.b,z12\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z6\.b,z14\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z7\.b,z15\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z24\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z25\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z26\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z27\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z20\.b,z28\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z21\.b,z29\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z22\.b,z30\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z23\.b,z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z1\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z30\.b-z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z14\.b-z15\.b},pn9,\[x26,x3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z3\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z28\.b-z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z8\.b-z11\.b},pn11,\[x27,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z8\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z9\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z10\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z4\.b,z12\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z6\.b,z14\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z7\.b,z15\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z24\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z25\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z26\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z27\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z20\.b,z28\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z21\.b,z29\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z22\.b,z30\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z23\.b,z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn14,\[x15,x24\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1,lsl#0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0,X1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp,x1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11,\[x4,x6\]'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a040001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0401c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0\]
+[^:]+: a04003c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30\]
+[^:]+: a04003e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp\]
+[^:]+: a0480000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0470000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b156c ld1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a040801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0409c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0\]
+[^:]+: a04083c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30\]
+[^:]+: a04083e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp\]
+[^:]+: a0488000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a0478000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a0458e28 ld1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400001 ld1b {z1\.b, z9\.b}, pn8/z, \[x0\]
+[^:]+: a1400002 ld1b {z2\.b, z10\.b}, pn8/z, \[x0\]
+[^:]+: a1400003 ld1b {z3\.b, z11\.b}, pn8/z, \[x0\]
+[^:]+: a1400004 ld1b {z4\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1400005 ld1b {z5\.b, z13\.b}, pn8/z, \[x0\]
+[^:]+: a1400006 ld1b {z6\.b, z14\.b}, pn8/z, \[x0\]
+[^:]+: a1400007 ld1b {z7\.b, z15\.b}, pn8/z, \[x0\]
+[^:]+: a1400010 ld1b {z16\.b, z24\.b}, pn8/z, \[x0\]
+[^:]+: a1400011 ld1b {z17\.b, z25\.b}, pn8/z, \[x0\]
+[^:]+: a1400012 ld1b {z18\.b, z26\.b}, pn8/z, \[x0\]
+[^:]+: a1400013 ld1b {z19\.b, z27\.b}, pn8/z, \[x0\]
+[^:]+: a1400014 ld1b {z20\.b, z28\.b}, pn8/z, \[x0\]
+[^:]+: a1400015 ld1b {z21\.b, z29\.b}, pn8/z, \[x0\]
+[^:]+: a1400016 ld1b {z22\.b, z30\.b}, pn8/z, \[x0\]
+[^:]+: a1400017 ld1b {z23\.b, z31\.b}, pn8/z, \[x0\]
+[^:]+: a1401c00 ld1b {z0\.b, z8\.b}, pn15/z, \[x0\]
+[^:]+: a14003c0 ld1b {z0\.b, z8\.b}, pn8/z, \[x30\]
+[^:]+: a14003e0 ld1b {z0\.b, z8\.b}, pn8/z, \[sp\]
+[^:]+: a1480000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1470000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1430ac3 ld1b {z3\.b, z11\.b}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408001 ld1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0\]
+[^:]+: a1408002 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0\]
+[^:]+: a1408003 ld1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0\]
+[^:]+: a1408010 ld1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0\]
+[^:]+: a1408011 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0\]
+[^:]+: a1408012 ld1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0\]
+[^:]+: a1408013 ld1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0\]
+[^:]+: a1409c00 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0\]
+[^:]+: a14083c0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30\]
+[^:]+: a14083e0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp\]
+[^:]+: a1488000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a1478000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a1429ba2 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14/z, \[x29, #8, mul vl\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0011c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00103c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00103e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a003074e ld1b {z14\.b-z15\.b}, pn9/z, \[x26, x3\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
+[^:]+: a001801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a0019c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0, x1\]
+[^:]+: a00183c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30, x1\]
+[^:]+: a00183e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp, x1\]
+[^:]+: a01e8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x30\]
+[^:]+: a01f8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a0018f68 ld1b {z8\.b-z11\.b}, pn11/z, \[x27, x1\]
+[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010001 ld1b {z1\.b, z9\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010002 ld1b {z2\.b, z10\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010003 ld1b {z3\.b, z11\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010004 ld1b {z4\.b, z12\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010005 ld1b {z5\.b, z13\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010006 ld1b {z6\.b, z14\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010007 ld1b {z7\.b, z15\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010010 ld1b {z16\.b, z24\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010011 ld1b {z17\.b, z25\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010012 ld1b {z18\.b, z26\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010013 ld1b {z19\.b, z27\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010014 ld1b {z20\.b, z28\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010015 ld1b {z21\.b, z29\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010016 ld1b {z22\.b, z30\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1010017 ld1b {z23\.b, z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1011c00 ld1b {z0\.b, z8\.b}, pn15/z, \[x0, x1\]
+[^:]+: a10103c0 ld1b {z0\.b, z8\.b}, pn8/z, \[x30, x1\]
+[^:]+: a10103e0 ld1b {z0\.b, z8\.b}, pn8/z, \[sp, x1\]
+[^:]+: a11e0000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x30\]
+[^:]+: a11f0000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a11819e5 ld1b {z5\.b, z13\.b}, pn14/z, \[x15, x24\]
+[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018001 ld1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018002 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018003 ld1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018010 ld1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018011 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018012 ld1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1018013 ld1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0, x1\]
+[^:]+: a1019c00 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0, x1\]
+[^:]+: a10183c0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30, x1\]
+[^:]+: a10183e0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp, x1\]
+[^:]+: a11e8000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x30\]
+[^:]+: a11f8000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, xzr\]
+[^:]+: a1068c91 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11/z, \[x4, x6\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
+[^:]+: a040001f ldnt1b {z30\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0401c01 ldnt1b {z0\.b-z1\.b}, pn15/z, \[x0\]
+[^:]+: a04003c1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x30\]
+[^:]+: a04003e1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[sp\]
+[^:]+: a0480001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0470001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b156d ldnt1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
+[^:]+: a040801d ldnt1b {z28\.b-z31\.b}, pn8/z, \[x0\]
+[^:]+: a0409c01 ldnt1b {z0\.b-z3\.b}, pn15/z, \[x0\]
+[^:]+: a04083c1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x30\]
+[^:]+: a04083e1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[sp\]
+[^:]+: a0488001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a0478001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a0458e29 ldnt1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
+[^:]+: a1400009 ldnt1b {z1\.b, z9\.b}, pn8/z, \[x0\]
+[^:]+: a140000a ldnt1b {z2\.b, z10\.b}, pn8/z, \[x0\]
+[^:]+: a140000b ldnt1b {z3\.b, z11\.b}, pn8/z, \[x0\]
+[^:]+: a140000c ldnt1b {z4\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a140000d ldnt1b {z5\.b, z13\.b}, pn8/z, \[x0\]
+[^:]+: a140000e ldnt1b {z6\.b, z14\.b}, pn8/z, \[x0\]
+[^:]+: a140000f ldnt1b {z7\.b, z15\.b}, pn8/z, \[x0\]
+[^:]+: a1400018 ldnt1b {z16\.b, z24\.b}, pn8/z, \[x0\]
+[^:]+: a1400019 ldnt1b {z17\.b, z25\.b}, pn8/z, \[x0\]
+[^:]+: a140001a ldnt1b {z18\.b, z26\.b}, pn8/z, \[x0\]
+[^:]+: a140001b ldnt1b {z19\.b, z27\.b}, pn8/z, \[x0\]
+[^:]+: a140001c ldnt1b {z20\.b, z28\.b}, pn8/z, \[x0\]
+[^:]+: a140001d ldnt1b {z21\.b, z29\.b}, pn8/z, \[x0\]
+[^:]+: a140001e ldnt1b {z22\.b, z30\.b}, pn8/z, \[x0\]
+[^:]+: a140001f ldnt1b {z23\.b, z31\.b}, pn8/z, \[x0\]
+[^:]+: a1401c08 ldnt1b {z0\.b, z8\.b}, pn15/z, \[x0\]
+[^:]+: a14003c8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x30\]
+[^:]+: a14003e8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[sp\]
+[^:]+: a1480008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1470008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1430acb ldnt1b {z3\.b, z11\.b}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
+[^:]+: a1408009 ldnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0\]
+[^:]+: a140800a ldnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0\]
+[^:]+: a140800b ldnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0\]
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+[^:]+: a060801d stnt1b {z28\.b-z31\.b}, pn8, \[x0\]
+[^:]+: a0609c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0\]
+[^:]+: a06083c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30\]
+[^:]+: a06083e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp\]
+[^:]+: a0688001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a0678001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #28, mul vl\]
+[^:]+: a0658e29 stnt1b {z8\.b-z11\.b}, pn11, \[x17, #20, mul vl\]
+[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
+[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
+[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
+[^:]+: a1600009 stnt1b {z1\.b, z9\.b}, pn8, \[x0\]
+[^:]+: a160000a stnt1b {z2\.b, z10\.b}, pn8, \[x0\]
+[^:]+: a160000b stnt1b {z3\.b, z11\.b}, pn8, \[x0\]
+[^:]+: a160000c stnt1b {z4\.b, z12\.b}, pn8, \[x0\]
+[^:]+: a160000d stnt1b {z5\.b, z13\.b}, pn8, \[x0\]
+[^:]+: a160000e stnt1b {z6\.b, z14\.b}, pn8, \[x0\]
+[^:]+: a160000f stnt1b {z7\.b, z15\.b}, pn8, \[x0\]
+[^:]+: a1600018 stnt1b {z16\.b, z24\.b}, pn8, \[x0\]
+[^:]+: a1600019 stnt1b {z17\.b, z25\.b}, pn8, \[x0\]
+[^:]+: a160001a stnt1b {z18\.b, z26\.b}, pn8, \[x0\]
+[^:]+: a160001b stnt1b {z19\.b, z27\.b}, pn8, \[x0\]
+[^:]+: a160001c stnt1b {z20\.b, z28\.b}, pn8, \[x0\]
+[^:]+: a160001d stnt1b {z21\.b, z29\.b}, pn8, \[x0\]
+[^:]+: a160001e stnt1b {z22\.b, z30\.b}, pn8, \[x0\]
+[^:]+: a160001f stnt1b {z23\.b, z31\.b}, pn8, \[x0\]
+[^:]+: a1601c08 stnt1b {z0\.b, z8\.b}, pn15, \[x0\]
+[^:]+: a16003c8 stnt1b {z0\.b, z8\.b}, pn8, \[x30\]
+[^:]+: a16003e8 stnt1b {z0\.b, z8\.b}, pn8, \[sp\]
+[^:]+: a1680008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a1670008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, #14, mul vl\]
+[^:]+: a1630acb stnt1b {z3\.b, z11\.b}, pn10, \[x22, #6, mul vl\]
+[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
+[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
+[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
+[^:]+: a1608009 stnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0\]
+[^:]+: a160800a stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0\]
+[^:]+: a160800b stnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0\]
+[^:]+: a1608018 stnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8, \[x0\]
+[^:]+: a1608019 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0\]
+[^:]+: a160801a stnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0\]
+[^:]+: a160801b stnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0\]
+[^:]+: a1609c08 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0\]
+[^:]+: a16083c8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30\]
+[^:]+: a16083e8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp\]
+[^:]+: a1688008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a1678008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #28, mul vl\]
+[^:]+: a1629baa stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14, \[x29, #8, mul vl\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
+[^:]+: a021001f stnt1b {z30\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0211c01 stnt1b {z0\.b-z1\.b}, pn15, \[x0, x1\]
+[^:]+: a02103c1 stnt1b {z0\.b-z1\.b}, pn8, \[x30, x1\]
+[^:]+: a02103e1 stnt1b {z0\.b-z1\.b}, pn8, \[sp, x1\]
+[^:]+: a03e0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x30\]
+[^:]+: a03f0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, xzr\]
+[^:]+: a023074f stnt1b {z14\.b-z15\.b}, pn9, \[x26, x3\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
+[^:]+: a021801d stnt1b {z28\.b-z31\.b}, pn8, \[x0, x1\]
+[^:]+: a0219c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0, x1\]
+[^:]+: a02183c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30, x1\]
+[^:]+: a02183e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp, x1\]
+[^:]+: a03e8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x30\]
+[^:]+: a03f8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, xzr\]
+[^:]+: a0218f69 stnt1b {z8\.b-z11\.b}, pn11, \[x27, x1\]
+[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
+[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
+[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
+[^:]+: a1210009 stnt1b {z1\.b, z9\.b}, pn8, \[x0, x1\]
+[^:]+: a121000a stnt1b {z2\.b, z10\.b}, pn8, \[x0, x1\]
+[^:]+: a121000b stnt1b {z3\.b, z11\.b}, pn8, \[x0, x1\]
+[^:]+: a121000c stnt1b {z4\.b, z12\.b}, pn8, \[x0, x1\]
+[^:]+: a121000d stnt1b {z5\.b, z13\.b}, pn8, \[x0, x1\]
+[^:]+: a121000e stnt1b {z6\.b, z14\.b}, pn8, \[x0, x1\]
+[^:]+: a121000f stnt1b {z7\.b, z15\.b}, pn8, \[x0, x1\]
+[^:]+: a1210018 stnt1b {z16\.b, z24\.b}, pn8, \[x0, x1\]
+[^:]+: a1210019 stnt1b {z17\.b, z25\.b}, pn8, \[x0, x1\]
+[^:]+: a121001a stnt1b {z18\.b, z26\.b}, pn8, \[x0, x1\]
+[^:]+: a121001b stnt1b {z19\.b, z27\.b}, pn8, \[x0, x1\]
+[^:]+: a121001c stnt1b {z20\.b, z28\.b}, pn8, \[x0, x1\]
+[^:]+: a121001d stnt1b {z21\.b, z29\.b}, pn8, \[x0, x1\]
+[^:]+: a121001e stnt1b {z22\.b, z30\.b}, pn8, \[x0, x1\]
+[^:]+: a121001f stnt1b {z23\.b, z31\.b}, pn8, \[x0, x1\]
+[^:]+: a1211c08 stnt1b {z0\.b, z8\.b}, pn15, \[x0, x1\]
+[^:]+: a12103c8 stnt1b {z0\.b, z8\.b}, pn8, \[x30, x1\]
+[^:]+: a12103e8 stnt1b {z0\.b, z8\.b}, pn8, \[sp, x1\]
+[^:]+: a13e0008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x30\]
+[^:]+: a13f0008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, xzr\]
+[^:]+: a13819ed stnt1b {z5\.b, z13\.b}, pn14, \[x15, x24\]
+[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
+[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
+[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
+[^:]+: a1218009 stnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0, x1\]
+[^:]+: a121800a stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0, x1\]
+[^:]+: a121800b stnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0, x1\]
+[^:]+: a1218018 stnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8, \[x0, x1\]
+[^:]+: a1218019 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0, x1\]
+[^:]+: a121801a stnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0, x1\]
+[^:]+: a121801b stnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0, x1\]
+[^:]+: a1219c08 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0, x1\]
+[^:]+: a12183c8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30, x1\]
+[^:]+: a12183e8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp, x1\]
+[^:]+: a13e8008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x30\]
+[^:]+: a13f8008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, xzr\]
+[^:]+: a1268c99 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11, \[x4, x6\]
--- /dev/null
+ ld1b { z0.b - z1.b }, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B - Z1.B }, PN8/Z, [X0]
+ ld1b { z30.b - z31.b }, pn8/z, [x0]
+ ld1b { z0.b - z1.b }, pn15/z, [x0]
+ ld1b { z0.b - z1.b }, pn8/z, [x30]
+ ld1b { z0.b - z1.b }, pn8/z, [sp]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
+ ld1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
+
+ ld1b { z0.b - z3.b }, pn8/z, [x0]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B - Z3.B }, PN8/Z, [X0]
+ ld1b { z28.b - z31.b }, pn8/z, [x0]
+ ld1b { z0.b - z3.b }, pn15/z, [x0]
+ ld1b { z0.b - z3.b }, pn8/z, [x30]
+ ld1b { z0.b - z3.b }, pn8/z, [sp]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
+ ld1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
+
+ ld1b { z0.b, z8.b }, pn8/z, [x0]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B, Z8.B }, PN8/Z, [X0]
+ ld1b { z1.b, z9.b }, pn8/z, [x0]
+ ld1b { z2.b, z10.b }, pn8/z, [x0]
+ ld1b { z3.b, z11.b }, pn8/z, [x0]
+ ld1b { z4.b, z12.b }, pn8/z, [x0]
+ ld1b { z5.b, z13.b }, pn8/z, [x0]
+ ld1b { z6.b, z14.b }, pn8/z, [x0]
+ ld1b { z7.b, z15.b }, pn8/z, [x0]
+ ld1b { z16.b, z24.b }, pn8/z, [x0]
+ ld1b { z17.b, z25.b }, pn8/z, [x0]
+ ld1b { z18.b, z26.b }, pn8/z, [x0]
+ ld1b { z19.b, z27.b }, pn8/z, [x0]
+ ld1b { z20.b, z28.b }, pn8/z, [x0]
+ ld1b { z21.b, z29.b }, pn8/z, [x0]
+ ld1b { z22.b, z30.b }, pn8/z, [x0]
+ ld1b { z23.b, z31.b }, pn8/z, [x0]
+ ld1b { z0.b, z8.b }, pn15/z, [x0]
+ ld1b { z0.b, z8.b }, pn8/z, [x30]
+ ld1b { z0.b, z8.b }, pn8/z, [sp]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #-16, mul vl]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, #14, mul vl]
+ ld1b { z3.b, z11.b }, pn10/z, [x22, #6, mul vl]
+
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #0, mul vl]
+ LD1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0]
+ ld1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0]
+ ld1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0]
+ ld1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0]
+ ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0]
+ ld1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0]
+ ld1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0]
+ ld1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32, mul vl]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #28, mul vl]
+ ld1b { z2.b, z6.b, z10.b, z14.b }, pn14/z, [x29, #8, mul vl]
+
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
+ ld1b { z30.b - z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn15/z, [x0, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x30, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [sp, x1]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, x30]
+ ld1b { z0.b - z1.b }, pn8/z, [x0, xzr]
+ ld1b { z14.b - z15.b }, pn9/z, [x26, x3]
+
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
+ ld1b { z28.b - z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn15/z, [x0, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x30, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [sp, x1]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, x30]
+ ld1b { z0.b - z3.b }, pn8/z, [x0, xzr]
+ ld1b { z8.b - z11.b }, pn11/z, [x27, x1]
+
+ ld1b { z0.b, z8.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B, Z8.B }, PN8/Z, [X0, X1]
+ ld1b { z1.b, z9.b }, pn8/z, [x0, x1]
+ ld1b { z2.b, z10.b }, pn8/z, [x0, x1]
+ ld1b { z3.b, z11.b }, pn8/z, [x0, x1]
+ ld1b { z4.b, z12.b }, pn8/z, [x0, x1]
+ ld1b { z5.b, z13.b }, pn8/z, [x0, x1]
+ ld1b { z6.b, z14.b }, pn8/z, [x0, x1]
+ ld1b { z7.b, z15.b }, pn8/z, [x0, x1]
+ ld1b { z16.b, z24.b }, pn8/z, [x0, x1]
+ ld1b { z17.b, z25.b }, pn8/z, [x0, x1]
+ ld1b { z18.b, z26.b }, pn8/z, [x0, x1]
+ ld1b { z19.b, z27.b }, pn8/z, [x0, x1]
+ ld1b { z20.b, z28.b }, pn8/z, [x0, x1]
+ ld1b { z21.b, z29.b }, pn8/z, [x0, x1]
+ ld1b { z22.b, z30.b }, pn8/z, [x0, x1]
+ ld1b { z23.b, z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z8.b }, pn15/z, [x0, x1]
+ ld1b { z0.b, z8.b }, pn8/z, [x30, x1]
+ ld1b { z0.b, z8.b }, pn8/z, [sp, x1]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, x30]
+ ld1b { z0.b, z8.b }, pn8/z, [x0, xzr]
+ ld1b { z5.b, z13.b }, pn14/z, [x15, x24]
+
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #0]
+ LD1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0, X1]
+ ld1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0, x1]
+ ld1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0, x1]
+ ld1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0, x1]
+ ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0, x1]
+ ld1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0, x1]
+ ld1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0, x1]
+ ld1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp, x1]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x30]
+ ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, xzr]
+ ld1b { z17.b, z21.b, z25.b, z29.b }, pn11/z, [x4, x6]
+
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0]
+ ldnt1b { z30.b - z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn15/z, [x0]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x30]
+ ldnt1b { z0.b - z1.b }, pn8/z, [sp]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
+ ldnt1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0]
+ ldnt1b { z28.b - z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn15/z, [x0]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x30]
+ ldnt1b { z0.b - z3.b }, pn8/z, [sp]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
+ ldnt1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B, Z8.B }, PN8/Z, [X0]
+ ldnt1b { z1.b, z9.b }, pn8/z, [x0]
+ ldnt1b { z2.b, z10.b }, pn8/z, [x0]
+ ldnt1b { z3.b, z11.b }, pn8/z, [x0]
+ ldnt1b { z4.b, z12.b }, pn8/z, [x0]
+ ldnt1b { z5.b, z13.b }, pn8/z, [x0]
+ ldnt1b { z6.b, z14.b }, pn8/z, [x0]
+ ldnt1b { z7.b, z15.b }, pn8/z, [x0]
+ ldnt1b { z16.b, z24.b }, pn8/z, [x0]
+ ldnt1b { z17.b, z25.b }, pn8/z, [x0]
+ ldnt1b { z18.b, z26.b }, pn8/z, [x0]
+ ldnt1b { z19.b, z27.b }, pn8/z, [x0]
+ ldnt1b { z20.b, z28.b }, pn8/z, [x0]
+ ldnt1b { z21.b, z29.b }, pn8/z, [x0]
+ ldnt1b { z22.b, z30.b }, pn8/z, [x0]
+ ldnt1b { z23.b, z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b, z8.b }, pn15/z, [x0]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x30]
+ ldnt1b { z0.b, z8.b }, pn8/z, [sp]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, #-16, mul vl]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, #14, mul vl]
+ ldnt1b { z3.b, z11.b }, pn10/z, [x22, #6, mul vl]
+
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #0, mul vl]
+ LDNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0]
+ ldnt1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0]
+ ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0]
+ ldnt1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0]
+ ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0]
+ ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0]
+ ldnt1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0]
+ ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32, mul vl]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #28, mul vl]
+ ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn14/z, [x29, #8, mul vl]
+
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
+ ldnt1b { z30.b - z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b - z1.b }, pn8/z, [x0, xzr]
+ ldnt1b { z14.b - z15.b }, pn9/z, [x26, x3]
+
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
+ ldnt1b { z28.b - z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b - z3.b }, pn8/z, [x0, xzr]
+ ldnt1b { z8.b - z11.b }, pn11/z, [x27, x1]
+
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B, Z8.B }, PN8/Z, [X0, X1]
+ ldnt1b { z1.b, z9.b }, pn8/z, [x0, x1]
+ ldnt1b { z2.b, z10.b }, pn8/z, [x0, x1]
+ ldnt1b { z3.b, z11.b }, pn8/z, [x0, x1]
+ ldnt1b { z4.b, z12.b }, pn8/z, [x0, x1]
+ ldnt1b { z5.b, z13.b }, pn8/z, [x0, x1]
+ ldnt1b { z6.b, z14.b }, pn8/z, [x0, x1]
+ ldnt1b { z7.b, z15.b }, pn8/z, [x0, x1]
+ ldnt1b { z16.b, z24.b }, pn8/z, [x0, x1]
+ ldnt1b { z17.b, z25.b }, pn8/z, [x0, x1]
+ ldnt1b { z18.b, z26.b }, pn8/z, [x0, x1]
+ ldnt1b { z19.b, z27.b }, pn8/z, [x0, x1]
+ ldnt1b { z20.b, z28.b }, pn8/z, [x0, x1]
+ ldnt1b { z21.b, z29.b }, pn8/z, [x0, x1]
+ ldnt1b { z22.b, z30.b }, pn8/z, [x0, x1]
+ ldnt1b { z23.b, z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b, z8.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b, z8.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b, z8.b }, pn8/z, [x0, xzr]
+ ldnt1b { z5.b, z13.b }, pn14/z, [x15, x24]
+
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #0]
+ LDNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0, X1]
+ ldnt1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0, x1]
+ ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0, x1]
+ ldnt1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0, x1]
+ ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0, x1]
+ ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0, x1]
+ ldnt1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0, x1]
+ ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0, x1]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0, x1]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30, x1]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp, x1]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x30]
+ ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, xzr]
+ ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn11/z, [x4, x6]
+
+ st1b { z0.b - z1.b }, pn8, [x0]
+ st1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B - Z1.B }, PN8, [X0]
+ st1b { z30.b - z31.b }, pn8, [x0]
+ st1b { z0.b - z1.b }, pn15, [x0]
+ st1b { z0.b - z1.b }, pn8, [x30]
+ st1b { z0.b - z1.b }, pn8, [sp]
+ st1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
+ st1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
+ st1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
+
+ st1b { z0.b - z3.b }, pn8, [x0]
+ st1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B - Z3.B }, PN8, [X0]
+ st1b { z28.b - z31.b }, pn8, [x0]
+ st1b { z0.b - z3.b }, pn15, [x0]
+ st1b { z0.b - z3.b }, pn8, [x30]
+ st1b { z0.b - z3.b }, pn8, [sp]
+ st1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
+ st1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
+ st1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
+
+ st1b { z0.b, z8.b }, pn8, [x0]
+ st1b { z0.b, z8.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B, Z8.B }, PN8, [X0]
+ st1b { z1.b, z9.b }, pn8, [x0]
+ st1b { z2.b, z10.b }, pn8, [x0]
+ st1b { z3.b, z11.b }, pn8, [x0]
+ st1b { z4.b, z12.b }, pn8, [x0]
+ st1b { z5.b, z13.b }, pn8, [x0]
+ st1b { z6.b, z14.b }, pn8, [x0]
+ st1b { z7.b, z15.b }, pn8, [x0]
+ st1b { z16.b, z24.b }, pn8, [x0]
+ st1b { z17.b, z25.b }, pn8, [x0]
+ st1b { z18.b, z26.b }, pn8, [x0]
+ st1b { z19.b, z27.b }, pn8, [x0]
+ st1b { z20.b, z28.b }, pn8, [x0]
+ st1b { z21.b, z29.b }, pn8, [x0]
+ st1b { z22.b, z30.b }, pn8, [x0]
+ st1b { z23.b, z31.b }, pn8, [x0]
+ st1b { z0.b, z8.b }, pn15, [x0]
+ st1b { z0.b, z8.b }, pn8, [x30]
+ st1b { z0.b, z8.b }, pn8, [sp]
+ st1b { z0.b, z8.b }, pn8, [x0, #-16, mul vl]
+ st1b { z0.b, z8.b }, pn8, [x0, #14, mul vl]
+ st1b { z3.b, z11.b }, pn10, [x22, #6, mul vl]
+
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #0, mul vl]
+ ST1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0]
+ st1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0]
+ st1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0]
+ st1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0]
+ st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0]
+ st1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0]
+ st1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0]
+ st1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #-32, mul vl]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #28, mul vl]
+ st1b { z2.b, z6.b, z10.b, z14.b }, pn14, [x29, #8, mul vl]
+
+ st1b { z0.b - z1.b }, pn8, [x0, x1]
+ st1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B - Z1.B }, PN8, [X0, X1]
+ st1b { z30.b - z31.b }, pn8, [x0, x1]
+ st1b { z0.b - z1.b }, pn15, [x0, x1]
+ st1b { z0.b - z1.b }, pn8, [x30, x1]
+ st1b { z0.b - z1.b }, pn8, [sp, x1]
+ st1b { z0.b - z1.b }, pn8, [x0, x30]
+ st1b { z0.b - z1.b }, pn8, [x0, xzr]
+ st1b { z14.b - z15.b }, pn9, [x26, x3]
+
+ st1b { z0.b - z3.b }, pn8, [x0, x1]
+ st1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B - Z3.B }, PN8, [X0, X1]
+ st1b { z28.b - z31.b }, pn8, [x0, x1]
+ st1b { z0.b - z3.b }, pn15, [x0, x1]
+ st1b { z0.b - z3.b }, pn8, [x30, x1]
+ st1b { z0.b - z3.b }, pn8, [sp, x1]
+ st1b { z0.b - z3.b }, pn8, [x0, x30]
+ st1b { z0.b - z3.b }, pn8, [x0, xzr]
+ st1b { z8.b - z11.b }, pn11, [x27, x1]
+
+ st1b { z0.b, z8.b }, pn8, [x0, x1]
+ st1b { z0.b, z8.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B, Z8.B }, PN8, [X0, X1]
+ st1b { z1.b, z9.b }, pn8, [x0, x1]
+ st1b { z2.b, z10.b }, pn8, [x0, x1]
+ st1b { z3.b, z11.b }, pn8, [x0, x1]
+ st1b { z4.b, z12.b }, pn8, [x0, x1]
+ st1b { z5.b, z13.b }, pn8, [x0, x1]
+ st1b { z6.b, z14.b }, pn8, [x0, x1]
+ st1b { z7.b, z15.b }, pn8, [x0, x1]
+ st1b { z16.b, z24.b }, pn8, [x0, x1]
+ st1b { z17.b, z25.b }, pn8, [x0, x1]
+ st1b { z18.b, z26.b }, pn8, [x0, x1]
+ st1b { z19.b, z27.b }, pn8, [x0, x1]
+ st1b { z20.b, z28.b }, pn8, [x0, x1]
+ st1b { z21.b, z29.b }, pn8, [x0, x1]
+ st1b { z22.b, z30.b }, pn8, [x0, x1]
+ st1b { z23.b, z31.b }, pn8, [x0, x1]
+ st1b { z0.b, z8.b }, pn15, [x0, x1]
+ st1b { z0.b, z8.b }, pn8, [x30, x1]
+ st1b { z0.b, z8.b }, pn8, [sp, x1]
+ st1b { z0.b, z8.b }, pn8, [x0, x30]
+ st1b { z0.b, z8.b }, pn8, [x0, xzr]
+ st1b { z5.b, z13.b }, pn14, [x15, x24]
+
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1, lsl #0]
+ ST1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0, X1]
+ st1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0, x1]
+ st1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0, x1]
+ st1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0, x1]
+ st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0, x1]
+ st1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0, x1]
+ st1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0, x1]
+ st1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0, x1]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0, x1]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30, x1]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp, x1]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x30]
+ st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, xzr]
+ st1b { z17.b, z21.b, z25.b, z29.b }, pn11, [x4, x6]
+
+ stnt1b { z0.b - z1.b }, pn8, [x0]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B - Z1.B }, PN8, [X0]
+ stnt1b { z30.b - z31.b }, pn8, [x0]
+ stnt1b { z0.b - z1.b }, pn15, [x0]
+ stnt1b { z0.b - z1.b }, pn8, [x30]
+ stnt1b { z0.b - z1.b }, pn8, [sp]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
+ stnt1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
+ stnt1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
+
+ stnt1b { z0.b - z3.b }, pn8, [x0]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B - Z3.B }, PN8, [X0]
+ stnt1b { z28.b - z31.b }, pn8, [x0]
+ stnt1b { z0.b - z3.b }, pn15, [x0]
+ stnt1b { z0.b - z3.b }, pn8, [x30]
+ stnt1b { z0.b - z3.b }, pn8, [sp]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
+ stnt1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
+ stnt1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
+
+ stnt1b { z0.b, z8.b }, pn8, [x0]
+ stnt1b { z0.b, z8.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B, Z8.B }, PN8, [X0]
+ stnt1b { z1.b, z9.b }, pn8, [x0]
+ stnt1b { z2.b, z10.b }, pn8, [x0]
+ stnt1b { z3.b, z11.b }, pn8, [x0]
+ stnt1b { z4.b, z12.b }, pn8, [x0]
+ stnt1b { z5.b, z13.b }, pn8, [x0]
+ stnt1b { z6.b, z14.b }, pn8, [x0]
+ stnt1b { z7.b, z15.b }, pn8, [x0]
+ stnt1b { z16.b, z24.b }, pn8, [x0]
+ stnt1b { z17.b, z25.b }, pn8, [x0]
+ stnt1b { z18.b, z26.b }, pn8, [x0]
+ stnt1b { z19.b, z27.b }, pn8, [x0]
+ stnt1b { z20.b, z28.b }, pn8, [x0]
+ stnt1b { z21.b, z29.b }, pn8, [x0]
+ stnt1b { z22.b, z30.b }, pn8, [x0]
+ stnt1b { z23.b, z31.b }, pn8, [x0]
+ stnt1b { z0.b, z8.b }, pn15, [x0]
+ stnt1b { z0.b, z8.b }, pn8, [x30]
+ stnt1b { z0.b, z8.b }, pn8, [sp]
+ stnt1b { z0.b, z8.b }, pn8, [x0, #-16, mul vl]
+ stnt1b { z0.b, z8.b }, pn8, [x0, #14, mul vl]
+ stnt1b { z3.b, z11.b }, pn10, [x22, #6, mul vl]
+
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #0, mul vl]
+ STNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0]
+ stnt1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0]
+ stnt1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0]
+ stnt1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0]
+ stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0]
+ stnt1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0]
+ stnt1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0]
+ stnt1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #-32, mul vl]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #28, mul vl]
+ stnt1b { z2.b, z6.b, z10.b, z14.b }, pn14, [x29, #8, mul vl]
+
+ stnt1b { z0.b - z1.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B - Z1.B }, PN8, [X0, X1]
+ stnt1b { z30.b - z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn15, [x0, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x30, x1]
+ stnt1b { z0.b - z1.b }, pn8, [sp, x1]
+ stnt1b { z0.b - z1.b }, pn8, [x0, x30]
+ stnt1b { z0.b - z1.b }, pn8, [x0, xzr]
+ stnt1b { z14.b - z15.b }, pn9, [x26, x3]
+
+ stnt1b { z0.b - z3.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B - Z3.B }, PN8, [X0, X1]
+ stnt1b { z28.b - z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn15, [x0, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x30, x1]
+ stnt1b { z0.b - z3.b }, pn8, [sp, x1]
+ stnt1b { z0.b - z3.b }, pn8, [x0, x30]
+ stnt1b { z0.b - z3.b }, pn8, [x0, xzr]
+ stnt1b { z8.b - z11.b }, pn11, [x27, x1]
+
+ stnt1b { z0.b, z8.b }, pn8, [x0, x1]
+ stnt1b { z0.b, z8.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B, Z8.B }, PN8, [X0, X1]
+ stnt1b { z1.b, z9.b }, pn8, [x0, x1]
+ stnt1b { z2.b, z10.b }, pn8, [x0, x1]
+ stnt1b { z3.b, z11.b }, pn8, [x0, x1]
+ stnt1b { z4.b, z12.b }, pn8, [x0, x1]
+ stnt1b { z5.b, z13.b }, pn8, [x0, x1]
+ stnt1b { z6.b, z14.b }, pn8, [x0, x1]
+ stnt1b { z7.b, z15.b }, pn8, [x0, x1]
+ stnt1b { z16.b, z24.b }, pn8, [x0, x1]
+ stnt1b { z17.b, z25.b }, pn8, [x0, x1]
+ stnt1b { z18.b, z26.b }, pn8, [x0, x1]
+ stnt1b { z19.b, z27.b }, pn8, [x0, x1]
+ stnt1b { z20.b, z28.b }, pn8, [x0, x1]
+ stnt1b { z21.b, z29.b }, pn8, [x0, x1]
+ stnt1b { z22.b, z30.b }, pn8, [x0, x1]
+ stnt1b { z23.b, z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b, z8.b }, pn15, [x0, x1]
+ stnt1b { z0.b, z8.b }, pn8, [x30, x1]
+ stnt1b { z0.b, z8.b }, pn8, [sp, x1]
+ stnt1b { z0.b, z8.b }, pn8, [x0, x30]
+ stnt1b { z0.b, z8.b }, pn8, [x0, xzr]
+ stnt1b { z5.b, z13.b }, pn14, [x15, x24]
+
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1, lsl #0]
+ STNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0, X1]
+ stnt1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0, x1]
+ stnt1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0, x1]
+ stnt1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0, x1]
+ stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0, x1]
+ stnt1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0, x1]
+ stnt1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0, x1]
+ stnt1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0, x1]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0, x1]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30, x1]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp, x1]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x30]
+ stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, xzr]
+ stnt1b { z17.b, z21.b, z25.b, z29.b }, pn11, [x4, x6]
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-3-invalid.s
+#error_output: sme2-3-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1d 0,pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1d {z0\.d-z1\.d},0,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,0'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1d {z0\.d-z2\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z1\.d-z2\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d-z1\.d},p8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8/m,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8\.d,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z1\.d},pn0/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z1\.d},pn7/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[w0,w1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[xzr,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[sp,sp,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,w1,sxtw#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,w1,uxtw#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z1\.d-z4\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z2\.d-z5\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z3\.d-z6\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d-z3\.d},p8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8/m,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8\.d,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z3\.d},pn0/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z3\.d},pn7/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[w0,w1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[xzr,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[sp,sp,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,w1,sxtw#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,w1,uxtw#3\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z2\.d},pn8/z,\[x0,x1,lsl#3\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z3\.d},pn8/z,\[x0,x1,lsl#3\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z4\.d},pn8/z,\[x0,x1,lsl#3\]`
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z8\.d,z16\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z24\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z8\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]`
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d,z8\.d},p8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[w0,w30,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[xzr,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[x0,sp,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z4\.d,z8\.d,z12\.d,z16\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z20\.d,z24\.d,z28\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},p8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[w0,w30,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[xzr,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,sp,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#1\]'
--- /dev/null
+ ld1d 0, pn8/z, [x0]
+ ld1d { z0.d - z1.d }, 0, [x0]
+ ld1d { z0.d - z1.d }, pn8/z, 0
+
+ ld1d { z0.d - z2.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z1.d - z2.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, p8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/m, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8.d, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn0/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn7/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [w0, w1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [xzr, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [sp, sp, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #1]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #2]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #4]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, w1, sxtw #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, w1, uxtw #3]
+
+ ld1d { z1.d - z4.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z2.d - z5.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z3.d - z6.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, p8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/m, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8.d, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn0/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn7/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [w0, w1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [xzr, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [sp, sp, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #1]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #2]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #4]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, w1, sxtw #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, w1, uxtw #3]
+
+ ld1d { z0.d, z2.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z3.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z4.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z8.d, z16.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z24.d, z0.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z8.d, z0.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.h, z8.h }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z8.d }, p8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [w0, w30, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [xzr, xzr, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, sp, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #1]
+
+ ld1d { z4.d, z8.d, z12.d, z16.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z20.d, z24.d, z28.d, z0.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, p8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [w0, w30, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [xzr, xzr, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, sp, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #1]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-3.s
+#error_output: sme2-3-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z1\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z30\.d-z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z12\.d-z13\.d},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z3\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z28\.d-z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z8\.d-z11\.d},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z8\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z9\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z10\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z4\.d,z12\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z6\.d,z14\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z7\.d,z15\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z24\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z25\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z26\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z27\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z20\.d,z28\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z21\.d,z29\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z22\.d,z30\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z23\.d,z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z1\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z30\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z14\.d-z15\.d},pn9/z,\[x26,x3,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z3\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z28\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z8\.d-z11\.d},pn11/z,\[x27,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z8\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z9\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z10\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z4\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z6\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z7\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z24\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z25\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z26\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z27\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z20\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z21\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z22\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z23\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn14/z,\[x15,x24,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11/z,\[x4,x6,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z1\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z30\.d-z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z12\.d-z13\.d},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z3\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z28\.d-z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z8\.d-z11\.d},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z8\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z9\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z10\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z4\.d,z12\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z6\.d,z14\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z7\.d,z15\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z24\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z25\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z26\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z27\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z20\.d,z28\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z21\.d,z29\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z22\.d,z30\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z23\.d,z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z1\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z30\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z14\.d-z15\.d},pn9/z,\[x26,x3,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z3\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z28\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z8\.d-z11\.d},pn11/z,\[x27,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z8\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z9\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z10\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z4\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z6\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z7\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z24\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z25\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z26\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z27\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z20\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z21\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z22\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z23\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn14/z,\[x15,x24,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11/z,\[x4,x6,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z1\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z30\.d-z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z12\.d-z13\.d},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z3\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z28\.d-z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z8\.d-z11\.d},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z8\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z9\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z10\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z4\.d,z12\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z6\.d,z14\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z7\.d,z15\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z24\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z25\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z26\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z27\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z20\.d,z28\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z21\.d,z29\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z22\.d,z30\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z23\.d,z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z1\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z30\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z14\.d-z15\.d},pn9,\[x26,x3,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z3\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z28\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z8\.d-z11\.d},pn11,\[x27,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z8\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z9\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z10\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z4\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z6\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z7\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z24\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z25\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z26\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z27\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z20\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z21\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z22\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z23\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn14,\[x15,x24,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11,\[x4,x6,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z1\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z30\.d-z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z12\.d-z13\.d},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z3\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z28\.d-z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z8\.d-z11\.d},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z8\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z9\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z10\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z4\.d,z12\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z6\.d,z14\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z7\.d,z15\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z24\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z25\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z26\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z27\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z20\.d,z28\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z21\.d,z29\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z22\.d,z30\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z23\.d,z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z1\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z30\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z14\.d-z15\.d},pn9,\[x26,x3,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z3\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z28\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z8\.d-z11\.d},pn11,\[x27,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z8\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z9\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z10\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z4\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z6\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z7\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z24\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z25\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z26\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z27\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z20\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z21\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z22\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z23\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn14,\[x15,x24,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl 3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0,X1,LSL#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x30,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,xzr,lsl#3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11,\[x4,x6,lsl#3\]'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a040601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a0407c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0\]
+[^:]+: a04063c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30\]
+[^:]+: a04063e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp\]
+[^:]+: a0486000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0476000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b756c ld1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a040fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0\]
+[^:]+: a040e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30\]
+[^:]+: a040e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp\]
+[^:]+: a048e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ee28 ld1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406001 ld1d {z1\.d, z9\.d}, pn8/z, \[x0\]
+[^:]+: a1406002 ld1d {z2\.d, z10\.d}, pn8/z, \[x0\]
+[^:]+: a1406003 ld1d {z3\.d, z11\.d}, pn8/z, \[x0\]
+[^:]+: a1406004 ld1d {z4\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a1406005 ld1d {z5\.d, z13\.d}, pn8/z, \[x0\]
+[^:]+: a1406006 ld1d {z6\.d, z14\.d}, pn8/z, \[x0\]
+[^:]+: a1406007 ld1d {z7\.d, z15\.d}, pn8/z, \[x0\]
+[^:]+: a1406010 ld1d {z16\.d, z24\.d}, pn8/z, \[x0\]
+[^:]+: a1406011 ld1d {z17\.d, z25\.d}, pn8/z, \[x0\]
+[^:]+: a1406012 ld1d {z18\.d, z26\.d}, pn8/z, \[x0\]
+[^:]+: a1406013 ld1d {z19\.d, z27\.d}, pn8/z, \[x0\]
+[^:]+: a1406014 ld1d {z20\.d, z28\.d}, pn8/z, \[x0\]
+[^:]+: a1406015 ld1d {z21\.d, z29\.d}, pn8/z, \[x0\]
+[^:]+: a1406016 ld1d {z22\.d, z30\.d}, pn8/z, \[x0\]
+[^:]+: a1406017 ld1d {z23\.d, z31\.d}, pn8/z, \[x0\]
+[^:]+: a1407c00 ld1d {z0\.d, z8\.d}, pn15/z, \[x0\]
+[^:]+: a14063c0 ld1d {z0\.d, z8\.d}, pn8/z, \[x30\]
+[^:]+: a14063e0 ld1d {z0\.d, z8\.d}, pn8/z, \[sp\]
+[^:]+: a1486000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1476000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1436ac3 ld1d {z3\.d, z11\.d}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e001 ld1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0\]
+[^:]+: a140e002 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0\]
+[^:]+: a140e003 ld1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0\]
+[^:]+: a140e010 ld1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0\]
+[^:]+: a140e011 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0\]
+[^:]+: a140e012 ld1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0\]
+[^:]+: a140e013 ld1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0\]
+[^:]+: a140fc00 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0\]
+[^:]+: a140e3c0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30\]
+[^:]+: a140e3e0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp\]
+[^:]+: a148e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a147e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a142fba2 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14/z, \[x29, #8, mul vl\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a0017c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a00163c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a00163e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01e6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01f6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a003674e ld1d {z14\.d-z15\.d}, pn9/z, \[x26, x3, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a001fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a001e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a001e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a01ee000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a01fe000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a001ef68 ld1d {z8\.d-z11\.d}, pn11/z, \[x27, x1, lsl #3\]
+[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016001 ld1d {z1\.d, z9\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016002 ld1d {z2\.d, z10\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016003 ld1d {z3\.d, z11\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016004 ld1d {z4\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016005 ld1d {z5\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016006 ld1d {z6\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016007 ld1d {z7\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016010 ld1d {z16\.d, z24\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016011 ld1d {z17\.d, z25\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016012 ld1d {z18\.d, z26\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016013 ld1d {z19\.d, z27\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016014 ld1d {z20\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016015 ld1d {z21\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016016 ld1d {z22\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1016017 ld1d {z23\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a1017c00 ld1d {z0\.d, z8\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a10163c0 ld1d {z0\.d, z8\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a10163e0 ld1d {z0\.d, z8\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a11e6000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a11f6000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a11879e5 ld1d {z5\.d, z13\.d}, pn14/z, \[x15, x24, lsl #3\]
+[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e001 ld1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e002 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e003 ld1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e010 ld1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e011 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e012 ld1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101e013 ld1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101fc00 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0, x1, lsl #3\]
+[^:]+: a101e3c0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30, x1, lsl #3\]
+[^:]+: a101e3e0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp, x1, lsl #3\]
+[^:]+: a11ee000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x30, lsl #3\]
+[^:]+: a11fe000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, xzr, lsl #3\]
+[^:]+: a106ec91 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11/z, \[x4, x6, lsl #3\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
+[^:]+: a040601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a0407c01 ldnt1d {z0\.d-z1\.d}, pn15/z, \[x0\]
+[^:]+: a04063c1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x30\]
+[^:]+: a04063e1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[sp\]
+[^:]+: a0486001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0476001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b756d ldnt1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
+[^:]+: a040e01d ldnt1d {z28\.d-z31\.d}, pn8/z, \[x0\]
+[^:]+: a040fc01 ldnt1d {z0\.d-z3\.d}, pn15/z, \[x0\]
+[^:]+: a040e3c1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x30\]
+[^:]+: a040e3e1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[sp\]
+[^:]+: a048e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ee29 ldnt1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
+[^:]+: a1406009 ldnt1d {z1\.d, z9\.d}, pn8/z, \[x0\]
+[^:]+: a140600a ldnt1d {z2\.d, z10\.d}, pn8/z, \[x0\]
+[^:]+: a140600b ldnt1d {z3\.d, z11\.d}, pn8/z, \[x0\]
+[^:]+: a140600c ldnt1d {z4\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140600d ldnt1d {z5\.d, z13\.d}, pn8/z, \[x0\]
+[^:]+: a140600e ldnt1d {z6\.d, z14\.d}, pn8/z, \[x0\]
+[^:]+: a140600f ldnt1d {z7\.d, z15\.d}, pn8/z, \[x0\]
+[^:]+: a1406018 ldnt1d {z16\.d, z24\.d}, pn8/z, \[x0\]
+[^:]+: a1406019 ldnt1d {z17\.d, z25\.d}, pn8/z, \[x0\]
+[^:]+: a140601a ldnt1d {z18\.d, z26\.d}, pn8/z, \[x0\]
+[^:]+: a140601b ldnt1d {z19\.d, z27\.d}, pn8/z, \[x0\]
+[^:]+: a140601c ldnt1d {z20\.d, z28\.d}, pn8/z, \[x0\]
+[^:]+: a140601d ldnt1d {z21\.d, z29\.d}, pn8/z, \[x0\]
+[^:]+: a140601e ldnt1d {z22\.d, z30\.d}, pn8/z, \[x0\]
+[^:]+: a140601f ldnt1d {z23\.d, z31\.d}, pn8/z, \[x0\]
+[^:]+: a1407c08 ldnt1d {z0\.d, z8\.d}, pn15/z, \[x0\]
+[^:]+: a14063c8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x30\]
+[^:]+: a14063e8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[sp\]
+[^:]+: a1486008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1476008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1436acb ldnt1d {z3\.d, z11\.d}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
+[^:]+: a140e009 ldnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0\]
+[^:]+: a140e00a ldnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0\]
+[^:]+: a140e00b ldnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0\]
+[^:]+: a140e018 ldnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0\]
+[^:]+: a140e019 ldnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0\]
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+[^:]+: a001601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
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+[^:]+: a101e01b ldnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
+[^:]+: a101fc08 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0, x1, lsl #3\]
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+[^:]+: a101e3e8 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp, x1, lsl #3\]
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+[^:]+: a13fe000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a126ec91 st1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11, \[x4, x6, lsl #3\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
+[^:]+: a060601f stnt1d {z30\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a0607c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0\]
+[^:]+: a06063c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30\]
+[^:]+: a06063e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp\]
+[^:]+: a0686001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0676001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b756d stnt1d {z12\.d-z13\.d}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
+[^:]+: a060e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0\]
+[^:]+: a060fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0\]
+[^:]+: a060e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30\]
+[^:]+: a060e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp\]
+[^:]+: a068e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ee29 stnt1d {z8\.d-z11\.d}, pn11, \[x17, #20, mul vl\]
+[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
+[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
+[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
+[^:]+: a1606009 stnt1d {z1\.d, z9\.d}, pn8, \[x0\]
+[^:]+: a160600a stnt1d {z2\.d, z10\.d}, pn8, \[x0\]
+[^:]+: a160600b stnt1d {z3\.d, z11\.d}, pn8, \[x0\]
+[^:]+: a160600c stnt1d {z4\.d, z12\.d}, pn8, \[x0\]
+[^:]+: a160600d stnt1d {z5\.d, z13\.d}, pn8, \[x0\]
+[^:]+: a160600e stnt1d {z6\.d, z14\.d}, pn8, \[x0\]
+[^:]+: a160600f stnt1d {z7\.d, z15\.d}, pn8, \[x0\]
+[^:]+: a1606018 stnt1d {z16\.d, z24\.d}, pn8, \[x0\]
+[^:]+: a1606019 stnt1d {z17\.d, z25\.d}, pn8, \[x0\]
+[^:]+: a160601a stnt1d {z18\.d, z26\.d}, pn8, \[x0\]
+[^:]+: a160601b stnt1d {z19\.d, z27\.d}, pn8, \[x0\]
+[^:]+: a160601c stnt1d {z20\.d, z28\.d}, pn8, \[x0\]
+[^:]+: a160601d stnt1d {z21\.d, z29\.d}, pn8, \[x0\]
+[^:]+: a160601e stnt1d {z22\.d, z30\.d}, pn8, \[x0\]
+[^:]+: a160601f stnt1d {z23\.d, z31\.d}, pn8, \[x0\]
+[^:]+: a1607c08 stnt1d {z0\.d, z8\.d}, pn15, \[x0\]
+[^:]+: a16063c8 stnt1d {z0\.d, z8\.d}, pn8, \[x30\]
+[^:]+: a16063e8 stnt1d {z0\.d, z8\.d}, pn8, \[sp\]
+[^:]+: a1686008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a1676008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, #14, mul vl\]
+[^:]+: a1636acb stnt1d {z3\.d, z11\.d}, pn10, \[x22, #6, mul vl\]
+[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
+[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
+[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
+[^:]+: a160e009 stnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0\]
+[^:]+: a160e00a stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0\]
+[^:]+: a160e00b stnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0\]
+[^:]+: a160e018 stnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0\]
+[^:]+: a160e019 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0\]
+[^:]+: a160e01a stnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0\]
+[^:]+: a160e01b stnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0\]
+[^:]+: a160fc08 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0\]
+[^:]+: a160e3c8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30\]
+[^:]+: a160e3e8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp\]
+[^:]+: a168e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a167e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #28, mul vl\]
+[^:]+: a162fbaa stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14, \[x29, #8, mul vl\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021601f stnt1d {z30\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a0217c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a02163c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a02163e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03e6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03f6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a023674f stnt1d {z14\.d-z15\.d}, pn9, \[x26, x3, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a021fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a021e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a021e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a03ee001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a03fe001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a021ef69 stnt1d {z8\.d-z11\.d}, pn11, \[x27, x1, lsl #3\]
+[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1216009 stnt1d {z1\.d, z9\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600a stnt1d {z2\.d, z10\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600b stnt1d {z3\.d, z11\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600c stnt1d {z4\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600d stnt1d {z5\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600e stnt1d {z6\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121600f stnt1d {z7\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1216018 stnt1d {z16\.d, z24\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1216019 stnt1d {z17\.d, z25\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601a stnt1d {z18\.d, z26\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601b stnt1d {z19\.d, z27\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601c stnt1d {z20\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601d stnt1d {z21\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601e stnt1d {z22\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121601f stnt1d {z23\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a1217c08 stnt1d {z0\.d, z8\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a12163c8 stnt1d {z0\.d, z8\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a12163e8 stnt1d {z0\.d, z8\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a13e6008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a13f6008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a13879ed stnt1d {z5\.d, z13\.d}, pn14, \[x15, x24, lsl #3\]
+[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e009 stnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e00a stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e00b stnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e018 stnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e019 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e01a stnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121e01b stnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
+[^:]+: a121fc08 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0, x1, lsl #3\]
+[^:]+: a121e3c8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30, x1, lsl #3\]
+[^:]+: a121e3e8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp, x1, lsl #3\]
+[^:]+: a13ee008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x30, lsl #3\]
+[^:]+: a13fe008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, xzr, lsl #3\]
+[^:]+: a126ec99 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11, \[x4, x6, lsl #3\]
--- /dev/null
+ ld1d { z0.d - z1.d }, pn8/z, [x0]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D - Z1.D }, PN8/Z, [X0]
+ ld1d { z30.d - z31.d }, pn8/z, [x0]
+ ld1d { z0.d - z1.d }, pn15/z, [x0]
+ ld1d { z0.d - z1.d }, pn8/z, [x30]
+ ld1d { z0.d - z1.d }, pn8/z, [sp]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
+ ld1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
+
+ ld1d { z0.d - z3.d }, pn8/z, [x0]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D - Z3.D }, PN8/Z, [X0]
+ ld1d { z28.d - z31.d }, pn8/z, [x0]
+ ld1d { z0.d - z3.d }, pn15/z, [x0]
+ ld1d { z0.d - z3.d }, pn8/z, [x30]
+ ld1d { z0.d - z3.d }, pn8/z, [sp]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
+ ld1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
+
+ ld1d { z0.d, z8.d }, pn8/z, [x0]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D, Z8.D }, PN8/Z, [X0]
+ ld1d { z1.d, z9.d }, pn8/z, [x0]
+ ld1d { z2.d, z10.d }, pn8/z, [x0]
+ ld1d { z3.d, z11.d }, pn8/z, [x0]
+ ld1d { z4.d, z12.d }, pn8/z, [x0]
+ ld1d { z5.d, z13.d }, pn8/z, [x0]
+ ld1d { z6.d, z14.d }, pn8/z, [x0]
+ ld1d { z7.d, z15.d }, pn8/z, [x0]
+ ld1d { z16.d, z24.d }, pn8/z, [x0]
+ ld1d { z17.d, z25.d }, pn8/z, [x0]
+ ld1d { z18.d, z26.d }, pn8/z, [x0]
+ ld1d { z19.d, z27.d }, pn8/z, [x0]
+ ld1d { z20.d, z28.d }, pn8/z, [x0]
+ ld1d { z21.d, z29.d }, pn8/z, [x0]
+ ld1d { z22.d, z30.d }, pn8/z, [x0]
+ ld1d { z23.d, z31.d }, pn8/z, [x0]
+ ld1d { z0.d, z8.d }, pn15/z, [x0]
+ ld1d { z0.d, z8.d }, pn8/z, [x30]
+ ld1d { z0.d, z8.d }, pn8/z, [sp]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, #-16, mul vl]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, #14, mul vl]
+ ld1d { z3.d, z11.d }, pn10/z, [x22, #6, mul vl]
+
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #0, mul vl]
+ LD1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0]
+ ld1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0]
+ ld1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0]
+ ld1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0]
+ ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0]
+ ld1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0]
+ ld1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0]
+ ld1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #-32, mul vl]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #28, mul vl]
+ ld1d { z2.d, z6.d, z10.d, z14.d }, pn14/z, [x29, #8, mul vl]
+
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
+
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
+
+ ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D, Z8.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z1.d, z9.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z2.d, z10.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z3.d, z11.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z4.d, z12.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z5.d, z13.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z6.d, z14.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z7.d, z15.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z16.d, z24.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z17.d, z25.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z18.d, z26.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z19.d, z27.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z20.d, z28.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z21.d, z29.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z22.d, z30.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z23.d, z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z8.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d, z8.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z5.d, z13.d }, pn14/z, [x15, x24, lsl #3]
+
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl 3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #3]
+ LD1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0, X1, LSL #3]
+ ld1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp, x1, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x30, lsl #3]
+ ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, xzr, lsl #3]
+ ld1d { z17.d, z21.d, z25.d, z29.d }, pn11/z, [x4, x6, lsl #3]
+
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0]
+ ldnt1d { z30.d - z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn15/z, [x0]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x30]
+ ldnt1d { z0.d - z1.d }, pn8/z, [sp]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
+ ldnt1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0]
+ ldnt1d { z28.d - z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn15/z, [x0]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x30]
+ ldnt1d { z0.d - z3.d }, pn8/z, [sp]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
+ ldnt1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D, Z8.D }, PN8/Z, [X0]
+ ldnt1d { z1.d, z9.d }, pn8/z, [x0]
+ ldnt1d { z2.d, z10.d }, pn8/z, [x0]
+ ldnt1d { z3.d, z11.d }, pn8/z, [x0]
+ ldnt1d { z4.d, z12.d }, pn8/z, [x0]
+ ldnt1d { z5.d, z13.d }, pn8/z, [x0]
+ ldnt1d { z6.d, z14.d }, pn8/z, [x0]
+ ldnt1d { z7.d, z15.d }, pn8/z, [x0]
+ ldnt1d { z16.d, z24.d }, pn8/z, [x0]
+ ldnt1d { z17.d, z25.d }, pn8/z, [x0]
+ ldnt1d { z18.d, z26.d }, pn8/z, [x0]
+ ldnt1d { z19.d, z27.d }, pn8/z, [x0]
+ ldnt1d { z20.d, z28.d }, pn8/z, [x0]
+ ldnt1d { z21.d, z29.d }, pn8/z, [x0]
+ ldnt1d { z22.d, z30.d }, pn8/z, [x0]
+ ldnt1d { z23.d, z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d, z8.d }, pn15/z, [x0]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x30]
+ ldnt1d { z0.d, z8.d }, pn8/z, [sp]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, #-16, mul vl]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, #14, mul vl]
+ ldnt1d { z3.d, z11.d }, pn10/z, [x22, #6, mul vl]
+
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #0, mul vl]
+ LDNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0]
+ ldnt1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0]
+ ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0]
+ ldnt1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0]
+ ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0]
+ ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0]
+ ldnt1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0]
+ ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #-32, mul vl]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #28, mul vl]
+ ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn14/z, [x29, #8, mul vl]
+
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
+
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
+
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D, Z8.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z1.d, z9.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z2.d, z10.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z3.d, z11.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z4.d, z12.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z5.d, z13.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z6.d, z14.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z7.d, z15.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z16.d, z24.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z17.d, z25.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z18.d, z26.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z19.d, z27.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z20.d, z28.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z21.d, z29.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z22.d, z30.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z23.d, z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d, z8.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d, z8.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d, z8.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z5.d, z13.d }, pn14/z, [x15, x24, lsl #3]
+
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl 3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #3]
+ LDNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0, X1, LSL #3]
+ ldnt1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0, x1, lsl #3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30, x1, lsl #3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp, x1, lsl #3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x30, lsl #3]
+ ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, xzr, lsl #3]
+ ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn11/z, [x4, x6, lsl #3]
+
+ st1d { z0.d - z1.d }, pn8, [x0]
+ st1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D - Z1.D }, PN8, [X0]
+ st1d { z30.d - z31.d }, pn8, [x0]
+ st1d { z0.d - z1.d }, pn15, [x0]
+ st1d { z0.d - z1.d }, pn8, [x30]
+ st1d { z0.d - z1.d }, pn8, [sp]
+ st1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
+ st1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
+ st1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
+
+ st1d { z0.d - z3.d }, pn8, [x0]
+ st1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D - Z3.D }, PN8, [X0]
+ st1d { z28.d - z31.d }, pn8, [x0]
+ st1d { z0.d - z3.d }, pn15, [x0]
+ st1d { z0.d - z3.d }, pn8, [x30]
+ st1d { z0.d - z3.d }, pn8, [sp]
+ st1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
+ st1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
+ st1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
+
+ st1d { z0.d, z8.d }, pn8, [x0]
+ st1d { z0.d, z8.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D, Z8.D }, PN8, [X0]
+ st1d { z1.d, z9.d }, pn8, [x0]
+ st1d { z2.d, z10.d }, pn8, [x0]
+ st1d { z3.d, z11.d }, pn8, [x0]
+ st1d { z4.d, z12.d }, pn8, [x0]
+ st1d { z5.d, z13.d }, pn8, [x0]
+ st1d { z6.d, z14.d }, pn8, [x0]
+ st1d { z7.d, z15.d }, pn8, [x0]
+ st1d { z16.d, z24.d }, pn8, [x0]
+ st1d { z17.d, z25.d }, pn8, [x0]
+ st1d { z18.d, z26.d }, pn8, [x0]
+ st1d { z19.d, z27.d }, pn8, [x0]
+ st1d { z20.d, z28.d }, pn8, [x0]
+ st1d { z21.d, z29.d }, pn8, [x0]
+ st1d { z22.d, z30.d }, pn8, [x0]
+ st1d { z23.d, z31.d }, pn8, [x0]
+ st1d { z0.d, z8.d }, pn15, [x0]
+ st1d { z0.d, z8.d }, pn8, [x30]
+ st1d { z0.d, z8.d }, pn8, [sp]
+ st1d { z0.d, z8.d }, pn8, [x0, #-16, mul vl]
+ st1d { z0.d, z8.d }, pn8, [x0, #14, mul vl]
+ st1d { z3.d, z11.d }, pn10, [x22, #6, mul vl]
+
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #0, mul vl]
+ ST1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0]
+ st1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0]
+ st1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0]
+ st1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0]
+ st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0]
+ st1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0]
+ st1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0]
+ st1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #-32, mul vl]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #28, mul vl]
+ st1d { z2.d, z6.d, z10.d, z14.d }, pn14, [x29, #8, mul vl]
+
+ st1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
+ st1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
+
+ st1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
+ st1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
+
+ st1d { z0.d, z8.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d, z8.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D, Z8.D }, PN8, [X0, X1, LSL #3]
+ st1d { z1.d, z9.d }, pn8, [x0, x1, lsl #3]
+ st1d { z2.d, z10.d }, pn8, [x0, x1, lsl #3]
+ st1d { z3.d, z11.d }, pn8, [x0, x1, lsl #3]
+ st1d { z4.d, z12.d }, pn8, [x0, x1, lsl #3]
+ st1d { z5.d, z13.d }, pn8, [x0, x1, lsl #3]
+ st1d { z6.d, z14.d }, pn8, [x0, x1, lsl #3]
+ st1d { z7.d, z15.d }, pn8, [x0, x1, lsl #3]
+ st1d { z16.d, z24.d }, pn8, [x0, x1, lsl #3]
+ st1d { z17.d, z25.d }, pn8, [x0, x1, lsl #3]
+ st1d { z18.d, z26.d }, pn8, [x0, x1, lsl #3]
+ st1d { z19.d, z27.d }, pn8, [x0, x1, lsl #3]
+ st1d { z20.d, z28.d }, pn8, [x0, x1, lsl #3]
+ st1d { z21.d, z29.d }, pn8, [x0, x1, lsl #3]
+ st1d { z22.d, z30.d }, pn8, [x0, x1, lsl #3]
+ st1d { z23.d, z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d, z8.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d, z8.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d, z8.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d, z8.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d, z8.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z5.d, z13.d }, pn14, [x15, x24, lsl #3]
+
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl 3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl #3]
+ ST1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0, X1, LSL #3]
+ st1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0, x1, lsl #3]
+ st1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0, x1, lsl #3]
+ st1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0, x1, lsl #3]
+ st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0, x1, lsl #3]
+ st1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0, x1, lsl #3]
+ st1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0, x1, lsl #3]
+ st1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0, x1, lsl #3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0, x1, lsl #3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30, x1, lsl #3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp, x1, lsl #3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x30, lsl #3]
+ st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, xzr, lsl #3]
+ st1d { z17.d, z21.d, z25.d, z29.d }, pn11, [x4, x6, lsl #3]
+
+ stnt1d { z0.d - z1.d }, pn8, [x0]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D - Z1.D }, PN8, [X0]
+ stnt1d { z30.d - z31.d }, pn8, [x0]
+ stnt1d { z0.d - z1.d }, pn15, [x0]
+ stnt1d { z0.d - z1.d }, pn8, [x30]
+ stnt1d { z0.d - z1.d }, pn8, [sp]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
+ stnt1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
+ stnt1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
+
+ stnt1d { z0.d - z3.d }, pn8, [x0]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D - Z3.D }, PN8, [X0]
+ stnt1d { z28.d - z31.d }, pn8, [x0]
+ stnt1d { z0.d - z3.d }, pn15, [x0]
+ stnt1d { z0.d - z3.d }, pn8, [x30]
+ stnt1d { z0.d - z3.d }, pn8, [sp]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
+ stnt1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
+ stnt1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
+
+ stnt1d { z0.d, z8.d }, pn8, [x0]
+ stnt1d { z0.d, z8.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D, Z8.D }, PN8, [X0]
+ stnt1d { z1.d, z9.d }, pn8, [x0]
+ stnt1d { z2.d, z10.d }, pn8, [x0]
+ stnt1d { z3.d, z11.d }, pn8, [x0]
+ stnt1d { z4.d, z12.d }, pn8, [x0]
+ stnt1d { z5.d, z13.d }, pn8, [x0]
+ stnt1d { z6.d, z14.d }, pn8, [x0]
+ stnt1d { z7.d, z15.d }, pn8, [x0]
+ stnt1d { z16.d, z24.d }, pn8, [x0]
+ stnt1d { z17.d, z25.d }, pn8, [x0]
+ stnt1d { z18.d, z26.d }, pn8, [x0]
+ stnt1d { z19.d, z27.d }, pn8, [x0]
+ stnt1d { z20.d, z28.d }, pn8, [x0]
+ stnt1d { z21.d, z29.d }, pn8, [x0]
+ stnt1d { z22.d, z30.d }, pn8, [x0]
+ stnt1d { z23.d, z31.d }, pn8, [x0]
+ stnt1d { z0.d, z8.d }, pn15, [x0]
+ stnt1d { z0.d, z8.d }, pn8, [x30]
+ stnt1d { z0.d, z8.d }, pn8, [sp]
+ stnt1d { z0.d, z8.d }, pn8, [x0, #-16, mul vl]
+ stnt1d { z0.d, z8.d }, pn8, [x0, #14, mul vl]
+ stnt1d { z3.d, z11.d }, pn10, [x22, #6, mul vl]
+
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #0, mul vl]
+ STNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0]
+ stnt1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0]
+ stnt1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0]
+ stnt1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0]
+ stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0]
+ stnt1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0]
+ stnt1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0]
+ stnt1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #-32, mul vl]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #28, mul vl]
+ stnt1d { z2.d, z6.d, z10.d, z14.d }, pn14, [x29, #8, mul vl]
+
+ stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
+
+ stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
+
+ stnt1d { z0.d, z8.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d, z8.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D, Z8.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z1.d, z9.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z2.d, z10.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z3.d, z11.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z4.d, z12.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z5.d, z13.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z6.d, z14.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z7.d, z15.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z16.d, z24.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z17.d, z25.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z18.d, z26.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z19.d, z27.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z20.d, z28.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z21.d, z29.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z22.d, z30.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z23.d, z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d, z8.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d, z8.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d, z8.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d, z8.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d, z8.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z5.d, z13.d }, pn14, [x15, x24, lsl #3]
+
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl 3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl #3]
+ STNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0, X1, LSL #3]
+ stnt1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0, x1, lsl #3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0, x1, lsl #3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30, x1, lsl #3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp, x1, lsl #3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x30, lsl #3]
+ stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, xzr, lsl #3]
+ stnt1d { z17.d, z21.d, z25.d, z29.d }, pn11, [x4, x6, lsl #3]
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-4-invalid.s
+#error_output: sme2-4-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1h 0,pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1h {z0\.h-z1\.h},0,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,0'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1h {z0\.h-z2\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z1\.h-z2\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h-z1\.h},p8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8/m,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8\.h,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z1\.h},pn0/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z1\.h},pn7/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[w0,w1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[xzr,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[sp,sp,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,w1,sxtw#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,w1,uxtw#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z1\.h-z4\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z2\.h-z5\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z3\.h-z6\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h-z3\.h},p8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8/m,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8\.h,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z3\.h},pn0/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z3\.h},pn7/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[w0,w1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[xzr,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[sp,sp,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,w1,sxtw#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,w1,uxtw#1\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z2\.h},pn8/z,\[x0,x1,lsl#1\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z3\.h},pn8/z,\[x0,x1,lsl#1\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z4\.h},pn8/z,\[x0,x1,lsl#1\]`
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z8\.h,z16\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z24\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z8\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]`
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h,z8\.h},p8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[w0,w30,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[xzr,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[x0,sp,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z4\.h,z8\.h,z12\.h,z16\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z20\.h,z24\.h,z28\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},p8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[w0,w30,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[xzr,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,sp,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#3\]'
--- /dev/null
+ ld1h 0, pn8/z, [x0]
+ ld1h { z0.h - z1.h }, 0, [x0]
+ ld1h { z0.h - z1.h }, pn8/z, 0
+
+ ld1h { z0.h - z2.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z1.h - z2.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, p8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/m, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8.h, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn0/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn7/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [w0, w1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [xzr, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [sp, sp, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #2]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #3]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #4]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, w1, sxtw #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, w1, uxtw #1]
+
+ ld1h { z1.h - z4.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z2.h - z5.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z3.h - z6.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, p8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/m, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8.h, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn0/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn7/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [w0, w1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [xzr, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [sp, sp, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #2]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #3]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #4]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, w1, sxtw #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, w1, uxtw #1]
+
+ ld1h { z0.h, z2.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z3.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z4.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z8.h, z16.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z24.h, z0.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z8.h, z0.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.d, z8.d }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z8.h }, p8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [w0, w30, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [xzr, xzr, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, sp, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #2]
+
+ ld1h { z4.h, z8.h, z12.h, z16.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z20.h, z24.h, z28.h, z0.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, p8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [w0, w30, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [xzr, xzr, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, sp, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #3]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-4.s
+#error_output: sme2-4-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z1\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z30\.h-z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z12\.h-z13\.h},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z3\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z28\.h-z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z8\.h-z11\.h},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z8\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z9\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z10\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z4\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z6\.h,z14\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z7\.h,z15\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z24\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z25\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z26\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z27\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z20\.h,z28\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z21\.h,z29\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z22\.h,z30\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z23\.h,z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z1\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z30\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z14\.h-z15\.h},pn9/z,\[x26,x3,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z3\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z28\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z8\.h-z11\.h},pn11/z,\[x27,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z8\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z9\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z10\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z4\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z6\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z7\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z24\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z25\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z26\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z27\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z20\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z21\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z22\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z23\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn14/z,\[x15,x24,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11/z,\[x4,x6,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z1\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z30\.h-z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z12\.h-z13\.h},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z3\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z28\.h-z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z8\.h-z11\.h},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z8\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z9\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z10\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z4\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z6\.h,z14\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z7\.h,z15\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z24\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z25\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z26\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z27\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z20\.h,z28\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z21\.h,z29\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z22\.h,z30\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z23\.h,z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z1\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z30\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z14\.h-z15\.h},pn9/z,\[x26,x3,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z3\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z28\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z8\.h-z11\.h},pn11/z,\[x27,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z8\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z9\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z10\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z4\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z6\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z7\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z24\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z25\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z26\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z27\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z20\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z21\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z22\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z23\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn14/z,\[x15,x24,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11/z,\[x4,x6,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z1\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z30\.h-z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z12\.h-z13\.h},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z3\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z28\.h-z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z8\.h-z11\.h},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z8\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z9\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z10\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z4\.h,z12\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z6\.h,z14\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z7\.h,z15\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z24\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z25\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z26\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z27\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z20\.h,z28\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z21\.h,z29\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z22\.h,z30\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z23\.h,z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z1\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z30\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z14\.h-z15\.h},pn9,\[x26,x3,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z3\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z28\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z8\.h-z11\.h},pn11,\[x27,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z8\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z9\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z10\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z4\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z6\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z7\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z24\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z25\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z26\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z27\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z20\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z21\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z22\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z23\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn14,\[x15,x24,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11,\[x4,x6,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z1\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z30\.h-z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z12\.h-z13\.h},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z3\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z28\.h-z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z8\.h-z11\.h},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z8\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z9\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z10\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z4\.h,z12\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z6\.h,z14\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z7\.h,z15\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z24\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z25\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z26\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z27\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z20\.h,z28\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z21\.h,z29\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z22\.h,z30\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z23\.h,z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z1\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z30\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z14\.h-z15\.h},pn9,\[x26,x3,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z3\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z28\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z8\.h-z11\.h},pn11,\[x27,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z8\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z9\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z10\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z4\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z6\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z7\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z24\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z25\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z26\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z27\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z20\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z21\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z22\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z23\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn14,\[x15,x24,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl 1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0,X1,LSL#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x30,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,xzr,lsl#1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11,\[x4,x6,lsl#1\]'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
+[^:]+: a040201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a0403c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0\]
+[^:]+: a04023c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30\]
+[^:]+: a04023e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp\]
+[^:]+: a0482000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0472000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b356c ld1h {z12\.h-z13\.h}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
+[^:]+: a040a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0\]
+[^:]+: a040bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0\]
+[^:]+: a040a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30\]
+[^:]+: a040a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp\]
+[^:]+: a048a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ae28 ld1h {z8\.h-z11\.h}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
+[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
+[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
+[^:]+: a1402001 ld1h {z1\.h, z9\.h}, pn8/z, \[x0\]
+[^:]+: a1402002 ld1h {z2\.h, z10\.h}, pn8/z, \[x0\]
+[^:]+: a1402003 ld1h {z3\.h, z11\.h}, pn8/z, \[x0\]
+[^:]+: a1402004 ld1h {z4\.h, z12\.h}, pn8/z, \[x0\]
+[^:]+: a1402005 ld1h {z5\.h, z13\.h}, pn8/z, \[x0\]
+[^:]+: a1402006 ld1h {z6\.h, z14\.h}, pn8/z, \[x0\]
+[^:]+: a1402007 ld1h {z7\.h, z15\.h}, pn8/z, \[x0\]
+[^:]+: a1402010 ld1h {z16\.h, z24\.h}, pn8/z, \[x0\]
+[^:]+: a1402011 ld1h {z17\.h, z25\.h}, pn8/z, \[x0\]
+[^:]+: a1402012 ld1h {z18\.h, z26\.h}, pn8/z, \[x0\]
+[^:]+: a1402013 ld1h {z19\.h, z27\.h}, pn8/z, \[x0\]
+[^:]+: a1402014 ld1h {z20\.h, z28\.h}, pn8/z, \[x0\]
+[^:]+: a1402015 ld1h {z21\.h, z29\.h}, pn8/z, \[x0\]
+[^:]+: a1402016 ld1h {z22\.h, z30\.h}, pn8/z, \[x0\]
+[^:]+: a1402017 ld1h {z23\.h, z31\.h}, pn8/z, \[x0\]
+[^:]+: a1403c00 ld1h {z0\.h, z8\.h}, pn15/z, \[x0\]
+[^:]+: a14023c0 ld1h {z0\.h, z8\.h}, pn8/z, \[x30\]
+[^:]+: a14023e0 ld1h {z0\.h, z8\.h}, pn8/z, \[sp\]
+[^:]+: a1482000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1472000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1432ac3 ld1h {z3\.h, z11\.h}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
+[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
+[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
+[^:]+: a140a001 ld1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0\]
+[^:]+: a140a002 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0\]
+[^:]+: a140a003 ld1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0\]
+[^:]+: a140a010 ld1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0\]
+[^:]+: a140a011 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0\]
+[^:]+: a140a012 ld1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0\]
+[^:]+: a140a013 ld1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0\]
+[^:]+: a140bc00 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0\]
+[^:]+: a140a3c0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30\]
+[^:]+: a140a3e0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp\]
+[^:]+: a148a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a147a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a142bba2 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn14/z, \[x29, #8, mul vl\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a0013c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a00123c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a00123e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01e2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01f2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a003274e ld1h {z14\.h-z15\.h}, pn9/z, \[x26, x3, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a001bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a001a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a001a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a01ea000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a01fa000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a001af68 ld1h {z8\.h-z11\.h}, pn11/z, \[x27, x1, lsl #1\]
+[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012001 ld1h {z1\.h, z9\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012002 ld1h {z2\.h, z10\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012003 ld1h {z3\.h, z11\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012004 ld1h {z4\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012005 ld1h {z5\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012006 ld1h {z6\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012007 ld1h {z7\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012010 ld1h {z16\.h, z24\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012011 ld1h {z17\.h, z25\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012012 ld1h {z18\.h, z26\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012013 ld1h {z19\.h, z27\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012014 ld1h {z20\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012015 ld1h {z21\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012016 ld1h {z22\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1012017 ld1h {z23\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a1013c00 ld1h {z0\.h, z8\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a10123c0 ld1h {z0\.h, z8\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a10123e0 ld1h {z0\.h, z8\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a11e2000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a11f2000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a11839e5 ld1h {z5\.h, z13\.h}, pn14/z, \[x15, x24, lsl #1\]
+[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a001 ld1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a002 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a003 ld1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a010 ld1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a011 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a012 ld1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101a013 ld1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
+[^:]+: a101bc00 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0, x1, lsl #1\]
+[^:]+: a101a3c0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30, x1, lsl #1\]
+[^:]+: a101a3e0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp, x1, lsl #1\]
+[^:]+: a11ea000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x30, lsl #1\]
+[^:]+: a11fa000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, xzr, lsl #1\]
+[^:]+: a106ac91 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11/z, \[x4, x6, lsl #1\]
+[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
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+[^:]+: a021bc00 st1h {z0\.h-z3\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a021a3c0 st1h {z0\.h-z3\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a021a3e0 st1h {z0\.h-z3\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03ea000 st1h {z0\.h-z3\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03fa000 st1h {z0\.h-z3\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a021af68 st1h {z8\.h-z11\.h}, pn11, \[x27, x1, lsl #1\]
+[^:]+: a1212000 st1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212000 st1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212000 st1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212001 st1h {z1\.h, z9\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212002 st1h {z2\.h, z10\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212003 st1h {z3\.h, z11\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212004 st1h {z4\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212005 st1h {z5\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212006 st1h {z6\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212007 st1h {z7\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212010 st1h {z16\.h, z24\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212011 st1h {z17\.h, z25\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212012 st1h {z18\.h, z26\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212013 st1h {z19\.h, z27\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212014 st1h {z20\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212015 st1h {z21\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212016 st1h {z22\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212017 st1h {z23\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1213c00 st1h {z0\.h, z8\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a12123c0 st1h {z0\.h, z8\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a12123e0 st1h {z0\.h, z8\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a13e2000 st1h {z0\.h, z8\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a13f2000 st1h {z0\.h, z8\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a13839e5 st1h {z5\.h, z13\.h}, pn14, \[x15, x24, lsl #1\]
+[^:]+: a121a000 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a000 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a000 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a001 st1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a002 st1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a003 st1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a010 st1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a011 st1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a012 st1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a013 st1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121bc00 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a121a3c0 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a121a3e0 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a13ea000 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a13fa000 st1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a126ac91 st1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11, \[x4, x6, lsl #1\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a0602001 stnt1h {z0\.h-z1\.h}, pn8, \[x0\]
+[^:]+: a060201f stnt1h {z30\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a0603c01 stnt1h {z0\.h-z1\.h}, pn15, \[x0\]
+[^:]+: a06023c1 stnt1h {z0\.h-z1\.h}, pn8, \[x30\]
+[^:]+: a06023e1 stnt1h {z0\.h-z1\.h}, pn8, \[sp\]
+[^:]+: a0682001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0672001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b356d stnt1h {z12\.h-z13\.h}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0\]
+[^:]+: a060a01d stnt1h {z28\.h-z31\.h}, pn8, \[x0\]
+[^:]+: a060bc01 stnt1h {z0\.h-z3\.h}, pn15, \[x0\]
+[^:]+: a060a3c1 stnt1h {z0\.h-z3\.h}, pn8, \[x30\]
+[^:]+: a060a3e1 stnt1h {z0\.h-z3\.h}, pn8, \[sp\]
+[^:]+: a068a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ae29 stnt1h {z8\.h-z11\.h}, pn11, \[x17, #20, mul vl\]
+[^:]+: a1602008 stnt1h {z0\.h, z8\.h}, pn8, \[x0\]
+[^:]+: a1602008 stnt1h {z0\.h, z8\.h}, pn8, \[x0\]
+[^:]+: a1602008 stnt1h {z0\.h, z8\.h}, pn8, \[x0\]
+[^:]+: a1602009 stnt1h {z1\.h, z9\.h}, pn8, \[x0\]
+[^:]+: a160200a stnt1h {z2\.h, z10\.h}, pn8, \[x0\]
+[^:]+: a160200b stnt1h {z3\.h, z11\.h}, pn8, \[x0\]
+[^:]+: a160200c stnt1h {z4\.h, z12\.h}, pn8, \[x0\]
+[^:]+: a160200d stnt1h {z5\.h, z13\.h}, pn8, \[x0\]
+[^:]+: a160200e stnt1h {z6\.h, z14\.h}, pn8, \[x0\]
+[^:]+: a160200f stnt1h {z7\.h, z15\.h}, pn8, \[x0\]
+[^:]+: a1602018 stnt1h {z16\.h, z24\.h}, pn8, \[x0\]
+[^:]+: a1602019 stnt1h {z17\.h, z25\.h}, pn8, \[x0\]
+[^:]+: a160201a stnt1h {z18\.h, z26\.h}, pn8, \[x0\]
+[^:]+: a160201b stnt1h {z19\.h, z27\.h}, pn8, \[x0\]
+[^:]+: a160201c stnt1h {z20\.h, z28\.h}, pn8, \[x0\]
+[^:]+: a160201d stnt1h {z21\.h, z29\.h}, pn8, \[x0\]
+[^:]+: a160201e stnt1h {z22\.h, z30\.h}, pn8, \[x0\]
+[^:]+: a160201f stnt1h {z23\.h, z31\.h}, pn8, \[x0\]
+[^:]+: a1603c08 stnt1h {z0\.h, z8\.h}, pn15, \[x0\]
+[^:]+: a16023c8 stnt1h {z0\.h, z8\.h}, pn8, \[x30\]
+[^:]+: a16023e8 stnt1h {z0\.h, z8\.h}, pn8, \[sp\]
+[^:]+: a1682008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a1672008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, #14, mul vl\]
+[^:]+: a1632acb stnt1h {z3\.h, z11\.h}, pn10, \[x22, #6, mul vl\]
+[^:]+: a160a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0\]
+[^:]+: a160a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0\]
+[^:]+: a160a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0\]
+[^:]+: a160a009 stnt1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8, \[x0\]
+[^:]+: a160a00a stnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8, \[x0\]
+[^:]+: a160a00b stnt1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8, \[x0\]
+[^:]+: a160a018 stnt1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8, \[x0\]
+[^:]+: a160a019 stnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8, \[x0\]
+[^:]+: a160a01a stnt1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8, \[x0\]
+[^:]+: a160a01b stnt1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8, \[x0\]
+[^:]+: a160bc08 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15, \[x0\]
+[^:]+: a160a3c8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x30\]
+[^:]+: a160a3e8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[sp\]
+[^:]+: a168a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a167a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, #28, mul vl\]
+[^:]+: a162bbaa stnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn14, \[x29, #8, mul vl\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0212001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021201f stnt1h {z30\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a0213c01 stnt1h {z0\.h-z1\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a02123c1 stnt1h {z0\.h-z1\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a02123e1 stnt1h {z0\.h-z1\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03e2001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03f2001 stnt1h {z0\.h-z1\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a023274f stnt1h {z14\.h-z15\.h}, pn9, \[x26, x3, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021a01d stnt1h {z28\.h-z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a021bc01 stnt1h {z0\.h-z3\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a021a3c1 stnt1h {z0\.h-z3\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a021a3e1 stnt1h {z0\.h-z3\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a03ea001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a03fa001 stnt1h {z0\.h-z3\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a021af69 stnt1h {z8\.h-z11\.h}, pn11, \[x27, x1, lsl #1\]
+[^:]+: a1212008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212009 stnt1h {z1\.h, z9\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200a stnt1h {z2\.h, z10\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200b stnt1h {z3\.h, z11\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200c stnt1h {z4\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200d stnt1h {z5\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200e stnt1h {z6\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121200f stnt1h {z7\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212018 stnt1h {z16\.h, z24\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1212019 stnt1h {z17\.h, z25\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201a stnt1h {z18\.h, z26\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201b stnt1h {z19\.h, z27\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201c stnt1h {z20\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201d stnt1h {z21\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201e stnt1h {z22\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121201f stnt1h {z23\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a1213c08 stnt1h {z0\.h, z8\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a12123c8 stnt1h {z0\.h, z8\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a12123e8 stnt1h {z0\.h, z8\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a13e2008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a13f2008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a13839ed stnt1h {z5\.h, z13\.h}, pn14, \[x15, x24, lsl #1\]
+[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a009 stnt1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a00a stnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a00b stnt1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a018 stnt1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a019 stnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a01a stnt1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121a01b stnt1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
+[^:]+: a121bc08 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15, \[x0, x1, lsl #1\]
+[^:]+: a121a3c8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x30, x1, lsl #1\]
+[^:]+: a121a3e8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[sp, x1, lsl #1\]
+[^:]+: a13ea008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x30, lsl #1\]
+[^:]+: a13fa008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, xzr, lsl #1\]
+[^:]+: a126ac99 stnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11, \[x4, x6, lsl #1\]
--- /dev/null
+ ld1h { z0.h - z1.h }, pn8/z, [x0]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H - Z1.H }, PN8/Z, [X0]
+ ld1h { z30.h - z31.h }, pn8/z, [x0]
+ ld1h { z0.h - z1.h }, pn15/z, [x0]
+ ld1h { z0.h - z1.h }, pn8/z, [x30]
+ ld1h { z0.h - z1.h }, pn8/z, [sp]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
+ ld1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
+
+ ld1h { z0.h - z3.h }, pn8/z, [x0]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H - Z3.H }, PN8/Z, [X0]
+ ld1h { z28.h - z31.h }, pn8/z, [x0]
+ ld1h { z0.h - z3.h }, pn15/z, [x0]
+ ld1h { z0.h - z3.h }, pn8/z, [x30]
+ ld1h { z0.h - z3.h }, pn8/z, [sp]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
+ ld1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
+
+ ld1h { z0.h, z8.h }, pn8/z, [x0]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H, Z8.H }, PN8/Z, [X0]
+ ld1h { z1.h, z9.h }, pn8/z, [x0]
+ ld1h { z2.h, z10.h }, pn8/z, [x0]
+ ld1h { z3.h, z11.h }, pn8/z, [x0]
+ ld1h { z4.h, z12.h }, pn8/z, [x0]
+ ld1h { z5.h, z13.h }, pn8/z, [x0]
+ ld1h { z6.h, z14.h }, pn8/z, [x0]
+ ld1h { z7.h, z15.h }, pn8/z, [x0]
+ ld1h { z16.h, z24.h }, pn8/z, [x0]
+ ld1h { z17.h, z25.h }, pn8/z, [x0]
+ ld1h { z18.h, z26.h }, pn8/z, [x0]
+ ld1h { z19.h, z27.h }, pn8/z, [x0]
+ ld1h { z20.h, z28.h }, pn8/z, [x0]
+ ld1h { z21.h, z29.h }, pn8/z, [x0]
+ ld1h { z22.h, z30.h }, pn8/z, [x0]
+ ld1h { z23.h, z31.h }, pn8/z, [x0]
+ ld1h { z0.h, z8.h }, pn15/z, [x0]
+ ld1h { z0.h, z8.h }, pn8/z, [x30]
+ ld1h { z0.h, z8.h }, pn8/z, [sp]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, #-16, mul vl]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, #14, mul vl]
+ ld1h { z3.h, z11.h }, pn10/z, [x22, #6, mul vl]
+
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #0, mul vl]
+ LD1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0]
+ ld1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0]
+ ld1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0]
+ ld1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0]
+ ld1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0]
+ ld1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0]
+ ld1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0]
+ ld1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #-32, mul vl]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #28, mul vl]
+ ld1h { z2.h, z6.h, z10.h, z14.h }, pn14/z, [x29, #8, mul vl]
+
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
+
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
+
+ ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H, Z8.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z1.h, z9.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z2.h, z10.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z3.h, z11.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z4.h, z12.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z5.h, z13.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z6.h, z14.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z7.h, z15.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z16.h, z24.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z17.h, z25.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z18.h, z26.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z19.h, z27.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z20.h, z28.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z21.h, z29.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z22.h, z30.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z23.h, z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z8.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h, z8.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z5.h, z13.h }, pn14/z, [x15, x24, lsl #1]
+
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl 1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #1]
+ LD1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0, X1, LSL #1]
+ ld1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp, x1, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x30, lsl #1]
+ ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, xzr, lsl #1]
+ ld1h { z17.h, z21.h, z25.h, z29.h }, pn11/z, [x4, x6, lsl #1]
+
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0]
+ ldnt1h { z30.h - z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn15/z, [x0]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x30]
+ ldnt1h { z0.h - z1.h }, pn8/z, [sp]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
+ ldnt1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0]
+ ldnt1h { z28.h - z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn15/z, [x0]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x30]
+ ldnt1h { z0.h - z3.h }, pn8/z, [sp]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
+ ldnt1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H, Z8.H }, PN8/Z, [X0]
+ ldnt1h { z1.h, z9.h }, pn8/z, [x0]
+ ldnt1h { z2.h, z10.h }, pn8/z, [x0]
+ ldnt1h { z3.h, z11.h }, pn8/z, [x0]
+ ldnt1h { z4.h, z12.h }, pn8/z, [x0]
+ ldnt1h { z5.h, z13.h }, pn8/z, [x0]
+ ldnt1h { z6.h, z14.h }, pn8/z, [x0]
+ ldnt1h { z7.h, z15.h }, pn8/z, [x0]
+ ldnt1h { z16.h, z24.h }, pn8/z, [x0]
+ ldnt1h { z17.h, z25.h }, pn8/z, [x0]
+ ldnt1h { z18.h, z26.h }, pn8/z, [x0]
+ ldnt1h { z19.h, z27.h }, pn8/z, [x0]
+ ldnt1h { z20.h, z28.h }, pn8/z, [x0]
+ ldnt1h { z21.h, z29.h }, pn8/z, [x0]
+ ldnt1h { z22.h, z30.h }, pn8/z, [x0]
+ ldnt1h { z23.h, z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h, z8.h }, pn15/z, [x0]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x30]
+ ldnt1h { z0.h, z8.h }, pn8/z, [sp]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, #-16, mul vl]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, #14, mul vl]
+ ldnt1h { z3.h, z11.h }, pn10/z, [x22, #6, mul vl]
+
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #0, mul vl]
+ LDNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0]
+ ldnt1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0]
+ ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0]
+ ldnt1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0]
+ ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0]
+ ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0]
+ ldnt1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0]
+ ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #-32, mul vl]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #28, mul vl]
+ ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn14/z, [x29, #8, mul vl]
+
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
+
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
+
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H, Z8.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z1.h, z9.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z2.h, z10.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z3.h, z11.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z4.h, z12.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z5.h, z13.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z6.h, z14.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z7.h, z15.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z16.h, z24.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z17.h, z25.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z18.h, z26.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z19.h, z27.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z20.h, z28.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z21.h, z29.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z22.h, z30.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z23.h, z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h, z8.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h, z8.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h, z8.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z5.h, z13.h }, pn14/z, [x15, x24, lsl #1]
+
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl 1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #1]
+ LDNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0, X1, LSL #1]
+ ldnt1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0, x1, lsl #1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30, x1, lsl #1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp, x1, lsl #1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x30, lsl #1]
+ ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, xzr, lsl #1]
+ ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn11/z, [x4, x6, lsl #1]
+
+ st1h { z0.h - z1.h }, pn8, [x0]
+ st1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H - Z1.H }, PN8, [X0]
+ st1h { z30.h - z31.h }, pn8, [x0]
+ st1h { z0.h - z1.h }, pn15, [x0]
+ st1h { z0.h - z1.h }, pn8, [x30]
+ st1h { z0.h - z1.h }, pn8, [sp]
+ st1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
+ st1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
+ st1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
+
+ st1h { z0.h - z3.h }, pn8, [x0]
+ st1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H - Z3.H }, PN8, [X0]
+ st1h { z28.h - z31.h }, pn8, [x0]
+ st1h { z0.h - z3.h }, pn15, [x0]
+ st1h { z0.h - z3.h }, pn8, [x30]
+ st1h { z0.h - z3.h }, pn8, [sp]
+ st1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
+ st1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
+ st1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
+
+ st1h { z0.h, z8.h }, pn8, [x0]
+ st1h { z0.h, z8.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H, Z8.H }, PN8, [X0]
+ st1h { z1.h, z9.h }, pn8, [x0]
+ st1h { z2.h, z10.h }, pn8, [x0]
+ st1h { z3.h, z11.h }, pn8, [x0]
+ st1h { z4.h, z12.h }, pn8, [x0]
+ st1h { z5.h, z13.h }, pn8, [x0]
+ st1h { z6.h, z14.h }, pn8, [x0]
+ st1h { z7.h, z15.h }, pn8, [x0]
+ st1h { z16.h, z24.h }, pn8, [x0]
+ st1h { z17.h, z25.h }, pn8, [x0]
+ st1h { z18.h, z26.h }, pn8, [x0]
+ st1h { z19.h, z27.h }, pn8, [x0]
+ st1h { z20.h, z28.h }, pn8, [x0]
+ st1h { z21.h, z29.h }, pn8, [x0]
+ st1h { z22.h, z30.h }, pn8, [x0]
+ st1h { z23.h, z31.h }, pn8, [x0]
+ st1h { z0.h, z8.h }, pn15, [x0]
+ st1h { z0.h, z8.h }, pn8, [x30]
+ st1h { z0.h, z8.h }, pn8, [sp]
+ st1h { z0.h, z8.h }, pn8, [x0, #-16, mul vl]
+ st1h { z0.h, z8.h }, pn8, [x0, #14, mul vl]
+ st1h { z3.h, z11.h }, pn10, [x22, #6, mul vl]
+
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #0, mul vl]
+ ST1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0]
+ st1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0]
+ st1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0]
+ st1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0]
+ st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0]
+ st1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0]
+ st1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0]
+ st1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #-32, mul vl]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #28, mul vl]
+ st1h { z2.h, z6.h, z10.h, z14.h }, pn14, [x29, #8, mul vl]
+
+ st1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
+ st1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
+
+ st1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
+ st1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
+
+ st1h { z0.h, z8.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h, z8.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H, Z8.H }, PN8, [X0, X1, LSL #1]
+ st1h { z1.h, z9.h }, pn8, [x0, x1, lsl #1]
+ st1h { z2.h, z10.h }, pn8, [x0, x1, lsl #1]
+ st1h { z3.h, z11.h }, pn8, [x0, x1, lsl #1]
+ st1h { z4.h, z12.h }, pn8, [x0, x1, lsl #1]
+ st1h { z5.h, z13.h }, pn8, [x0, x1, lsl #1]
+ st1h { z6.h, z14.h }, pn8, [x0, x1, lsl #1]
+ st1h { z7.h, z15.h }, pn8, [x0, x1, lsl #1]
+ st1h { z16.h, z24.h }, pn8, [x0, x1, lsl #1]
+ st1h { z17.h, z25.h }, pn8, [x0, x1, lsl #1]
+ st1h { z18.h, z26.h }, pn8, [x0, x1, lsl #1]
+ st1h { z19.h, z27.h }, pn8, [x0, x1, lsl #1]
+ st1h { z20.h, z28.h }, pn8, [x0, x1, lsl #1]
+ st1h { z21.h, z29.h }, pn8, [x0, x1, lsl #1]
+ st1h { z22.h, z30.h }, pn8, [x0, x1, lsl #1]
+ st1h { z23.h, z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h, z8.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h, z8.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h, z8.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h, z8.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h, z8.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z5.h, z13.h }, pn14, [x15, x24, lsl #1]
+
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl 1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl #1]
+ ST1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0, X1, LSL #1]
+ st1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0, x1, lsl #1]
+ st1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0, x1, lsl #1]
+ st1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0, x1, lsl #1]
+ st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0, x1, lsl #1]
+ st1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0, x1, lsl #1]
+ st1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0, x1, lsl #1]
+ st1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0, x1, lsl #1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0, x1, lsl #1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30, x1, lsl #1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp, x1, lsl #1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x30, lsl #1]
+ st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, xzr, lsl #1]
+ st1h { z17.h, z21.h, z25.h, z29.h }, pn11, [x4, x6, lsl #1]
+
+ stnt1h { z0.h - z1.h }, pn8, [x0]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H - Z1.H }, PN8, [X0]
+ stnt1h { z30.h - z31.h }, pn8, [x0]
+ stnt1h { z0.h - z1.h }, pn15, [x0]
+ stnt1h { z0.h - z1.h }, pn8, [x30]
+ stnt1h { z0.h - z1.h }, pn8, [sp]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
+ stnt1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
+ stnt1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
+
+ stnt1h { z0.h - z3.h }, pn8, [x0]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H - Z3.H }, PN8, [X0]
+ stnt1h { z28.h - z31.h }, pn8, [x0]
+ stnt1h { z0.h - z3.h }, pn15, [x0]
+ stnt1h { z0.h - z3.h }, pn8, [x30]
+ stnt1h { z0.h - z3.h }, pn8, [sp]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
+ stnt1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
+ stnt1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
+
+ stnt1h { z0.h, z8.h }, pn8, [x0]
+ stnt1h { z0.h, z8.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H, Z8.H }, PN8, [X0]
+ stnt1h { z1.h, z9.h }, pn8, [x0]
+ stnt1h { z2.h, z10.h }, pn8, [x0]
+ stnt1h { z3.h, z11.h }, pn8, [x0]
+ stnt1h { z4.h, z12.h }, pn8, [x0]
+ stnt1h { z5.h, z13.h }, pn8, [x0]
+ stnt1h { z6.h, z14.h }, pn8, [x0]
+ stnt1h { z7.h, z15.h }, pn8, [x0]
+ stnt1h { z16.h, z24.h }, pn8, [x0]
+ stnt1h { z17.h, z25.h }, pn8, [x0]
+ stnt1h { z18.h, z26.h }, pn8, [x0]
+ stnt1h { z19.h, z27.h }, pn8, [x0]
+ stnt1h { z20.h, z28.h }, pn8, [x0]
+ stnt1h { z21.h, z29.h }, pn8, [x0]
+ stnt1h { z22.h, z30.h }, pn8, [x0]
+ stnt1h { z23.h, z31.h }, pn8, [x0]
+ stnt1h { z0.h, z8.h }, pn15, [x0]
+ stnt1h { z0.h, z8.h }, pn8, [x30]
+ stnt1h { z0.h, z8.h }, pn8, [sp]
+ stnt1h { z0.h, z8.h }, pn8, [x0, #-16, mul vl]
+ stnt1h { z0.h, z8.h }, pn8, [x0, #14, mul vl]
+ stnt1h { z3.h, z11.h }, pn10, [x22, #6, mul vl]
+
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #0, mul vl]
+ STNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0]
+ stnt1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0]
+ stnt1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0]
+ stnt1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0]
+ stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0]
+ stnt1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0]
+ stnt1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0]
+ stnt1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #-32, mul vl]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #28, mul vl]
+ stnt1h { z2.h, z6.h, z10.h, z14.h }, pn14, [x29, #8, mul vl]
+
+ stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
+
+ stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
+
+ stnt1h { z0.h, z8.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h, z8.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H, Z8.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z1.h, z9.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z2.h, z10.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z3.h, z11.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z4.h, z12.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z5.h, z13.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z6.h, z14.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z7.h, z15.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z16.h, z24.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z17.h, z25.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z18.h, z26.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z19.h, z27.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z20.h, z28.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z21.h, z29.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z22.h, z30.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z23.h, z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h, z8.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h, z8.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h, z8.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h, z8.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h, z8.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z5.h, z13.h }, pn14, [x15, x24, lsl #1]
+
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl 1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl #1]
+ STNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0, X1, LSL #1]
+ stnt1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0, x1, lsl #1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0, x1, lsl #1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30, x1, lsl #1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp, x1, lsl #1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x30, lsl #1]
+ stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, xzr, lsl #1]
+ stnt1h { z17.h, z21.h, z25.h, z29.h }, pn11, [x4, x6, lsl #1]
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-5-invalid.s
+#error_output: sme2-5-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1w 0,pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1w {z0\.s-z1\.s},0,\[x0\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,0'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1w {z0\.s-z2\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z1\.s-z2\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s-z1\.s},p8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8/m,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8\.s,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z1\.s},pn0/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z1\.s},pn7/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[w0,w1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[xzr,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[sp,sp,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,w1,sxtw#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,w1,uxtw#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z1\.s-z4\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z2\.s-z5\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z3\.s-z6\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s-z3\.s},p8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8/m,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8\.s,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z3\.s},pn0/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z3\.s},pn7/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[w0,w1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[xzr,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[sp,sp,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#3\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#4\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,w1,sxtw#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,w1,uxtw#2\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z2\.s},pn8/z,\[x0,x1,lsl#2\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z3\.s},pn8/z,\[x0,x1,lsl#2\]`
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z4\.s},pn8/z,\[x0,x1,lsl#2\]`
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z8\.s,z16\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z24\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z8\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]`
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s,z8\.s},p8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[w0,w30,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[xzr,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[x0,sp,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#1\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z4\.s,z8\.s,z12\.s,z16\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z20\.s,z24\.s,z28\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},p8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[w0,w30,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[xzr,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,sp,lsl#2\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#1\]'
--- /dev/null
+ ld1w 0, pn8/z, [x0]
+ ld1w { z0.s - z1.s }, 0, [x0]
+ ld1w { z0.s - z1.s }, pn8/z, 0
+
+ ld1w { z0.s - z2.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z1.s - z2.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, p8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/m, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8.s, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn0/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn7/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [w0, w1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [xzr, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [sp, sp, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #1]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #3]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #4]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, w1, sxtw #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, w1, uxtw #2]
+
+ ld1w { z1.s - z4.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z2.s - z5.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z3.s - z6.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, p8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/m, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8.s, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn0/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn7/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [w0, w1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [xzr, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [sp, sp, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #1]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #3]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #4]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, w1, sxtw #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, w1, uxtw #2]
+
+ ld1w { z0.s, z2.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z3.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z4.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z8.s, z16.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z24.s, z0.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z8.s, z0.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.h, z8.h }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z8.s }, p8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [w0, w30, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [xzr, xzr, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, sp, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #1]
+
+ ld1w { z4.s, z8.s, z12.s, z16.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z20.s, z24.s, z28.s, z0.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, p8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [w0, w30, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [xzr, xzr, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, sp, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #1]
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-5.s
+#error_output: sme2-5-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z1\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z30\.s-z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z12\.s-z13\.s},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z3\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z28\.s-z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z8\.s-z11\.s},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z8\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z9\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z10\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z4\.s,z12\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z6\.s,z14\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z7\.s,z15\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z24\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z25\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z26\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z27\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z20\.s,z28\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z21\.s,z29\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z22\.s,z30\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z23\.s,z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z1\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z30\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z14\.s-z15\.s},pn9/z,\[x26,x3,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z3\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z28\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z8\.s-z11\.s},pn11/z,\[x27,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z8\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z9\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z10\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z4\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z6\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z7\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z24\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z25\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z26\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z27\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z20\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z21\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z22\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z23\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn14/z,\[x15,x24,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11/z,\[x4,x6,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z1\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z30\.s-z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z12\.s-z13\.s},pn13/z,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z3\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z28\.s-z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z8\.s-z11\.s},pn11/z,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z8\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z9\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z10\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z4\.s,z12\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z6\.s,z14\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z7\.s,z15\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z24\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z25\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z26\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z27\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z20\.s,z28\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z21\.s,z29\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z22\.s,z30\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z23\.s,z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn10/z,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14/z,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z1\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z30\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z14\.s-z15\.s},pn9/z,\[x26,x3,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z3\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z28\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z8\.s-z11\.s},pn11/z,\[x27,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z8\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z9\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z10\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z4\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z6\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z7\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z24\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z25\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z26\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z27\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z20\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z21\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z22\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z23\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn14/z,\[x15,x24,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11/z,\[x4,x6,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z1\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z30\.s-z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z12\.s-z13\.s},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z3\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z28\.s-z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z8\.s-z11\.s},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z8\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z9\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z10\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z4\.s,z12\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z6\.s,z14\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z7\.s,z15\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z24\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z25\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z26\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z27\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z20\.s,z28\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z21\.s,z29\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z22\.s,z30\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z23\.s,z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z1\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z30\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z14\.s-z15\.s},pn9,\[x26,x3,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z3\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z28\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z8\.s-z11\.s},pn11,\[x27,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z8\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z9\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z10\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z4\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z6\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z7\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z24\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z25\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z26\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z27\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z20\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z21\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z22\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z23\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn14,\[x15,x24,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11,\[x4,x6,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z1\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z30\.s-z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z12\.s-z13\.s},pn13,\[x11,#-10,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z3\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z28\.s-z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z8\.s-z11\.s},pn11,\[x17,#20,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z8\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z9\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z10\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z4\.s,z12\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z6\.s,z14\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z7\.s,z15\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z24\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z25\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z26\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z27\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z20\.s,z28\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z21\.s,z29\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z22\.s,z30\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z23\.s,z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#-16,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#14,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn10,\[x22,#6,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#0,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#-32,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#28,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14,\[x29,#8,mul vl\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z1\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z30\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z14\.s-z15\.s},pn9,\[x26,x3,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z3\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z28\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z8\.s-z11\.s},pn11,\[x27,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z8\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z9\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z10\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z4\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z6\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z7\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z24\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z25\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z26\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z27\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z20\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z21\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z22\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z23\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn14,\[x15,x24,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl 2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0,X1,LSL#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp,x1,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x30,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,xzr,lsl#2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11,\[x4,x6,lsl#2\]'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a040401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a0405c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0\]
+[^:]+: a04043c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30\]
+[^:]+: a04043e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp\]
+[^:]+: a0484000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0474000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b556c ld1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a040dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0\]
+[^:]+: a040c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30\]
+[^:]+: a040c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp\]
+[^:]+: a048c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ce28 ld1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404001 ld1w {z1\.s, z9\.s}, pn8/z, \[x0\]
+[^:]+: a1404002 ld1w {z2\.s, z10\.s}, pn8/z, \[x0\]
+[^:]+: a1404003 ld1w {z3\.s, z11\.s}, pn8/z, \[x0\]
+[^:]+: a1404004 ld1w {z4\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a1404005 ld1w {z5\.s, z13\.s}, pn8/z, \[x0\]
+[^:]+: a1404006 ld1w {z6\.s, z14\.s}, pn8/z, \[x0\]
+[^:]+: a1404007 ld1w {z7\.s, z15\.s}, pn8/z, \[x0\]
+[^:]+: a1404010 ld1w {z16\.s, z24\.s}, pn8/z, \[x0\]
+[^:]+: a1404011 ld1w {z17\.s, z25\.s}, pn8/z, \[x0\]
+[^:]+: a1404012 ld1w {z18\.s, z26\.s}, pn8/z, \[x0\]
+[^:]+: a1404013 ld1w {z19\.s, z27\.s}, pn8/z, \[x0\]
+[^:]+: a1404014 ld1w {z20\.s, z28\.s}, pn8/z, \[x0\]
+[^:]+: a1404015 ld1w {z21\.s, z29\.s}, pn8/z, \[x0\]
+[^:]+: a1404016 ld1w {z22\.s, z30\.s}, pn8/z, \[x0\]
+[^:]+: a1404017 ld1w {z23\.s, z31\.s}, pn8/z, \[x0\]
+[^:]+: a1405c00 ld1w {z0\.s, z8\.s}, pn15/z, \[x0\]
+[^:]+: a14043c0 ld1w {z0\.s, z8\.s}, pn8/z, \[x30\]
+[^:]+: a14043e0 ld1w {z0\.s, z8\.s}, pn8/z, \[sp\]
+[^:]+: a1484000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1474000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1434ac3 ld1w {z3\.s, z11\.s}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c001 ld1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0\]
+[^:]+: a140c002 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0\]
+[^:]+: a140c003 ld1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0\]
+[^:]+: a140c010 ld1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0\]
+[^:]+: a140c011 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0\]
+[^:]+: a140c012 ld1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0\]
+[^:]+: a140c013 ld1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0\]
+[^:]+: a140dc00 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0\]
+[^:]+: a140c3c0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30\]
+[^:]+: a140c3e0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp\]
+[^:]+: a148c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a147c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a142dba2 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14/z, \[x29, #8, mul vl\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0015c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a00143c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a00143e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01e4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01f4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a003474e ld1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a001c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a001c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01ec000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01fc000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a001cf68 ld1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
+[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014001 ld1w {z1\.s, z9\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014002 ld1w {z2\.s, z10\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014003 ld1w {z3\.s, z11\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014004 ld1w {z4\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014005 ld1w {z5\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014006 ld1w {z6\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014007 ld1w {z7\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014010 ld1w {z16\.s, z24\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014011 ld1w {z17\.s, z25\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014012 ld1w {z18\.s, z26\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014013 ld1w {z19\.s, z27\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014014 ld1w {z20\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014015 ld1w {z21\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014016 ld1w {z22\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014017 ld1w {z23\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1015c00 ld1w {z0\.s, z8\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a10143c0 ld1w {z0\.s, z8\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a10143e0 ld1w {z0\.s, z8\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a11e4000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a11f4000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a11859e5 ld1w {z5\.s, z13\.s}, pn14/z, \[x15, x24, lsl #2\]
+[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c001 ld1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c002 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c003 ld1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c010 ld1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c011 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c012 ld1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c013 ld1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101dc00 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a101c3c0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a101c3e0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a11ec000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a11fc000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a106cc91 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11/z, \[x4, x6, lsl #2\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
+[^:]+: a040401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a0405c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0\]
+[^:]+: a04043c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30\]
+[^:]+: a04043e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp\]
+[^:]+: a0484001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a0474001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a04b556d ldnt1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
+[^:]+: a040c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0\]
+[^:]+: a040dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0\]
+[^:]+: a040c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30\]
+[^:]+: a040c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp\]
+[^:]+: a048c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a047c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a045ce29 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
+[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
+[^:]+: a1404009 ldnt1w {z1\.s, z9\.s}, pn8/z, \[x0\]
+[^:]+: a140400a ldnt1w {z2\.s, z10\.s}, pn8/z, \[x0\]
+[^:]+: a140400b ldnt1w {z3\.s, z11\.s}, pn8/z, \[x0\]
+[^:]+: a140400c ldnt1w {z4\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140400d ldnt1w {z5\.s, z13\.s}, pn8/z, \[x0\]
+[^:]+: a140400e ldnt1w {z6\.s, z14\.s}, pn8/z, \[x0\]
+[^:]+: a140400f ldnt1w {z7\.s, z15\.s}, pn8/z, \[x0\]
+[^:]+: a1404018 ldnt1w {z16\.s, z24\.s}, pn8/z, \[x0\]
+[^:]+: a1404019 ldnt1w {z17\.s, z25\.s}, pn8/z, \[x0\]
+[^:]+: a140401a ldnt1w {z18\.s, z26\.s}, pn8/z, \[x0\]
+[^:]+: a140401b ldnt1w {z19\.s, z27\.s}, pn8/z, \[x0\]
+[^:]+: a140401c ldnt1w {z20\.s, z28\.s}, pn8/z, \[x0\]
+[^:]+: a140401d ldnt1w {z21\.s, z29\.s}, pn8/z, \[x0\]
+[^:]+: a140401e ldnt1w {z22\.s, z30\.s}, pn8/z, \[x0\]
+[^:]+: a140401f ldnt1w {z23\.s, z31\.s}, pn8/z, \[x0\]
+[^:]+: a1405c08 ldnt1w {z0\.s, z8\.s}, pn15/z, \[x0\]
+[^:]+: a14043c8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x30\]
+[^:]+: a14043e8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[sp\]
+[^:]+: a1484008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, #-16, mul vl\]
+[^:]+: a1474008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, #14, mul vl\]
+[^:]+: a1434acb ldnt1w {z3\.s, z11\.s}, pn10/z, \[x22, #6, mul vl\]
+[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
+[^:]+: a140c009 ldnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0\]
+[^:]+: a140c00a ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0\]
+[^:]+: a140c00b ldnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0\]
+[^:]+: a140c018 ldnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0\]
+[^:]+: a140c019 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0\]
+[^:]+: a140c01a ldnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0\]
+[^:]+: a140c01b ldnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0\]
+[^:]+: a140dc08 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0\]
+[^:]+: a140c3c8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30\]
+[^:]+: a140c3e8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp\]
+[^:]+: a148c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #-32, mul vl\]
+[^:]+: a147c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #28, mul vl\]
+[^:]+: a142dbaa ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14/z, \[x29, #8, mul vl\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a0015c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a00143c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a00143e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01e4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01f4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a003474f ldnt1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a001dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a001c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a001c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a01ec001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a01fc001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a001cf69 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
+[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014009 ldnt1w {z1\.s, z9\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400a ldnt1w {z2\.s, z10\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400b ldnt1w {z3\.s, z11\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400c ldnt1w {z4\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400d ldnt1w {z5\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400e ldnt1w {z6\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101400f ldnt1w {z7\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014018 ldnt1w {z16\.s, z24\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1014019 ldnt1w {z17\.s, z25\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401a ldnt1w {z18\.s, z26\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401b ldnt1w {z19\.s, z27\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401c ldnt1w {z20\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401d ldnt1w {z21\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401e ldnt1w {z22\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101401f ldnt1w {z23\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a1015c08 ldnt1w {z0\.s, z8\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a10143c8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a10143e8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a11e4008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a11f4008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a11859ed ldnt1w {z5\.s, z13\.s}, pn14/z, \[x15, x24, lsl #2\]
+[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c009 ldnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c00a ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c00b ldnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c018 ldnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c019 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c01a ldnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101c01b ldnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
+[^:]+: a101dc08 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0, x1, lsl #2\]
+[^:]+: a101c3c8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30, x1, lsl #2\]
+[^:]+: a101c3e8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp, x1, lsl #2\]
+[^:]+: a11ec008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x30, lsl #2\]
+[^:]+: a11fc008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, xzr, lsl #2\]
+[^:]+: a106cc99 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11/z, \[x4, x6, lsl #2\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a060401e st1w {z30\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a0605c00 st1w {z0\.s-z1\.s}, pn15, \[x0\]
+[^:]+: a06043c0 st1w {z0\.s-z1\.s}, pn8, \[x30\]
+[^:]+: a06043e0 st1w {z0\.s-z1\.s}, pn8, \[sp\]
+[^:]+: a0684000 st1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0674000 st1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b556c st1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c01c st1w {z28\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a060dc00 st1w {z0\.s-z3\.s}, pn15, \[x0\]
+[^:]+: a060c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30\]
+[^:]+: a060c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp\]
+[^:]+: a068c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ce28 st1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
+[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604001 st1w {z1\.s, z9\.s}, pn8, \[x0\]
+[^:]+: a1604002 st1w {z2\.s, z10\.s}, pn8, \[x0\]
+[^:]+: a1604003 st1w {z3\.s, z11\.s}, pn8, \[x0\]
+[^:]+: a1604004 st1w {z4\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a1604005 st1w {z5\.s, z13\.s}, pn8, \[x0\]
+[^:]+: a1604006 st1w {z6\.s, z14\.s}, pn8, \[x0\]
+[^:]+: a1604007 st1w {z7\.s, z15\.s}, pn8, \[x0\]
+[^:]+: a1604010 st1w {z16\.s, z24\.s}, pn8, \[x0\]
+[^:]+: a1604011 st1w {z17\.s, z25\.s}, pn8, \[x0\]
+[^:]+: a1604012 st1w {z18\.s, z26\.s}, pn8, \[x0\]
+[^:]+: a1604013 st1w {z19\.s, z27\.s}, pn8, \[x0\]
+[^:]+: a1604014 st1w {z20\.s, z28\.s}, pn8, \[x0\]
+[^:]+: a1604015 st1w {z21\.s, z29\.s}, pn8, \[x0\]
+[^:]+: a1604016 st1w {z22\.s, z30\.s}, pn8, \[x0\]
+[^:]+: a1604017 st1w {z23\.s, z31\.s}, pn8, \[x0\]
+[^:]+: a1605c00 st1w {z0\.s, z8\.s}, pn15, \[x0\]
+[^:]+: a16043c0 st1w {z0\.s, z8\.s}, pn8, \[x30\]
+[^:]+: a16043e0 st1w {z0\.s, z8\.s}, pn8, \[sp\]
+[^:]+: a1684000 st1w {z0\.s, z8\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a1674000 st1w {z0\.s, z8\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a1634ac3 st1w {z3\.s, z11\.s}, pn10, \[x22, #6, mul vl\]
+[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c001 st1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0\]
+[^:]+: a160c002 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0\]
+[^:]+: a160c003 st1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0\]
+[^:]+: a160c010 st1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0\]
+[^:]+: a160c011 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0\]
+[^:]+: a160c012 st1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0\]
+[^:]+: a160c013 st1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0\]
+[^:]+: a160dc00 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0\]
+[^:]+: a160c3c0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30\]
+[^:]+: a160c3e0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp\]
+[^:]+: a168c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a167c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a162dba2 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14, \[x29, #8, mul vl\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021401e st1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0215c00 st1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a02143c0 st1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a02143e0 st1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03e4000 st1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03f4000 st1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a023474e st1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c01c st1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021dc00 st1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a021c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a021c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03ec000 st1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03fc000 st1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a021cf68 st1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
+[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214001 st1w {z1\.s, z9\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214002 st1w {z2\.s, z10\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214003 st1w {z3\.s, z11\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214004 st1w {z4\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214005 st1w {z5\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214006 st1w {z6\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214007 st1w {z7\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214010 st1w {z16\.s, z24\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214011 st1w {z17\.s, z25\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214012 st1w {z18\.s, z26\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214013 st1w {z19\.s, z27\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214014 st1w {z20\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214015 st1w {z21\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214016 st1w {z22\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214017 st1w {z23\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1215c00 st1w {z0\.s, z8\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a12143c0 st1w {z0\.s, z8\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a12143e0 st1w {z0\.s, z8\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a13e4000 st1w {z0\.s, z8\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a13f4000 st1w {z0\.s, z8\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a13859e5 st1w {z5\.s, z13\.s}, pn14, \[x15, x24, lsl #2\]
+[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c001 st1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c002 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c003 st1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c010 st1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c011 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c012 st1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c013 st1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121dc00 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a121c3c0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a121c3e0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a13ec000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a13fc000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a126cc91 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11, \[x4, x6, lsl #2\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
+[^:]+: a060401f stnt1w {z30\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a0605c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0\]
+[^:]+: a06043c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30\]
+[^:]+: a06043e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp\]
+[^:]+: a0684001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a0674001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a06b556d stnt1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
+[^:]+: a060c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0\]
+[^:]+: a060dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0\]
+[^:]+: a060c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30\]
+[^:]+: a060c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp\]
+[^:]+: a068c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a067c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a065ce29 stnt1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
+[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
+[^:]+: a1604009 stnt1w {z1\.s, z9\.s}, pn8, \[x0\]
+[^:]+: a160400a stnt1w {z2\.s, z10\.s}, pn8, \[x0\]
+[^:]+: a160400b stnt1w {z3\.s, z11\.s}, pn8, \[x0\]
+[^:]+: a160400c stnt1w {z4\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160400d stnt1w {z5\.s, z13\.s}, pn8, \[x0\]
+[^:]+: a160400e stnt1w {z6\.s, z14\.s}, pn8, \[x0\]
+[^:]+: a160400f stnt1w {z7\.s, z15\.s}, pn8, \[x0\]
+[^:]+: a1604018 stnt1w {z16\.s, z24\.s}, pn8, \[x0\]
+[^:]+: a1604019 stnt1w {z17\.s, z25\.s}, pn8, \[x0\]
+[^:]+: a160401a stnt1w {z18\.s, z26\.s}, pn8, \[x0\]
+[^:]+: a160401b stnt1w {z19\.s, z27\.s}, pn8, \[x0\]
+[^:]+: a160401c stnt1w {z20\.s, z28\.s}, pn8, \[x0\]
+[^:]+: a160401d stnt1w {z21\.s, z29\.s}, pn8, \[x0\]
+[^:]+: a160401e stnt1w {z22\.s, z30\.s}, pn8, \[x0\]
+[^:]+: a160401f stnt1w {z23\.s, z31\.s}, pn8, \[x0\]
+[^:]+: a1605c08 stnt1w {z0\.s, z8\.s}, pn15, \[x0\]
+[^:]+: a16043c8 stnt1w {z0\.s, z8\.s}, pn8, \[x30\]
+[^:]+: a16043e8 stnt1w {z0\.s, z8\.s}, pn8, \[sp\]
+[^:]+: a1684008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, #-16, mul vl\]
+[^:]+: a1674008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, #14, mul vl\]
+[^:]+: a1634acb stnt1w {z3\.s, z11\.s}, pn10, \[x22, #6, mul vl\]
+[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
+[^:]+: a160c009 stnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0\]
+[^:]+: a160c00a stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0\]
+[^:]+: a160c00b stnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0\]
+[^:]+: a160c018 stnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0\]
+[^:]+: a160c019 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0\]
+[^:]+: a160c01a stnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0\]
+[^:]+: a160c01b stnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0\]
+[^:]+: a160dc08 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0\]
+[^:]+: a160c3c8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30\]
+[^:]+: a160c3e8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp\]
+[^:]+: a168c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #-32, mul vl\]
+[^:]+: a167c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #28, mul vl\]
+[^:]+: a162dbaa stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14, \[x29, #8, mul vl\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021401f stnt1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a0215c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a02143c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a02143e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03e4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03f4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a023474f stnt1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a021dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a021c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a021c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a03ec001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a03fc001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a021cf69 stnt1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
+[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214009 stnt1w {z1\.s, z9\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400a stnt1w {z2\.s, z10\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400b stnt1w {z3\.s, z11\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400c stnt1w {z4\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400d stnt1w {z5\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400e stnt1w {z6\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121400f stnt1w {z7\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214018 stnt1w {z16\.s, z24\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1214019 stnt1w {z17\.s, z25\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401a stnt1w {z18\.s, z26\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401b stnt1w {z19\.s, z27\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401c stnt1w {z20\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401d stnt1w {z21\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401e stnt1w {z22\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121401f stnt1w {z23\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a1215c08 stnt1w {z0\.s, z8\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a12143c8 stnt1w {z0\.s, z8\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a12143e8 stnt1w {z0\.s, z8\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a13e4008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a13f4008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a13859ed stnt1w {z5\.s, z13\.s}, pn14, \[x15, x24, lsl #2\]
+[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c009 stnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c00a stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c00b stnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c018 stnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c019 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c01a stnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121c01b stnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
+[^:]+: a121dc08 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0, x1, lsl #2\]
+[^:]+: a121c3c8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30, x1, lsl #2\]
+[^:]+: a121c3e8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp, x1, lsl #2\]
+[^:]+: a13ec008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x30, lsl #2\]
+[^:]+: a13fc008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, xzr, lsl #2\]
+[^:]+: a126cc99 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11, \[x4, x6, lsl #2\]
--- /dev/null
+ ld1w { z0.s - z1.s }, pn8/z, [x0]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S - Z1.S }, PN8/Z, [X0]
+ ld1w { z30.s - z31.s }, pn8/z, [x0]
+ ld1w { z0.s - z1.s }, pn15/z, [x0]
+ ld1w { z0.s - z1.s }, pn8/z, [x30]
+ ld1w { z0.s - z1.s }, pn8/z, [sp]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
+ ld1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
+
+ ld1w { z0.s - z3.s }, pn8/z, [x0]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S - Z3.S }, PN8/Z, [X0]
+ ld1w { z28.s - z31.s }, pn8/z, [x0]
+ ld1w { z0.s - z3.s }, pn15/z, [x0]
+ ld1w { z0.s - z3.s }, pn8/z, [x30]
+ ld1w { z0.s - z3.s }, pn8/z, [sp]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
+ ld1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
+
+ ld1w { z0.s, z8.s }, pn8/z, [x0]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S, Z8.S }, PN8/Z, [X0]
+ ld1w { z1.s, z9.s }, pn8/z, [x0]
+ ld1w { z2.s, z10.s }, pn8/z, [x0]
+ ld1w { z3.s, z11.s }, pn8/z, [x0]
+ ld1w { z4.s, z12.s }, pn8/z, [x0]
+ ld1w { z5.s, z13.s }, pn8/z, [x0]
+ ld1w { z6.s, z14.s }, pn8/z, [x0]
+ ld1w { z7.s, z15.s }, pn8/z, [x0]
+ ld1w { z16.s, z24.s }, pn8/z, [x0]
+ ld1w { z17.s, z25.s }, pn8/z, [x0]
+ ld1w { z18.s, z26.s }, pn8/z, [x0]
+ ld1w { z19.s, z27.s }, pn8/z, [x0]
+ ld1w { z20.s, z28.s }, pn8/z, [x0]
+ ld1w { z21.s, z29.s }, pn8/z, [x0]
+ ld1w { z22.s, z30.s }, pn8/z, [x0]
+ ld1w { z23.s, z31.s }, pn8/z, [x0]
+ ld1w { z0.s, z8.s }, pn15/z, [x0]
+ ld1w { z0.s, z8.s }, pn8/z, [x30]
+ ld1w { z0.s, z8.s }, pn8/z, [sp]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, #-16, mul vl]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, #14, mul vl]
+ ld1w { z3.s, z11.s }, pn10/z, [x22, #6, mul vl]
+
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #0, mul vl]
+ LD1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0]
+ ld1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0]
+ ld1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0]
+ ld1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0]
+ ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0]
+ ld1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0]
+ ld1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0]
+ ld1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #-32, mul vl]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #28, mul vl]
+ ld1w { z2.s, z6.s, z10.s, z14.s }, pn14/z, [x29, #8, mul vl]
+
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
+
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
+
+ ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S, Z8.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z1.s, z9.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z2.s, z10.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z3.s, z11.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z4.s, z12.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z5.s, z13.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z6.s, z14.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z7.s, z15.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z16.s, z24.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z17.s, z25.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z18.s, z26.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z19.s, z27.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z20.s, z28.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z21.s, z29.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z22.s, z30.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z23.s, z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z8.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s, z8.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z5.s, z13.s }, pn14/z, [x15, x24, lsl #2]
+
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl 2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #2]
+ LD1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0, X1, LSL #2]
+ ld1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp, x1, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x30, lsl #2]
+ ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, xzr, lsl #2]
+ ld1w { z17.s, z21.s, z25.s, z29.s }, pn11/z, [x4, x6, lsl #2]
+
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0]
+ ldnt1w { z30.s - z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn15/z, [x0]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x30]
+ ldnt1w { z0.s - z1.s }, pn8/z, [sp]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
+ ldnt1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
+
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0]
+ ldnt1w { z28.s - z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn15/z, [x0]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x30]
+ ldnt1w { z0.s - z3.s }, pn8/z, [sp]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
+ ldnt1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
+
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S, Z8.S }, PN8/Z, [X0]
+ ldnt1w { z1.s, z9.s }, pn8/z, [x0]
+ ldnt1w { z2.s, z10.s }, pn8/z, [x0]
+ ldnt1w { z3.s, z11.s }, pn8/z, [x0]
+ ldnt1w { z4.s, z12.s }, pn8/z, [x0]
+ ldnt1w { z5.s, z13.s }, pn8/z, [x0]
+ ldnt1w { z6.s, z14.s }, pn8/z, [x0]
+ ldnt1w { z7.s, z15.s }, pn8/z, [x0]
+ ldnt1w { z16.s, z24.s }, pn8/z, [x0]
+ ldnt1w { z17.s, z25.s }, pn8/z, [x0]
+ ldnt1w { z18.s, z26.s }, pn8/z, [x0]
+ ldnt1w { z19.s, z27.s }, pn8/z, [x0]
+ ldnt1w { z20.s, z28.s }, pn8/z, [x0]
+ ldnt1w { z21.s, z29.s }, pn8/z, [x0]
+ ldnt1w { z22.s, z30.s }, pn8/z, [x0]
+ ldnt1w { z23.s, z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s, z8.s }, pn15/z, [x0]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x30]
+ ldnt1w { z0.s, z8.s }, pn8/z, [sp]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, #-16, mul vl]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, #14, mul vl]
+ ldnt1w { z3.s, z11.s }, pn10/z, [x22, #6, mul vl]
+
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #0, mul vl]
+ LDNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0]
+ ldnt1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0]
+ ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0]
+ ldnt1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0]
+ ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0]
+ ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0]
+ ldnt1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0]
+ ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #-32, mul vl]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #28, mul vl]
+ ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn14/z, [x29, #8, mul vl]
+
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
+
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
+
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S, Z8.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z1.s, z9.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z2.s, z10.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z3.s, z11.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z4.s, z12.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z5.s, z13.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z6.s, z14.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z7.s, z15.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z16.s, z24.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z17.s, z25.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z18.s, z26.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z19.s, z27.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z20.s, z28.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z21.s, z29.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z22.s, z30.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z23.s, z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s, z8.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s, z8.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s, z8.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z5.s, z13.s }, pn14/z, [x15, x24, lsl #2]
+
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl 2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #2]
+ LDNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0, X1, LSL #2]
+ ldnt1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0, x1, lsl #2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30, x1, lsl #2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp, x1, lsl #2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x30, lsl #2]
+ ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, xzr, lsl #2]
+ ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn11/z, [x4, x6, lsl #2]
+
+ st1w { z0.s - z1.s }, pn8, [x0]
+ st1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S - Z1.S }, PN8, [X0]
+ st1w { z30.s - z31.s }, pn8, [x0]
+ st1w { z0.s - z1.s }, pn15, [x0]
+ st1w { z0.s - z1.s }, pn8, [x30]
+ st1w { z0.s - z1.s }, pn8, [sp]
+ st1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
+ st1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
+ st1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
+
+ st1w { z0.s - z3.s }, pn8, [x0]
+ st1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S - Z3.S }, PN8, [X0]
+ st1w { z28.s - z31.s }, pn8, [x0]
+ st1w { z0.s - z3.s }, pn15, [x0]
+ st1w { z0.s - z3.s }, pn8, [x30]
+ st1w { z0.s - z3.s }, pn8, [sp]
+ st1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
+ st1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
+ st1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
+
+ st1w { z0.s, z8.s }, pn8, [x0]
+ st1w { z0.s, z8.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S, Z8.S }, PN8, [X0]
+ st1w { z1.s, z9.s }, pn8, [x0]
+ st1w { z2.s, z10.s }, pn8, [x0]
+ st1w { z3.s, z11.s }, pn8, [x0]
+ st1w { z4.s, z12.s }, pn8, [x0]
+ st1w { z5.s, z13.s }, pn8, [x0]
+ st1w { z6.s, z14.s }, pn8, [x0]
+ st1w { z7.s, z15.s }, pn8, [x0]
+ st1w { z16.s, z24.s }, pn8, [x0]
+ st1w { z17.s, z25.s }, pn8, [x0]
+ st1w { z18.s, z26.s }, pn8, [x0]
+ st1w { z19.s, z27.s }, pn8, [x0]
+ st1w { z20.s, z28.s }, pn8, [x0]
+ st1w { z21.s, z29.s }, pn8, [x0]
+ st1w { z22.s, z30.s }, pn8, [x0]
+ st1w { z23.s, z31.s }, pn8, [x0]
+ st1w { z0.s, z8.s }, pn15, [x0]
+ st1w { z0.s, z8.s }, pn8, [x30]
+ st1w { z0.s, z8.s }, pn8, [sp]
+ st1w { z0.s, z8.s }, pn8, [x0, #-16, mul vl]
+ st1w { z0.s, z8.s }, pn8, [x0, #14, mul vl]
+ st1w { z3.s, z11.s }, pn10, [x22, #6, mul vl]
+
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #0, mul vl]
+ ST1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0]
+ st1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0]
+ st1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0]
+ st1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0]
+ st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0]
+ st1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0]
+ st1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0]
+ st1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #-32, mul vl]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #28, mul vl]
+ st1w { z2.s, z6.s, z10.s, z14.s }, pn14, [x29, #8, mul vl]
+
+ st1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
+ st1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
+
+ st1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
+ st1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
+
+ st1w { z0.s, z8.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s, z8.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S, Z8.S }, PN8, [X0, X1, LSL #2]
+ st1w { z1.s, z9.s }, pn8, [x0, x1, lsl #2]
+ st1w { z2.s, z10.s }, pn8, [x0, x1, lsl #2]
+ st1w { z3.s, z11.s }, pn8, [x0, x1, lsl #2]
+ st1w { z4.s, z12.s }, pn8, [x0, x1, lsl #2]
+ st1w { z5.s, z13.s }, pn8, [x0, x1, lsl #2]
+ st1w { z6.s, z14.s }, pn8, [x0, x1, lsl #2]
+ st1w { z7.s, z15.s }, pn8, [x0, x1, lsl #2]
+ st1w { z16.s, z24.s }, pn8, [x0, x1, lsl #2]
+ st1w { z17.s, z25.s }, pn8, [x0, x1, lsl #2]
+ st1w { z18.s, z26.s }, pn8, [x0, x1, lsl #2]
+ st1w { z19.s, z27.s }, pn8, [x0, x1, lsl #2]
+ st1w { z20.s, z28.s }, pn8, [x0, x1, lsl #2]
+ st1w { z21.s, z29.s }, pn8, [x0, x1, lsl #2]
+ st1w { z22.s, z30.s }, pn8, [x0, x1, lsl #2]
+ st1w { z23.s, z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s, z8.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s, z8.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s, z8.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s, z8.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s, z8.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z5.s, z13.s }, pn14, [x15, x24, lsl #2]
+
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl 2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl #2]
+ ST1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0, X1, LSL #2]
+ st1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0, x1, lsl #2]
+ st1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0, x1, lsl #2]
+ st1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0, x1, lsl #2]
+ st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0, x1, lsl #2]
+ st1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0, x1, lsl #2]
+ st1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0, x1, lsl #2]
+ st1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0, x1, lsl #2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0, x1, lsl #2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30, x1, lsl #2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp, x1, lsl #2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x30, lsl #2]
+ st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, xzr, lsl #2]
+ st1w { z17.s, z21.s, z25.s, z29.s }, pn11, [x4, x6, lsl #2]
+
+ stnt1w { z0.s - z1.s }, pn8, [x0]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S - Z1.S }, PN8, [X0]
+ stnt1w { z30.s - z31.s }, pn8, [x0]
+ stnt1w { z0.s - z1.s }, pn15, [x0]
+ stnt1w { z0.s - z1.s }, pn8, [x30]
+ stnt1w { z0.s - z1.s }, pn8, [sp]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
+ stnt1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
+ stnt1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
+
+ stnt1w { z0.s - z3.s }, pn8, [x0]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S - Z3.S }, PN8, [X0]
+ stnt1w { z28.s - z31.s }, pn8, [x0]
+ stnt1w { z0.s - z3.s }, pn15, [x0]
+ stnt1w { z0.s - z3.s }, pn8, [x30]
+ stnt1w { z0.s - z3.s }, pn8, [sp]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
+ stnt1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
+ stnt1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
+
+ stnt1w { z0.s, z8.s }, pn8, [x0]
+ stnt1w { z0.s, z8.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S, Z8.S }, PN8, [X0]
+ stnt1w { z1.s, z9.s }, pn8, [x0]
+ stnt1w { z2.s, z10.s }, pn8, [x0]
+ stnt1w { z3.s, z11.s }, pn8, [x0]
+ stnt1w { z4.s, z12.s }, pn8, [x0]
+ stnt1w { z5.s, z13.s }, pn8, [x0]
+ stnt1w { z6.s, z14.s }, pn8, [x0]
+ stnt1w { z7.s, z15.s }, pn8, [x0]
+ stnt1w { z16.s, z24.s }, pn8, [x0]
+ stnt1w { z17.s, z25.s }, pn8, [x0]
+ stnt1w { z18.s, z26.s }, pn8, [x0]
+ stnt1w { z19.s, z27.s }, pn8, [x0]
+ stnt1w { z20.s, z28.s }, pn8, [x0]
+ stnt1w { z21.s, z29.s }, pn8, [x0]
+ stnt1w { z22.s, z30.s }, pn8, [x0]
+ stnt1w { z23.s, z31.s }, pn8, [x0]
+ stnt1w { z0.s, z8.s }, pn15, [x0]
+ stnt1w { z0.s, z8.s }, pn8, [x30]
+ stnt1w { z0.s, z8.s }, pn8, [sp]
+ stnt1w { z0.s, z8.s }, pn8, [x0, #-16, mul vl]
+ stnt1w { z0.s, z8.s }, pn8, [x0, #14, mul vl]
+ stnt1w { z3.s, z11.s }, pn10, [x22, #6, mul vl]
+
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #0, mul vl]
+ STNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0]
+ stnt1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0]
+ stnt1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0]
+ stnt1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0]
+ stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0]
+ stnt1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0]
+ stnt1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0]
+ stnt1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #-32, mul vl]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #28, mul vl]
+ stnt1w { z2.s, z6.s, z10.s, z14.s }, pn14, [x29, #8, mul vl]
+
+ stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
+
+ stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
+
+ stnt1w { z0.s, z8.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s, z8.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S, Z8.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z1.s, z9.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z2.s, z10.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z3.s, z11.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z4.s, z12.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z5.s, z13.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z6.s, z14.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z7.s, z15.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z16.s, z24.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z17.s, z25.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z18.s, z26.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z19.s, z27.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z20.s, z28.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z21.s, z29.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z22.s, z30.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z23.s, z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s, z8.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s, z8.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s, z8.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s, z8.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s, z8.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z5.s, z13.s }, pn14, [x15, x24, lsl #2]
+
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl 2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl #2]
+ STNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0, X1, LSL #2]
+ stnt1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0, x1, lsl #2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0, x1, lsl #2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30, x1, lsl #2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp, x1, lsl #2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x30, lsl #2]
+ stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, xzr, lsl #2]
+ stnt1w { z17.s, z21.s, z25.s, z29.s }, pn11, [x4, x6, lsl #2]
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
+ AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
+ AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
+ AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
case 203:
case 209:
case 212:
- case 218:
- case 219:
- case 224:
+ case 220:
+ case 221:
+ case 226:
+ case 227:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 234:
+ case 237:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 225:
- case 233:
- case 238:
- case 239:
+ case 228:
+ case 236:
+ case 241:
+ case 242:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
case 216:
case 217:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
- case 220:
+ case 218:
+ case 219:
+ return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 222:
- case 226:
+ case 224:
+ case 229:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 221:
case 223:
+ case 225:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 227:
- case 228:
- case 229:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 230:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 231:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 232:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
+ case 233:
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 234:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 235:
- case 236:
- case 237:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 238:
+ case 239:
+ case 240:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- insert_field (self->fields[0], code, info->reg.regno, 0);
+ int val = info->reg.regno - get_operand_specific_data (self);
+ insert_field (self->fields[0], code, val, 0);
return true;
}
return true;
}
+/* Encode a strided register list. The first field holds the top bit
+ (0 or 16) and the second field holds the lower bits. The stride is
+ 16 divided by the list length. */
+bool
+aarch64_ins_sve_strided_reglist (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors
+ ATTRIBUTE_UNUSED)
+{
+ unsigned int num_regs = get_operand_specific_data (self);
+ unsigned int mask = 16 | (16 / num_regs - 1);
+ unsigned int val = info->reglist.first_regno;
+ assert ((val & mask) == val);
+ insert_field (self->fields[0], code, val >> 4, 0);
+ insert_field (self->fields[1], code, val & 15, 0);
+ return true;
+}
+
/* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
field. */
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
+AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
10987654321098765432109876543210
x1000000xx0xx10xxxxx00xxxxxxxxxx
mov. */
- return 2426;
+ return 2490;
}
else
{
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
mov. */
- return 2424;
+ return 2488;
}
}
else
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
mov. */
- return 2427;
+ return 2491;
}
else
{
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
mov. */
- return 2425;
+ return 2489;
}
}
}
10987654321098765432109876543210
x1000000xx0xx11xxxxx00xxxxxxxxxx
mov. */
- return 2422;
+ return 2486;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx10xxxxxxxxxx
mov. */
- return 2420;
+ return 2484;
}
}
else
10987654321098765432109876543210
x1000000xx0xx11xxxxx01xxxxxxxxxx
mov. */
- return 2423;
+ return 2487;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx11xxxxxxxxxx
mov. */
- return 2421;
+ return 2485;
}
}
}
}
else
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100000000xxxxxxxxxxxxxxxx0xxxx
- ld1b. */
- return 2393;
- }
- else
+ if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 0) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0100000100xxxxxxxxxxxxxxxx0xxxx
- smopa. */
- return 2372;
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx000xxxxxxxxxxxx0
+ ld1b. */
+ return 2424;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx100xxxxxxxxxxxx0
+ ld1b. */
+ return 2425;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx010xxxxxxxxxxxx0
+ ld1w. */
+ return 2448;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx110xxxxxxxxxxxx0
+ ld1w. */
+ return 2449;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx001xxxxxxxxxxxx0
+ ld1h. */
+ return 2440;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx101xxxxxxxxxxxx0
+ ld1h. */
+ return 2441;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx011xxxxxxxxxxxx0
+ ld1d. */
+ return 2432;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx111xxxxxxxxxxxx0
+ ld1d. */
+ return 2433;
+ }
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1100000100xxxxxxxxxxxxxxxx0xxxx
- ld1w. */
- return 2395;
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx000xxxxxxxxxxxx1
+ ldnt1b. */
+ return 2456;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx100xxxxxxxxxxxx1
+ ldnt1b. */
+ return 2457;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx010xxxxxxxxxxxx1
+ ldnt1w. */
+ return 2480;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx110xxxxxxxxxxxx1
+ ldnt1w. */
+ return 2481;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx001xxxxxxxxxxxx1
+ ldnt1h. */
+ return 2472;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx101xxxxxxxxxxxx1
+ ldnt1h. */
+ return 2473;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx011xxxxxxxxxxxx1
+ ldnt1d. */
+ return 2464;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000000xxxxx111xxxxxxxxxxxx1
+ ldnt1d. */
+ return 2465;
+ }
+ }
+ }
}
}
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
+ else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx100000010xxxxxxxxxxxxxxxx0xxxx
- ld1h. */
- return 2394;
+ x1100000000xxxxxxxxxxxxxxxxxxxxx
+ ld1b. */
+ return 2393;
}
- else
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
{
if (((word >> 30) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0100000110xxxxxxxxxxxxxxxx0xxxx
+ x0100000100xxxxxxxxxxxxxxxx0xxxx
smopa. */
- return 2373;
+ return 2372;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1100000110xxxxxxxxxxxxxxxx0xxxx
- ld1d. */
- return 2396;
+ x1100000100xxxxxxxxxxxxxxxx0xxxx
+ ld1w. */
+ return 2395;
}
}
- }
- }
- else
- {
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100000x00xxxxxxxxxxxxxxxx1xxxx
- smops. */
- return 2374;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100000x10xxxxxxxxxxxxxxxx1xxxx
- smops. */
- return 2375;
- }
- }
- }
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000001xxxxxxxxxxxxxxxx0xxxx
- st1b. */
- return 2403;
- }
- else
- {
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00000101xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2376;
- }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x00000101xxxxxxxxxxxxxxxx0xxxx
- st1w. */
- return 2405;
+ xx100000100xxxxxxxxxxxxxxxx1xxxx
+ smops. */
+ return 2374;
}
}
}
else
{
if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000011xxxxxxxxxxxxxxxx0xxxx
- st1h. */
- return 2404;
- }
- else
{
if (((word >> 30) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00000111xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2377;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00000111xxxxxxxxxxxxxxxx0xxxx
- st1d. */
- return 2406;
- }
- }
- }
- }
- else
- {
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000x01xxxxxxxxxxxxxxxx1xxxx
- sumops. */
- return 2378;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00000x11xxxxxxxxxxxxxxxx1xxxx
- sumops. */
- return 2379;
- }
- }
- }
- }
- else
- {
- if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0xx10000xxxxxxxxxxxxxxxxxxxxxxxx
- adr. */
- return 1191;
+ if (((word >> 0) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx000xxxxxxxxxxxx0
+ ld1b. */
+ return 2420;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx100xxxxxxxxxxxx0
+ ld1b. */
+ return 2421;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx010xxxxxxxxxxxx0
+ ld1w. */
+ return 2444;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx110xxxxxxxxxxxx0
+ ld1w. */
+ return 2445;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx001xxxxxxxxxxxx0
+ ld1h. */
+ return 2436;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx101xxxxxxxxxxxx0
+ ld1h. */
+ return 2437;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx011xxxxxxxxxxxx0
+ ld1d. */
+ return 2428;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx111xxxxxxxxxxxx0
+ ld1d. */
+ return 2429;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx000xxxxxxxxxxxx1
+ ldnt1b. */
+ return 2452;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx100xxxxxxxxxxxx1
+ ldnt1b. */
+ return 2453;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx010xxxxxxxxxxxx1
+ ldnt1w. */
+ return 2476;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx110xxxxxxxxxxxx1
+ ldnt1w. */
+ return 2477;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx001xxxxxxxxxxxx1
+ ldnt1h. */
+ return 2468;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx101xxxxxxxxxxxx1
+ ldnt1h. */
+ return 2469;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx011xxxxxxxxxxxx1
+ ldnt1d. */
+ return 2460;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000010xxxxx111xxxxxxxxxxxx1
+ ldnt1d. */
+ return 2461;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000010xxxxxxxxxxxxxxxxxxxxx
+ ld1h. */
+ return 2394;
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000110xxxxxxxxxxxxxxxx0xxxx
+ smopa. */
+ return 2373;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000110xxxxxxxxxxxxxxxx0xxxx
+ ld1d. */
+ return 2396;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100000110xxxxxxxxxxxxxxxx1xxxx
+ smops. */
+ return 2375;
+ }
+ }
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 1xx10000xxxxxxxxxxxxxxxxxxxxxxxx
- adrp. */
- return 1192;
- }
- }
- }
- else
- {
- if (((word >> 28) & 0x1) == 0)
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 21) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001000xxxxxxxxxxxxxxxx0xxxx
- ldr. */
- return 2413;
+ if (((word >> 0) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx000xxxxxxxxxxxx0
+ st1b. */
+ return 2504;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx100xxxxxxxxxxxx0
+ st1b. */
+ return 2505;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx010xxxxxxxxxxxx0
+ st1w. */
+ return 2528;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx110xxxxxxxxxxxx0
+ st1w. */
+ return 2529;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx001xxxxxxxxxxxx0
+ st1h. */
+ return 2520;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx101xxxxxxxxxxxx0
+ st1h. */
+ return 2521;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx011xxxxxxxxxxxx0
+ st1d. */
+ return 2512;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx111xxxxxxxxxxxx0
+ st1d. */
+ return 2513;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx000xxxxxxxxxxxx1
+ stnt1b. */
+ return 2536;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx100xxxxxxxxxxxx1
+ stnt1b. */
+ return 2537;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx010xxxxxxxxxxxx1
+ stnt1w. */
+ return 2560;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx110xxxxxxxxxxxx1
+ stnt1w. */
+ return 2561;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx001xxxxxxxxxxxx1
+ stnt1h. */
+ return 2552;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx101xxxxxxxxxxxx1
+ stnt1h. */
+ return 2553;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx011xxxxxxxxxxxx1
+ stnt1d. */
+ return 2544;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000001xxxxx111xxxxxxxxxxxx1
+ stnt1d. */
+ return 2545;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000001xxxxxxxxxxxxxxxxxxxxx
+ st1b. */
+ return 2403;
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000101xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2376;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000101xxxxxxxxxxxxxxxx0xxxx
+ st1w. */
+ return 2405;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00000101xxxxxxxxxxxxxxxx1xxxx
+ sumops. */
+ return 2378;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx000xxxxxxxxxxxx0
+ st1b. */
+ return 2500;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx100xxxxxxxxxxxx0
+ st1b. */
+ return 2501;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx010xxxxxxxxxxxx0
+ st1w. */
+ return 2524;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx110xxxxxxxxxxxx0
+ st1w. */
+ return 2525;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx001xxxxxxxxxxxx0
+ st1h. */
+ return 2516;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx101xxxxxxxxxxxx0
+ st1h. */
+ return 2517;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx011xxxxxxxxxxxx0
+ st1d. */
+ return 2508;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx111xxxxxxxxxxxx0
+ st1d. */
+ return 2509;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx000xxxxxxxxxxxx1
+ stnt1b. */
+ return 2532;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx100xxxxxxxxxxxx1
+ stnt1b. */
+ return 2533;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx010xxxxxxxxxxxx1
+ stnt1w. */
+ return 2556;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx110xxxxxxxxxxxx1
+ stnt1w. */
+ return 2557;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx001xxxxxxxxxxxx1
+ stnt1h. */
+ return 2548;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx101xxxxxxxxxxxx1
+ stnt1h. */
+ return 2549;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx011xxxxxxxxxxxx1
+ stnt1d. */
+ return 2540;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000011xxxxx111xxxxxxxxxxxx1
+ stnt1d. */
+ return 2541;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000011xxxxxxxxxxxxxxxxxxxxx
+ st1h. */
+ return 2404;
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00000111xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2377;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00000111xxxxxxxxxxxxxxxx0xxxx
+ st1d. */
+ return 2406;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00000111xxxxxxxxxxxxxxxx1xxxx
+ sumops. */
+ return 2379;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 31) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0xx10000xxxxxxxxxxxxxxxxxxxxxxxx
+ adr. */
+ return 1191;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 1xx10000xxxxxxxxxxxxxxxxxxxxxxxx
+ adrp. */
+ return 1192;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 28) & 0x1) == 0)
+ {
+ if (((word >> 21) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx000xxxxxxxxx0xxx
+ ld1b. */
+ return 2426;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx010xxxxxxxxx0xxx
+ ld1w. */
+ return 2450;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx001xxxxxxxxx0xxx
+ ld1h. */
+ return 2442;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx011xxxxxxxxx0xxx
+ ld1d. */
+ return 2434;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx000xxxxxxxxx1xxx
+ ldnt1b. */
+ return 2458;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx010xxxxxxxxx1xxx
+ ldnt1w. */
+ return 2482;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx001xxxxxxxxx1xxx
+ ldnt1h. */
+ return 2474;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001000xxxxx011xxxxxxxxx1xxx
+ ldnt1d. */
+ return 2466;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001000xxxxx0xxxxxxxxxxxxxxx
+ ldr. */
+ return 2413;
+ }
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx100xxxxxxxxx0xxx
+ ld1b. */
+ return 2427;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx110xxxxxxxxx0xxx
+ ld1w. */
+ return 2451;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx101xxxxxxxxx0xxx
+ ld1h. */
+ return 2443;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx111xxxxxxxxx0xxx
+ ld1d. */
+ return 2435;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx100xxxxxxxxx1xxx
+ ldnt1b. */
+ return 2459;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx110xxxxxxxxx1xxx
+ ldnt1w. */
+ return 2483;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx101xxxxxxxxx1xxx
+ ldnt1h. */
+ return 2475;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001000xxxxx111xxxxxxxxx1xxx
+ ldnt1d. */
+ return 2467;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001100xxxxxxxxxxxxxxxx0xxxx
+ bfmopa. */
+ return 2363;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001100xxxxxxxxxxxxxxxx0xxxx
+ usmopa. */
+ return 2384;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001100xxxxxxxxxxxxxxxx1xxxx
+ bfmops. */
+ return 2364;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001100xxxxxxxxxxxxxxxx1xxxx
+ usmops. */
+ return 2386;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx000xxxxxxxxx0xxx
+ ld1b. */
+ return 2422;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx100xxxxxxxxx0xxx
+ ld1b. */
+ return 2423;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx010xxxxxxxxx0xxx
+ ld1w. */
+ return 2446;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx110xxxxxxxxx0xxx
+ ld1w. */
+ return 2447;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx001xxxxxxxxx0xxx
+ ld1h. */
+ return 2438;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx101xxxxxxxxx0xxx
+ ld1h. */
+ return 2439;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx011xxxxxxxxx0xxx
+ ld1d. */
+ return 2430;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx111xxxxxxxxx0xxx
+ ld1d. */
+ return 2431;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx000xxxxxxxxx1xxx
+ ldnt1b. */
+ return 2454;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx100xxxxxxxxx1xxx
+ ldnt1b. */
+ return 2455;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx010xxxxxxxxx1xxx
+ ldnt1w. */
+ return 2478;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx110xxxxxxxxx1xxx
+ ldnt1w. */
+ return 2479;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx001xxxxxxxxx1xxx
+ ldnt1h. */
+ return 2470;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx101xxxxxxxxx1xxx
+ ldnt1h. */
+ return 2471;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx011xxxxxxxxx1xxx
+ ldnt1d. */
+ return 2462;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001010xxxxx111xxxxxxxxx1xxx
+ ldnt1d. */
+ return 2463;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001110xxxxxxxxxxxxxxxx0xxxx
+ usmopa. */
+ return 2385;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001110xxxxxxxxxxxxxxxx0xxxx
+ ld1q. */
+ return 2397;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001110xxxxxxxxxxxxxxxx1xxxx
+ usmops. */
+ return 2387;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx000xxxxxxxxx0xxx
+ st1b. */
+ return 2506;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx010xxxxxxxxx0xxx
+ st1w. */
+ return 2530;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx001xxxxxxxxx0xxx
+ st1h. */
+ return 2522;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx011xxxxxxxxx0xxx
+ st1d. */
+ return 2514;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx000xxxxxxxxx1xxx
+ stnt1b. */
+ return 2538;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx010xxxxxxxxx1xxx
+ stnt1w. */
+ return 2562;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx001xxxxxxxxx1xxx
+ stnt1h. */
+ return 2554;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0x00001001xxxxx011xxxxxxxxx1xxx
+ stnt1d. */
+ return 2546;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1x00001001xxxxx0xxxxxxxxxxxxxxx
+ str. */
+ return 2414;
+ }
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx100xxxxxxxxx0xxx
+ st1b. */
+ return 2507;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx110xxxxxxxxx0xxx
+ st1w. */
+ return 2531;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx101xxxxxxxxx0xxx
+ st1h. */
+ return 2523;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx111xxxxxxxxx0xxx
+ st1d. */
+ return 2515;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx100xxxxxxxxx1xxx
+ stnt1b. */
+ return 2539;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx110xxxxxxxxx1xxx
+ stnt1w. */
+ return 2563;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx101xxxxxxxxx1xxx
+ stnt1h. */
+ return 2555;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001001xxxxx111xxxxxxxxx1xxx
+ stnt1d. */
+ return 2547;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 4) & 0x1) == 0)
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001101xxxxxxxxxxxxxxxx0xxxx
+ fmopa. */
+ return 2367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001101xxxxxxxxxxxxxxxx0xxxx
+ umopa. */
+ return 2380;
+ }
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001101xxxxxxxxxxxxxxxx1xxxx
+ fmops. */
+ return 2370;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001101xxxxxxxxxxxxxxxx1xxxx
+ umops. */
+ return 2382;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx000xxxxxxxxx0xxx
+ st1b. */
+ return 2502;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx100xxxxxxxxx0xxx
+ st1b. */
+ return 2503;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx010xxxxxxxxx0xxx
+ st1w. */
+ return 2526;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx110xxxxxxxxx0xxx
+ st1w. */
+ return 2527;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx001xxxxxxxxx0xxx
+ st1h. */
+ return 2518;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx101xxxxxxxxx0xxx
+ st1h. */
+ return 2519;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx011xxxxxxxxx0xxx
+ st1d. */
+ return 2510;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx111xxxxxxxxx0xxx
+ st1d. */
+ return 2511;
+ }
+ }
+ }
}
else
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001100xxxxxxxxxxxxxxxx0xxxx
- bfmopa. */
- return 2363;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx000xxxxxxxxx1xxx
+ stnt1b. */
+ return 2534;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx100xxxxxxxxx1xxx
+ stnt1b. */
+ return 2535;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx010xxxxxxxxx1xxx
+ stnt1w. */
+ return 2558;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx110xxxxxxxxx1xxx
+ stnt1w. */
+ return 2559;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001100xxxxxxxxxxxxxxxx0xxxx
- usmopa. */
- return 2384;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx001xxxxxxxxx1xxx
+ stnt1h. */
+ return 2550;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx101xxxxxxxxx1xxx
+ stnt1h. */
+ return 2551;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx011xxxxxxxxx1xxx
+ stnt1d. */
+ return 2542;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx00001011xxxxx111xxxxxxxxx1xxx
+ stnt1d. */
+ return 2543;
+ }
+ }
}
}
}
else
{
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00001x10xxxxxxxxxxxxxxxx0xxxx
- usmopa. */
- return 2385;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00001x10xxxxxxxxxxxxxxxx0xxxx
- ld1q. */
- return 2397;
- }
- }
- }
- else
- {
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxxxxxxxxxxxxx0xxxx
- str. */
- return 2414;
- }
- else
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001101xxxxxxxxxxxxxxxx0xxxx
- fmopa. */
- return 2367;
+ x0x00001111xxxxxxxxxxxxxxxx0xxxx
+ umopa. */
+ return 2381;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx100001101xxxxxxxxxxxxxxxx0xxxx
- umopa. */
- return 2380;
+ x1x00001111xxxxxxxxxxxxxxxx0xxxx
+ st1q. */
+ return 2407;
}
}
- }
- else
- {
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00001x11xxxxxxxxxxxxxxxx0xxxx
- umopa. */
- return 2381;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00001x11xxxxxxxxxxxxxxxx0xxxx
- st1q. */
- return 2407;
- }
- }
- }
- }
- else
- {
- if (((word >> 21) & 0x1) == 0)
- {
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001x00xxxxxxxxxxxxxxxx1xxxx
- bfmops. */
- return 2364;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001x00xxxxxxxxxxxxxxxx1xxxx
- usmops. */
- return 2386;
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001x10xxxxxxxxxxxxxxxx1xxxx
- usmops. */
- return 2387;
- }
- }
- else
- {
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001x01xxxxxxxxxxxxxxxx1xxxx
- fmops. */
- return 2370;
- }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx100001x01xxxxxxxxxxxxxxxx1xxxx
+ xxx00001111xxxxxxxxxxxxxxxx1xxxx
umops. */
- return 2382;
+ return 2383;
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001x11xxxxxxxxxxxxxxxx1xxxx
- umops. */
- return 2383;
- }
}
}
}
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2476;
+ return 2604;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2484;
+ return 2612;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2480;
+ return 2608;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2487;
+ return 2615;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0000x1xxxxxxxxxx
cpyfp. */
- return 2536;
+ return 2664;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1000x1xxxxxxxxxx
cpyfprn. */
- return 2542;
+ return 2670;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0100x1xxxxxxxxxx
cpyfpwn. */
- return 2539;
+ return 2667;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1100x1xxxxxxxxxx
cpyfpn. */
- return 2545;
+ return 2673;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0010x1xxxxxxxxxx
cpyfprt. */
- return 2560;
+ return 2688;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1010x1xxxxxxxxxx
cpyfprtrn. */
- return 2566;
+ return 2694;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0110x1xxxxxxxxxx
cpyfprtwn. */
- return 2563;
+ return 2691;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1110x1xxxxxxxxxx
cpyfprtn. */
- return 2569;
+ return 2697;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0001x1xxxxxxxxxx
cpyfpwt. */
- return 2548;
+ return 2676;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1001x1xxxxxxxxxx
cpyfpwtrn. */
- return 2554;
+ return 2682;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0101x1xxxxxxxxxx
cpyfpwtwn. */
- return 2551;
+ return 2679;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1101x1xxxxxxxxxx
cpyfpwtn. */
- return 2557;
+ return 2685;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0011x1xxxxxxxxxx
cpyfpt. */
- return 2572;
+ return 2700;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1011x1xxxxxxxxxx
cpyfptrn. */
- return 2578;
+ return 2706;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0111x1xxxxxxxxxx
cpyfptwn. */
- return 2575;
+ return 2703;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1111x1xxxxxxxxxx
cpyfptn. */
- return 2581;
+ return 2709;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2477;
+ return 2605;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2485;
+ return 2613;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2481;
+ return 2609;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2488;
+ return 2616;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0000x1xxxxxxxxxx
cpyfm. */
- return 2537;
+ return 2665;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1000x1xxxxxxxxxx
cpyfmrn. */
- return 2543;
+ return 2671;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0100x1xxxxxxxxxx
cpyfmwn. */
- return 2540;
+ return 2668;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1100x1xxxxxxxxxx
cpyfmn. */
- return 2546;
+ return 2674;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0010x1xxxxxxxxxx
cpyfmrt. */
- return 2561;
+ return 2689;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1010x1xxxxxxxxxx
cpyfmrtrn. */
- return 2567;
+ return 2695;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0110x1xxxxxxxxxx
cpyfmrtwn. */
- return 2564;
+ return 2692;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1110x1xxxxxxxxxx
cpyfmrtn. */
- return 2570;
+ return 2698;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0001x1xxxxxxxxxx
cpyfmwt. */
- return 2549;
+ return 2677;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1001x1xxxxxxxxxx
cpyfmwtrn. */
- return 2555;
+ return 2683;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0101x1xxxxxxxxxx
cpyfmwtwn. */
- return 2552;
+ return 2680;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1101x1xxxxxxxxxx
cpyfmwtn. */
- return 2558;
+ return 2686;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0011x1xxxxxxxxxx
cpyfmt. */
- return 2573;
+ return 2701;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1011x1xxxxxxxxxx
cpyfmtrn. */
- return 2579;
+ return 2707;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0111x1xxxxxxxxxx
cpyfmtwn. */
- return 2576;
+ return 2704;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1111x1xxxxxxxxxx
cpyfmtn. */
- return 2582;
+ return 2710;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2479;
+ return 2607;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2486;
+ return 2614;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2483;
+ return 2611;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2478;
+ return 2606;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2482;
+ return 2610;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0000x1xxxxxxxxxx
cpyfe. */
- return 2538;
+ return 2666;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0000x1xxxxxxxxxx
setp. */
- return 2632;
+ return 2760;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1000x1xxxxxxxxxx
cpyfern. */
- return 2544;
+ return 2672;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1000x1xxxxxxxxxx
sete. */
- return 2634;
+ return 2762;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0100x1xxxxxxxxxx
cpyfewn. */
- return 2541;
+ return 2669;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0100x1xxxxxxxxxx
setm. */
- return 2633;
+ return 2761;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1100x1xxxxxxxxxx
cpyfen. */
- return 2547;
+ return 2675;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0010x1xxxxxxxxxx
cpyfert. */
- return 2562;
+ return 2690;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0010x1xxxxxxxxxx
setpn. */
- return 2638;
+ return 2766;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1010x1xxxxxxxxxx
cpyfertrn. */
- return 2568;
+ return 2696;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1010x1xxxxxxxxxx
seten. */
- return 2640;
+ return 2768;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0110x1xxxxxxxxxx
cpyfertwn. */
- return 2565;
+ return 2693;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0110x1xxxxxxxxxx
setmn. */
- return 2639;
+ return 2767;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1110x1xxxxxxxxxx
cpyfertn. */
- return 2571;
+ return 2699;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0001x1xxxxxxxxxx
cpyfewt. */
- return 2550;
+ return 2678;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0001x1xxxxxxxxxx
setpt. */
- return 2635;
+ return 2763;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1001x1xxxxxxxxxx
cpyfewtrn. */
- return 2556;
+ return 2684;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1001x1xxxxxxxxxx
setet. */
- return 2637;
+ return 2765;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0101x1xxxxxxxxxx
cpyfewtwn. */
- return 2553;
+ return 2681;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0101x1xxxxxxxxxx
setmt. */
- return 2636;
+ return 2764;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1101x1xxxxxxxxxx
cpyfewtn. */
- return 2559;
+ return 2687;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0011x1xxxxxxxxxx
cpyfet. */
- return 2574;
+ return 2702;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0011x1xxxxxxxxxx
setptn. */
- return 2641;
+ return 2769;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1011x1xxxxxxxxxx
cpyfetrn. */
- return 2580;
+ return 2708;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1011x1xxxxxxxxxx
setetn. */
- return 2643;
+ return 2771;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0111x1xxxxxxxxxx
cpyfetwn. */
- return 2577;
+ return 2705;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0111x1xxxxxxxxxx
setmtn. */
- return 2642;
+ return 2770;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1111x1xxxxxxxxxx
cpyfetn. */
- return 2583;
+ return 2711;
}
}
}
10987654321098765432109876543210
x1x11010110xxxx0x01000xxxxxxxxxx
abs. */
- return 2661;
+ return 2789;
}
else
{
10987654321098765432109876543210
xxx11010110xxxxxx11000xxxxxxxxxx
smax. */
- return 2664;
+ return 2792;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2474;
+ return 2602;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2475;
+ return 2603;
}
}
else
10987654321098765432109876543210
xxx11010110xxxxxx11010xxxxxxxxxx
smin. */
- return 2666;
+ return 2794;
}
}
}
10987654321098765432109876543210
xxx11010110xxxx0x00110xxxxxxxxxx
ctz. */
- return 2663;
+ return 2791;
}
else
{
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2473;
+ return 2601;
}
else
{
10987654321098765432109876543210
xxx11010x10xxxxxx11001xxxxxxxxxx
umax. */
- return 2665;
+ return 2793;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxxxx11011xxxxxxxxxx
umin. */
- return 2667;
+ return 2795;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxx0x00111xxxxxxxxxx
cnt. */
- return 2662;
+ return 2790;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2493;
+ return 2621;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2494;
+ return 2622;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2492;
+ return 2620;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2521;
+ return 2649;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2497;
+ return 2625;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2498;
+ return 2626;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2518;
+ return 2646;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2525;
+ return 2653;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2524;
+ return 2652;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2517;
+ return 2645;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2523;
+ return 2651;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2522;
+ return 2650;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2501;
+ return 2629;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2502;
+ return 2630;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2495;
+ return 2623;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2519;
+ return 2647;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2496;
+ return 2624;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2505;
+ return 2633;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2507;
+ return 2635;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2509;
+ return 2637;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2506;
+ return 2634;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2508;
+ return 2636;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2510;
+ return 2638;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2489;
+ return 2617;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2491;
+ return 2619;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2490;
+ return 2618;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2499;
+ return 2627;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2500;
+ return 2628;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2503;
+ return 2631;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2504;
+ return 2632;
}
}
}
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2520;
+ return 2648;
}
}
else
10987654321098765432109876543210
x1010100xxxxxxxxxxxxxxxxxxx1xxxx
bc.c. */
- return 2656;
+ return 2784;
}
else
{
10987654321098765432109876543210
xx01110100xxxxxx0000xxxxxxxxxxxx
cpyp. */
- return 2584;
+ return 2712;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0000xxxxxxxxxxxx
cpye. */
- return 2586;
+ return 2714;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1000xxxxxxxxxxxx
cpyprn. */
- return 2590;
+ return 2718;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1000xxxxxxxxxxxx
cpyern. */
- return 2592;
+ return 2720;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0100xxxxxxxxxxxx
cpypwn. */
- return 2587;
+ return 2715;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0100xxxxxxxxxxxx
cpyewn. */
- return 2589;
+ return 2717;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1100xxxxxxxxxxxx
cpypn. */
- return 2593;
+ return 2721;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1100xxxxxxxxxxxx
cpyen. */
- return 2595;
+ return 2723;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0010xxxxxxxxxxxx
cpyprt. */
- return 2608;
+ return 2736;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0010xxxxxxxxxxxx
cpyert. */
- return 2610;
+ return 2738;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1010xxxxxxxxxxxx
cpyprtrn. */
- return 2614;
+ return 2742;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1010xxxxxxxxxxxx
cpyertrn. */
- return 2616;
+ return 2744;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0110xxxxxxxxxxxx
cpyprtwn. */
- return 2611;
+ return 2739;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0110xxxxxxxxxxxx
cpyertwn. */
- return 2613;
+ return 2741;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1110xxxxxxxxxxxx
cpyprtn. */
- return 2617;
+ return 2745;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1110xxxxxxxxxxxx
cpyertn. */
- return 2619;
+ return 2747;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0001xxxxxxxxxxxx
cpypwt. */
- return 2596;
+ return 2724;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0001xxxxxxxxxxxx
cpyewt. */
- return 2598;
+ return 2726;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1001xxxxxxxxxxxx
cpypwtrn. */
- return 2602;
+ return 2730;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1001xxxxxxxxxxxx
cpyewtrn. */
- return 2604;
+ return 2732;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0101xxxxxxxxxxxx
cpypwtwn. */
- return 2599;
+ return 2727;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0101xxxxxxxxxxxx
cpyewtwn. */
- return 2601;
+ return 2729;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1101xxxxxxxxxxxx
cpypwtn. */
- return 2605;
+ return 2733;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1101xxxxxxxxxxxx
cpyewtn. */
- return 2607;
+ return 2735;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0011xxxxxxxxxxxx
cpypt. */
- return 2620;
+ return 2748;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0011xxxxxxxxxxxx
cpyet. */
- return 2622;
+ return 2750;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1011xxxxxxxxxxxx
cpyptrn. */
- return 2626;
+ return 2754;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1011xxxxxxxxxxxx
cpyetrn. */
- return 2628;
+ return 2756;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0111xxxxxxxxxxxx
cpyptwn. */
- return 2623;
+ return 2751;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0111xxxxxxxxxxxx
cpyetwn. */
- return 2625;
+ return 2753;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1111xxxxxxxxxxxx
cpyptn. */
- return 2629;
+ return 2757;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1111xxxxxxxxxxxx
cpyetn. */
- return 2631;
+ return 2759;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0000xxxxxxxxxxxx
cpym. */
- return 2585;
+ return 2713;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0000xxxxxxxxxxxx
setgp. */
- return 2644;
+ return 2772;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1000xxxxxxxxxxxx
cpymrn. */
- return 2591;
+ return 2719;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1000xxxxxxxxxxxx
setge. */
- return 2646;
+ return 2774;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0100xxxxxxxxxxxx
cpymwn. */
- return 2588;
+ return 2716;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0100xxxxxxxxxxxx
setgm. */
- return 2645;
+ return 2773;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1100xxxxxxxxxxxx
cpymn. */
- return 2594;
+ return 2722;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0010xxxxxxxxxxxx
cpymrt. */
- return 2609;
+ return 2737;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0010xxxxxxxxxxxx
setgpn. */
- return 2650;
+ return 2778;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1010xxxxxxxxxxxx
cpymrtrn. */
- return 2615;
+ return 2743;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1010xxxxxxxxxxxx
setgen. */
- return 2652;
+ return 2780;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0110xxxxxxxxxxxx
cpymrtwn. */
- return 2612;
+ return 2740;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0110xxxxxxxxxxxx
setgmn. */
- return 2651;
+ return 2779;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1110xxxxxxxxxxxx
cpymrtn. */
- return 2618;
+ return 2746;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0001xxxxxxxxxxxx
cpymwt. */
- return 2597;
+ return 2725;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0001xxxxxxxxxxxx
setgpt. */
- return 2647;
+ return 2775;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1001xxxxxxxxxxxx
cpymwtrn. */
- return 2603;
+ return 2731;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1001xxxxxxxxxxxx
setget. */
- return 2649;
+ return 2777;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0101xxxxxxxxxxxx
cpymwtwn. */
- return 2600;
+ return 2728;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0101xxxxxxxxxxxx
setgmt. */
- return 2648;
+ return 2776;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1101xxxxxxxxxxxx
cpymwtn. */
- return 2606;
+ return 2734;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0011xxxxxxxxxxxx
cpymt. */
- return 2621;
+ return 2749;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0011xxxxxxxxxxxx
setgptn. */
- return 2653;
+ return 2781;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1011xxxxxxxxxxxx
cpymtrn. */
- return 2627;
+ return 2755;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1011xxxxxxxxxxxx
setgetn. */
- return 2655;
+ return 2783;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0111xxxxxxxxxxxx
cpymtwn. */
- return 2624;
+ return 2752;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0111xxxxxxxxxxxx
setgmtn. */
- return 2654;
+ return 2782;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1111xxxxxxxxxxxx
cpymtn. */
- return 2630;
+ return 2758;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2511;
+ return 2639;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2437;
+ return 2565;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2513;
+ return 2641;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2514;
+ return 2642;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2444;
+ return 2572;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2446;
+ return 2574;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2448;
+ return 2576;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2449;
+ return 2577;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2442;
+ return 2570;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2451;
+ return 2579;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2450;
+ return 2578;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2455;
+ return 2583;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2452;
+ return 2580;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2436;
+ return 2564;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2512;
+ return 2640;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2528;
+ return 2656;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2526;
+ return 2654;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2533;
+ return 2661;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2532;
+ return 2660;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2529;
+ return 2657;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2530;
+ return 2658;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2447;
+ return 2575;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2440;
+ return 2568;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2453;
+ return 2581;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2443;
+ return 2571;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2456;
+ return 2584;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2441;
+ return 2569;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2454;
+ return 2582;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2445;
+ return 2573;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2459;
+ return 2587;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2463;
+ return 2591;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2460;
+ return 2588;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2464;
+ return 2592;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2457;
+ return 2585;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2461;
+ return 2589;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2458;
+ return 2586;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2462;
+ return 2590;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2465;
+ return 2593;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2469;
+ return 2597;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2466;
+ return 2594;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2470;
+ return 2598;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2467;
+ return 2595;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2471;
+ return 2599;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2468;
+ return 2596;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2472;
+ return 2600;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2439;
+ return 2567;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2438;
+ return 2566;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2516;
+ return 2644;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2515;
+ return 2643;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2527;
+ return 2655;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2535;
+ return 2663;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2534;
+ return 2662;
}
}
}
{
case 2389: value = 2391; break; /* mov --> mova. */
case 2391: return NULL; /* mova --> NULL. */
- case 2426: value = 2434; break; /* mov --> mova. */
- case 2434: return NULL; /* mova --> NULL. */
- case 2424: value = 2432; break; /* mov --> mova. */
- case 2432: return NULL; /* mova --> NULL. */
- case 2427: value = 2435; break; /* mov --> mova. */
- case 2435: return NULL; /* mova --> NULL. */
- case 2425: value = 2433; break; /* mov --> mova. */
- case 2433: return NULL; /* mova --> NULL. */
+ case 2490: value = 2498; break; /* mov --> mova. */
+ case 2498: return NULL; /* mova --> NULL. */
+ case 2488: value = 2496; break; /* mov --> mova. */
+ case 2496: return NULL; /* mova --> NULL. */
+ case 2491: value = 2499; break; /* mov --> mova. */
+ case 2499: return NULL; /* mova --> NULL. */
+ case 2489: value = 2497; break; /* mov --> mova. */
+ case 2497: return NULL; /* mova --> NULL. */
case 2388: value = 2390; break; /* mov --> mova. */
case 2390: return NULL; /* mova --> NULL. */
- case 2422: value = 2430; break; /* mov --> mova. */
- case 2430: return NULL; /* mova --> NULL. */
- case 2420: value = 2428; break; /* mov --> mova. */
- case 2428: return NULL; /* mova --> NULL. */
- case 2423: value = 2431; break; /* mov --> mova. */
- case 2431: return NULL; /* mova --> NULL. */
- case 2421: value = 2429; break; /* mov --> mova. */
- case 2429: return NULL; /* mova --> NULL. */
+ case 2486: value = 2494; break; /* mov --> mova. */
+ case 2494: return NULL; /* mova --> NULL. */
+ case 2484: value = 2492; break; /* mov --> mova. */
+ case 2492: return NULL; /* mova --> NULL. */
+ case 2487: value = 2495; break; /* mov --> mova. */
+ case 2495: return NULL; /* mova --> NULL. */
+ case 2485: value = 2493; break; /* mov --> mova. */
+ case 2493: return NULL; /* mova --> NULL. */
case 2393: value = 2398; break; /* ld1b --> ld1b. */
case 2398: return NULL; /* ld1b --> NULL. */
case 2395: value = 2400; break; /* ld1w --> ld1w. */
case 2407: value = 2412; break; /* st1q --> st1q. */
case 2412: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
- case 19: value = 2657; break; /* addg --> smax. */
- case 2657: value = 2658; break; /* smax --> umax. */
- case 2658: value = 2659; break; /* umax --> smin. */
- case 2659: value = 2660; break; /* smin --> umin. */
- case 2660: return NULL; /* umin --> NULL. */
+ case 19: value = 2785; break; /* addg --> smax. */
+ case 2785: value = 2786; break; /* smax --> umax. */
+ case 2786: value = 2787; break; /* umax --> smin. */
+ case 2787: value = 2788; break; /* smin --> umin. */
+ case 2788: return NULL; /* umin --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 20: return NULL; /* subg --> NULL. */
case 971: value = 975; break; /* stnp --> stp. */
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2531; break; /* fcvt --> bfcvt. */
- case 2531: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2659; break; /* fcvt --> bfcvt. */
+ case 2659: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 203:
case 209:
case 212:
- case 218:
- case 219:
- case 224:
+ case 220:
+ case 221:
+ case 226:
+ case 227:
return aarch64_ext_regno (self, info, code, inst, errors);
case 10:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 234:
+ case 237:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 225:
- case 233:
- case 238:
- case 239:
+ case 228:
+ case 236:
+ case 241:
+ case 242:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
case 216:
case 217:
return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
- case 220:
+ case 218:
+ case 219:
+ return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
case 222:
- case 226:
+ case 224:
+ case 229:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 221:
case 223:
+ case 225:
return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 227:
- case 228:
- case 229:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 230:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 231:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 232:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
+ case 233:
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 234:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 235:
- case 236:
- case 237:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 238:
+ case 239:
+ case 240:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
- info->reg.regno = extract_field (self->fields[0], code, 0);
+ info->reg.regno = (extract_field (self->fields[0], code, 0)
+ + get_operand_specific_data (self));
return true;
}
return true;
}
+/* Decode a strided register list. The first field holds the top bit
+ (0 or 16) and the second field holds the lower bits. The stride is
+ 16 divided by the list length. */
+bool
+aarch64_ext_sve_strided_reglist (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors
+ ATTRIBUTE_UNUSED)
+{
+ unsigned int upper = extract_field (self->fields[0], code, 0);
+ unsigned int lower = extract_field (self->fields[1], code, 0);
+ info->reglist.first_regno = upper * 16 + lower;
+ info->reglist.num_regs = get_operand_specific_data (self);
+ info->reglist.stride = 16 / info->reglist.num_regs;
+ return true;
+}
+
/* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
field. */
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_strided_reglist);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
{ 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
+ { 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */
+ { 0, 3 }, /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */
+ { 0, 2 }, /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
}
break;
+ case AARCH64_OPND_SME_Ztx2_STRIDED:
+ case AARCH64_OPND_SME_Ztx4_STRIDED:
+ /* 2-register lists have a stride of 8 and 4-register lists
+ have a stride of 4. */
+ num = get_operand_specific_data (&aarch64_operands[type]);
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
+ return 0;
+ num = 16 | (opnd->reglist.stride - 1);
+ if ((opnd->reglist.first_regno & ~num) != 0)
+ {
+ set_other_error (mismatch_detail, idx,
+ _("start register out of range"));
+ return 0;
+ }
+ break;
+
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
num = get_opcode_dependent_value (opcode);
break;
case AARCH64_OPND_CLASS_PRED_REG:
- if (opnd->reg.regno >= 8
- && get_operand_fields_width (get_operand_from_code (type)) == 3)
+ switch (type)
{
- set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
- return 0;
+ case AARCH64_OPND_SME_PNg3:
+ if (opnd->reg.regno < 8)
+ {
+ set_invalid_regno_error (mismatch_detail, idx, "pn", 8, 15);
+ return 0;
+ }
+ break;
+
+ default:
+ if (opnd->reg.regno >= 8
+ && get_operand_fields_width (get_operand_from_code (type)) == 3)
+ {
+ set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
+ return 0;
+ }
+ break;
}
break;
case AARCH64_OPND_SVE_PNg4_10:
case AARCH64_OPND_SVE_PNn:
case AARCH64_OPND_SVE_PNt:
+ case AARCH64_OPND_SME_PNg3:
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
snprintf (buf, size, "%s",
style_reg (styler, "pn%d", opnd->reg.regno));
+ else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
+ || opnd->qualifier == AARCH64_OPND_QLF_P_M)
+ snprintf (buf, size, "%s",
+ style_reg (styler, "pn%d/%s", opnd->reg.regno,
+ aarch64_get_qualifier_name (opnd->qualifier)));
else
snprintf (buf, size, "%s",
style_reg (styler, "pn%d.%s", opnd->reg.regno,
case AARCH64_OPND_SME_Zdnx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
+ case AARCH64_OPND_SME_Ztx2_STRIDED:
+ case AARCH64_OPND_SME_Ztx4_STRIDED:
print_register_list (buf, size, opnd, "z", styler);
break;
FLD_SME_Zdn4,
FLD_SME_Zn2,
FLD_SME_Zn4,
+ FLD_SME_ZtT,
+ FLD_SME_Zt3,
+ FLD_SME_Zt2,
FLD_SME_i1,
FLD_SME_size_22,
FLD_SME_tszh,
value by 2 to get the value
of an immediate operand. */
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
-#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
+#define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */
#define OPD_F_OD_LSB 5
-#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
-#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
+#define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */
+#define OPD_F_SHIFT_BY_4 0x00000400 /* Need to left shift the field
value by 4 to get the value
of an immediate operand. */
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* SME2 extensions to SME. */
+ SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa1408000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa0000000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa0008000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa1000000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1b", 0xa1008000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa0406000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa040e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa1406000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa140e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa0006000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa000e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa1006000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1d", 0xa100e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa0402000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa040a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa1402000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa140a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa0002000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa000a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa1002000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1h", 0xa100a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa0404000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa040c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa1404000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa140c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa0004000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa000c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa1004000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ld1w", 0xa100c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa0400001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa0408001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa1400008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa1408008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa0000001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa0008001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa1000008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1b", 0xa1008008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa0406001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa040e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa1406008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa140e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa0006001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa000e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa1006008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1d", 0xa100e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa0402001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa040a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa1402008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa140a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa0002001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa000a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa1002008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1h", 0xa100a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa0404001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa040c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa1404008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa140c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa0004001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
+ SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa1608000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa0200000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa0208000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa1200000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1b", 0xa1208000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("st1d", 0xa0606000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa060e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa1606000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa160e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa0206000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa020e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa1206000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1d", 0xa120e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("st1h", 0xa0602000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa060a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa1602000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa160a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa0202000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa020a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa1202000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1h", 0xa120a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("st1w", 0xa0604000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa060c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa1604000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa160c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa0204000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa020c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa1204000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("st1w", 0xa120c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa0600001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa0608001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa1600008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa1608008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa0200001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa0208001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa1200008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1b", 0xa1208008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa0606001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa060e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa1606008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa160e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa0206001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa020e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa1206008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1d", 0xa120e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa0602001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa060a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa1602008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa160a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa0202001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa020a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa1202008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1h", 0xa120a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa0604001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa060c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa1604008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa160c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa0204001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
F(FLD_SME_Zn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zn4), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
+ 2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \
+ "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \
+ 4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \
+ "a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
"an SME ZA tile ZA0-ZA3") \
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
"an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
+ Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \
+ "an SVE predicate-as-counter register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
projects / thirdparty / binutils-gdb.git / commitdiff
