Fix conditional add LRA failure for amdgcn

Fix ICE in testcase gfortran.dg/assumed_rank_bounds_3.f90.

2020-01-31  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
	alternative only.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0e99b72043762dfdfcce25a711c8344d7b521c04..022865d005d329432aef1dc084860cad1d691791 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-31  Andrew Stubbs  <ams@codesourcery.com>
+
+       * config/gcn/gcn-valu.md (addv64di3_exec): Allow one '0' in each
+       alternative only.
+
 2020-01-31  Uroš Bizjak  <ubizjak@gmail.com>
 
        * config/i386/i386.md (*movoi_internal_avx): Do not check for

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 4aad835b2efc6416866a55c8f3ccd1c95ba98150..ecdd60b8190b181a16d06e709c0679507e05e5fc 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1200,13 +1200,14 @@
    (set_attr "length" "8")])
 
 (define_insn_and_split "addv64di3_exec"
-  [(set (match_operand:V64DI 0 "register_operand"               "= &v,  &v")
+  [(set (match_operand:V64DI 0 "register_operand"           "= &v,  &v, &v")
        (vec_merge:V64DI
          (plus:V64DI
-           (match_operand:V64DI 1 "register_operand"            "%vDb,vDb0")
-           (match_operand:V64DI 2 "gcn_alu_operand"             "vDb0, vDb"))
-         (match_operand:V64DI 3 "gcn_register_or_unspec_operand" " U0,  U0")
-         (match_operand:DI 4 "gcn_exec_reg_operand"             "   e,   e")))
+           (match_operand:V64DI 1 "register_operand"        "%vDb,vDb0,vDb")
+           (match_operand:V64DI 2 "gcn_alu_operand"         "vDb0, vDb,vDb"))
+         (match_operand:V64DI 3 "gcn_register_or_unspec_operand"
+                                                            "   U,   U,  0")
+         (match_operand:DI 4 "gcn_exec_reg_operand"         "   e,   e,  e")))
    (clobber (reg:DI VCC_REG))]
   ""
   "#"