Merge tag 'mtd/fixes-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull MTD fixes from Miquel Raynal:
 "There has been OTP support improvements in the NVMEM subsystem, and
  later also improvements of OTP support in the NAND subsystem. This
  lead to situations that we currently cannot handle, so better prevent
  this situation from happening in order to avoid canceling device's
  probe.

  In the raw NAND subsystem, two runtime fixes have been shared, one
  fixing two important commands in the Qcom driver since it got reworked
  and a NULL pointer dereference happening on STB chips.

  Arnd also fixed a UBSAN link failure on diskonchip"

* tag 'mtd/fixes-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
  mtd: limit OTP NVMEM cell parse to non-NAND devices
  mtd: diskonchip: work around ubsan link failure
  mtd: rawnand: qcom: Fix broken OP_RESET_DEVICE command in qcom_misc_cmd_type_exec()
  mtd: rawnand: brcmnand: Fix data access violation for STB chip

diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 5887feb347a4e42aa1dcc779bc7f5b252402b16e..0de87bc63840546d8a11dfe959874a5af7835ac6 100644 (file)
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -900,7 +900,7 @@ static struct nvmem_device *mtd_otp_nvmem_register(struct mtd_info *mtd,
        config.name = compatible;
        config.id = NVMEM_DEVID_AUTO;
        config.owner = THIS_MODULE;
-       config.add_legacy_fixed_of_cells = true;
+       config.add_legacy_fixed_of_cells = !mtd_type_is_nand(mtd);
        config.type = NVMEM_TYPE_OTP;
        config.root_only = true;
        config.ignore_wp = true;

diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index a8d12c71f987be95817a69b4ee92c229ec8bf814..1b2ec0fec60c7a19e76f67dc5db47e98f4ad8a28 100644 (file)
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -857,7 +857,7 @@ static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl,
        struct brcmnand_soc *soc = ctrl->soc;
        int i;
 
-       if (soc->read_data_bus) {
+       if (soc && soc->read_data_bus) {
                soc->read_data_bus(soc, flash_cache, buffer, fc_words);
        } else {
                for (i = 0; i < fc_words; i++)

diff --git a/drivers/mtd/nand/raw/diskonchip.c b/drivers/mtd/nand/raw/diskonchip.c
index 5243fab9face0034ecf54838345624b816f91906..8db7fc424571116abb467def163d2f1725c49b9f 100644 (file)
--- a/drivers/mtd/nand/raw/diskonchip.c
+++ b/drivers/mtd/nand/raw/diskonchip.c
@@ -53,7 +53,7 @@ static unsigned long doc_locations[] __initdata = {
        0xe8000, 0xea000, 0xec000, 0xee000,
 #endif
 #endif
-       0xffffffff };
+};
 
 static struct mtd_info *doclist = NULL;
 
@@ -1554,7 +1554,7 @@ static int __init init_nanddoc(void)
                if (ret < 0)
                        return ret;
        } else {
-               for (i = 0; (doc_locations[i] != 0xffffffff); i++) {
+               for (i = 0; i < ARRAY_SIZE(doc_locations); i++) {
                        doc_probe(doc_locations[i]);
                }
        }

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index b079605c84d38204971834ea2c26d2858165b506..b8cff9240b286c7ac789bf4216611b54bee05dd3 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
                              host->cfg0_raw & ~(7 << CW_PER_PAGE));
                nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
                instrs = 3;
-       } else {
+       } else if (q_op.cmd_reg != OP_RESET_DEVICE) {
                return 0;
        }
 
@@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
        nandc_set_reg(chip, NAND_EXEC_CMD, 1);
 
        write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
-       (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
-       2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
-       NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
+       if (q_op.cmd_reg == OP_BLOCK_ERASE)
+               write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
 
        write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
        read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);