x86: CET v2.0: Rename savessp to saveprevssp

Replace savessp with saveprevssp for CET v2.0:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* testsuite/gas/i386/cet-intel.d: Updated.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ed35a2139b0c61355cc76770a00eb7c126c63789..855401daeb4c16c60a7c4743ec3e8f14c4499bc4 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * testsuite/gas/i386/cet-intel.d: Updated.
+       * testsuite/gas/i386/cet.d: Likewise.
+       * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+       * testsuite/gas/i386/x86-64-cet.d: Likewise.
+       * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
+       * testsuite/gas/i386/x86-64-cet.s: Likewise.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/tc-i386.c (md_assemble): Update NOTRACK prefix check.

diff --git a/gas/testsuite/gas/i386/cet-intel.d b/gas/testsuite/gas/i386/cet-intel.d
index a5f5533472e7d90a8f11f710cdb6ea5bb5765685..c16a963640f413f93eacab1b4f4e17c30ed4ddf0 100644 (file)
--- a/gas/testsuite/gas/i386/cet-intel.d
+++ b/gas/testsuite/gas/i386/cet-intel.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:   f3 0f 01 e9             incsspd 
  +[a-f0-9]+:   f3 0f 1e c9             rdsspd ecx
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 0f 01 29             rstorssp QWORD PTR \[ecx\]
  +[a-f0-9]+:   0f 38 f6 04 02          wrssd  \[edx\+eax\*1\],eax
  +[a-f0-9]+:   66 0f 38 f5 14 2f       wrussd \[edi\+ebp\*1\],edx
@@ -20,7 +20,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 0f 1e fb             endbr32 
  +[a-f0-9]+:   f3 0f 01 e9             incsspd 
  +[a-f0-9]+:   f3 0f 1e c9             rdsspd ecx
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 0f 01 2c 01          rstorssp QWORD PTR \[ecx\+eax\*1\]
  +[a-f0-9]+:   0f 38 f6 02             wrssd  \[edx\],eax
  +[a-f0-9]+:   66 0f 38 f5 14 2f       wrussd \[edi\+ebp\*1\],edx

diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d
index bb356e498536c5f38b8b6ebd7517ef9f0d912c15..449f04e63eff591a48a1679bfba9e30b4d1148cb 100644 (file)
--- a/gas/testsuite/gas/i386/cet.d
+++ b/gas/testsuite/gas/i386/cet.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
 0+ <_start>:
  +[a-f0-9]+:   f3 0f 01 e9             incsspd 
  +[a-f0-9]+:   f3 0f 1e c9             rdsspd %ecx
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 0f 01 29             rstorssp \(%ecx\)
  +[a-f0-9]+:   0f 38 f6 04 02          wrssd  %eax,\(%edx,%eax,1\)
  +[a-f0-9]+:   66 0f 38 f5 14 2f       wrussd %edx,\(%edi,%ebp,1\)
@@ -18,7 +18,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 0f 1e fb             endbr32 
  +[a-f0-9]+:   f3 0f 01 e9             incsspd 
  +[a-f0-9]+:   f3 0f 1e c9             rdsspd %ecx
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 0f 01 2c 01          rstorssp \(%ecx,%eax,1\)
  +[a-f0-9]+:   0f 38 f6 02             wrssd  %eax,\(%edx\)
  +[a-f0-9]+:   66 0f 38 f5 14 2f       wrussd %edx,\(%edi,%ebp,1\)

diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s
index deb659d694d525bc6ecd797d93b0487e5b011efb..f0b6db0b6ec23be56e166bf8d0f45525fd8cc8e8 100644 (file)
--- a/gas/testsuite/gas/i386/cet.s
+++ b/gas/testsuite/gas/i386/cet.s
@@ -3,7 +3,7 @@
 _start:
        incsspd
        rdsspd %ecx
-       savessp
+       saveprevssp
        rstorssp (%ecx)
        wrssd %eax, (%edx, %eax)
        wrussd %edx, (%edi, %ebp)
@@ -15,7 +15,7 @@ _start:
        .intel_syntax noprefix
        incsspd
        rdsspd ecx
-       savessp
+       saveprevssp
        rstorssp QWORD PTR [ecx + eax]
        wrssd [edx],eax
        wrussd [edi + ebp],edx

diff --git a/gas/testsuite/gas/i386/x86-64-cet-intel.d b/gas/testsuite/gas/i386/x86-64-cet-intel.d
index 07e666fbb9fcfa31b893213f1a9fcda6176b21c0..2d2af7189938d258264df7b5c8b7efe598040162 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-cet-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 48 0f 01 e9          incsspq 
  +[a-f0-9]+:   f3 41 0f 1e cc          rdsspd r12d
  +[a-f0-9]+:   f3 48 0f 1e c8          rdsspq rax
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 41 0f 01 2c 24       rstorssp QWORD PTR \[r12\]
  +[a-f0-9]+:   41 0f 38 f6 04 24       wrssd  \[r12\],eax
  +[a-f0-9]+:   4a 0f 38 f6 14 39       wrssq  \[rcx\+r15\*1\],rdx
@@ -25,7 +25,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 48 0f 01 e9          incsspq 
  +[a-f0-9]+:   f3 41 0f 1e cc          rdsspd r12d
  +[a-f0-9]+:   f3 48 0f 1e c8          rdsspq rax
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 41 0f 01 2c 24       rstorssp QWORD PTR \[r12\]
  +[a-f0-9]+:   41 0f 38 f6 04 24       wrssd  \[r12\],eax
  +[a-f0-9]+:   4a 0f 38 f6 14 39       wrssq  \[rcx\+r15\*1\],rdx

diff --git a/gas/testsuite/gas/i386/x86-64-cet.d b/gas/testsuite/gas/i386/x86-64-cet.d
index 7e5b717f6a95cc50c5fd6e85bcc24759adeee609..6981e9f183a03ce2b03eb2340479d28504ea8dc8 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-cet.d
+++ b/gas/testsuite/gas/i386/x86-64-cet.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 48 0f 01 e9          incsspq 
  +[a-f0-9]+:   f3 41 0f 1e cc          rdsspd %r12d
  +[a-f0-9]+:   f3 48 0f 1e c8          rdsspq %rax
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 41 0f 01 2c 24       rstorssp \(%r12\)
  +[a-f0-9]+:   41 0f 38 f6 04 24       wrssd  %eax,\(%r12\)
  +[a-f0-9]+:   4a 0f 38 f6 14 39       wrssq  %rdx,\(%rcx,%r15,1\)
@@ -24,7 +24,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   f3 48 0f 01 e9          incsspq 
  +[a-f0-9]+:   f3 41 0f 1e cc          rdsspd %r12d
  +[a-f0-9]+:   f3 48 0f 1e c8          rdsspq %rax
- +[a-f0-9]+:   f3 0f 01 ea             savessp 
+ +[a-f0-9]+:   f3 0f 01 ea             saveprevssp 
  +[a-f0-9]+:   f3 41 0f 01 2c 24       rstorssp \(%r12\)
  +[a-f0-9]+:   41 0f 38 f6 04 24       wrssd  %eax,\(%r12\)
  +[a-f0-9]+:   4a 0f 38 f6 14 39       wrssq  %rdx,\(%rcx,%r15,1\)

diff --git a/gas/testsuite/gas/i386/x86-64-cet.s b/gas/testsuite/gas/i386/x86-64-cet.s
index 15a28d74719bd77beeee53677d99c4cbe453cd84..fbed7004ba977778109fb6ab04a4608873d4dd56 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-cet.s
+++ b/gas/testsuite/gas/i386/x86-64-cet.s
@@ -5,7 +5,7 @@ _start:
        incsspq
        rdsspd %r12d
        rdsspq %rax
-       savessp
+       saveprevssp
        rstorssp (%r12)
        wrssd %eax, (%r12)
        wrssq %rdx, (%rcx, %r15)
@@ -21,7 +21,7 @@ _start:
        incsspq
        rdsspd r12d
        rdsspq rax
-       savessp
+       saveprevssp
        rstorssp QWORD PTR [r12]
        wrssd [r12],eax
        wrssq [rcx+r15],rdx

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 671837fa09ba39e0b690822707cd4190f6a4bfe4..3ffafa143816ee4f4c8c6b4e4edba455c5dfde9b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
+       * i386-opc.tbl: Likewise.
+       * i386-tbl.h: Regenerated.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 2e35e38e2be226b0d3e75e7ca1ab51fc9b8f41e4..58d4c06845052ab20d30b974628245ddb8a915fb 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3798,7 +3798,7 @@ static const struct dis386 prefix_table[][4] = {
   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
   {
     { Bad_Opcode },
-    { "savessp",       { Skip_MODRM }, PREFIX_OPCODE },
+    { "saveprevssp",   { Skip_MODRM }, PREFIX_OPCODE },
   },
 
   /* PREFIX_0F10 */

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5b1a4fd03bb06d9ed04b03c920ff8bd93e47c86a..47e1f6649997214ccb36ae65707437c097c16e21 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -6013,7 +6013,7 @@ incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
 incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
 rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
 rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
-savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 1fcd0030f719b9866544d19cfb9a6aa23c37b378..4bc3878bb8e7476ada1fd20f6ed95d5d79989186 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -92045,7 +92045,7 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
-  { "savessp", 0, 0xf30f01ea, None, 3,
+  { "saveprevssp", 0, 0xf30f01ea, None, 3,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,