--- /dev/null
+#as: -m750cl
+#objdump: -dr -Mppcps
+#name: PPC750CL paired single tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+0000000 <start>:
+ 0: e0 03 d0 04 psq_l f0,4\(r3\),1,5
+ 4: e4 22 30 08 psq_lu f1,8\(r2\),0,3
+ 8: 10 45 25 4c psq_lux f2,r5,r4,1,2
+ c: 10 62 22 8c psq_lx f3,r2,r4,0,5
+ 10: f0 62 30 08 psq_st f3,8\(r2\),0,3
+ 14: f4 62 70 08 psq_stu f3,8\(r2\),0,7
+ 18: 10 43 22 ce psq_stux f2,r3,r4,0,5
+ 1c: 10 c7 46 0e psq_stx f6,r7,r8,1,4
+ 20: 10 a0 3a 10 ps_abs f5,f7
+ 24: 10 a0 3a 11 ps_abs. f5,f7
+ 28: 10 22 18 2a ps_add f1,f2,f3
+ 2c: 10 22 18 2b ps_add. f1,f2,f3
+ 30: 11 82 20 40 ps_cmpo0 cr3,f2,f4
+ 34: 11 82 20 c0 ps_cmpo1 cr3,f2,f4
+ 38: 11 82 20 00 ps_cmpu0 cr3,f2,f4
+ 3c: 11 82 20 80 ps_cmpu1 cr3,f2,f4
+ 40: 10 44 30 24 ps_div f2,f4,f6
+ 44: 10 44 30 25 ps_div. f2,f4,f6
+ 48: 10 01 18 ba ps_madd f0,f1,f2,f3
+ 4c: 10 01 18 bb ps_madd. f0,f1,f2,f3
+ 50: 10 22 20 dc ps_madds0 f1,f2,f3,f4
+ 54: 10 22 20 dd ps_madds0. f1,f2,f3,f4
+ 58: 10 22 20 de ps_madds1 f1,f2,f3,f4
+ 5c: 10 22 20 df ps_madds1. f1,f2,f3,f4
+ 60: 10 44 34 20 ps_merge00 f2,f4,f6
+ 64: 10 44 34 21 ps_merge00. f2,f4,f6
+ 68: 10 44 34 60 ps_merge01 f2,f4,f6
+ 6c: 10 44 34 61 ps_merge01. f2,f4,f6
+ 70: 10 44 34 a0 ps_merge10 f2,f4,f6
+ 74: 10 44 34 a1 ps_merge10. f2,f4,f6
+ 78: 10 44 34 e0 ps_merge11 f2,f4,f6
+ 7c: 10 44 34 e1 ps_merge11. f2,f4,f6
+ 80: 10 60 28 90 ps_mr f3,f5
+ 84: 10 60 28 91 ps_mr. f3,f5
+ 88: 10 44 41 b8 ps_msub f2,f4,f6,f8
+ 8c: 10 44 41 b9 ps_msub. f2,f4,f6,f8
+ 90: 10 43 01 72 ps_mul f2,f3,f5
+ 94: 10 43 01 73 ps_mul. f2,f3,f5
+ 98: 10 64 01 d8 ps_muls0 f3,f4,f7
+ 9c: 10 64 01 d9 ps_muls0. f3,f4,f7
+ a0: 10 64 01 da ps_muls1 f3,f4,f7
+ a4: 10 64 01 db ps_muls1. f3,f4,f7
+ a8: 10 20 29 10 ps_nabs f1,f5
+ ac: 10 20 29 11 ps_nabs. f1,f5
+ b0: 10 20 28 50 ps_neg f1,f5
+ b4: 10 20 28 51 ps_neg. f1,f5
+ b8: 10 23 39 7e ps_nmadd f1,f3,f5,f7
+ bc: 10 23 39 7f ps_nmadd. f1,f3,f5,f7
+ c0: 10 23 39 7c ps_nmsub f1,f3,f5,f7
+ c4: 10 23 39 7d ps_nmsub. f1,f3,f5,f7
+ c8: 11 20 18 30 ps_res f9,f3
+ cc: 11 20 18 31 ps_res. f9,f3
+ d0: 11 20 18 34 ps_rsqrte f9,f3
+ d4: 11 20 18 35 ps_rsqrte. f9,f3
+ d8: 10 22 20 ee ps_sel f1,f2,f3,f4
+ dc: 10 22 20 ef ps_sel. f1,f2,f3,f4
+ e0: 10 ab 10 28 ps_sub f5,f11,f2
+ e4: 10 ab 10 29 ps_sub. f5,f11,f2
+ e8: 10 45 52 54 ps_sum0 f2,f5,f9,f10
+ ec: 10 45 52 55 ps_sum0. f2,f5,f9,f10
+ f0: 10 45 52 56 ps_sum1 f2,f5,f9,f10
+ f4: 10 45 52 57 ps_sum1. f2,f5,f9,f10
+ f8: 10 03 2f ec dcbz_l r3,r5
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
/* The E field in a wrteei instruction. */
+ /* And the W bit in the pair singles instructions. */
#define E DS + 1
+#define PSW E
{ 0x1, 15, NULL, NULL, 0 },
/* The FL1 field in a POWER SC form instruction. */
#define WS EVUIMM_8 + 1
{ 0x7, 11, NULL, NULL, 0 },
- /* The L field in an mtmsrd or A form instruction or W in an X form. */
-#define A_L WS + 1
+ /* PowerPC paired singles extensions. */
+ /* W bit in the pair singles instructions for x type instructions. */
+#define PSWM WS + 1
+ { 0x1, 10, 0, 0, 0 },
+
+ /* IDX bits for quantization in the pair singles instructions. */
+#define PSQ PSWM + 1
+ { 0x7, 12, 0, 0, 0 },
+
+ /* IDX bits for quantization in the pair singles x-type instructions. */
+#define PSQM PSQ + 1
+ { 0x7, 7, 0, 0, 0 },
+
+ /* Smaller D field for quantization in the pair singles instructions. */
+#define PSD PSQM + 1
+ { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
+#define A_L PSD + 1
#define W A_L
+#define MTMSRD_L W
{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
-#define RMC A_L + 1
+#define RMC MTMSRD_L + 1
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
/* An XO_MASK with the RB field fixed. */
#define XORB_MASK (XO_MASK | RB_MASK)
+/* An XOPS form instruction for paired singles. */
+#define XOPS(op, xop, rc) \
+ (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
+#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
+
+
/* An XS form instruction. */
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
#define XS_MASK XS (0x3f, 0x1ff, 1)
#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define XUC_MASK XUC(0x3f, 0x1f)
+/* An XW form instruction. */
+#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
+/* The mask for a G form instruction. rc not supported at present. */
+#define XW_MASK XW (0x3f, 0x3f, 0)
+
/* The BO encodings used in extended conditional branch mnemonics. */
#define BODNZF (0x0)
#define BODNZFP (0x1)
#define PPC750 PPC
#define PPC7450 PPC
#define PPC860 PPC
+#define PPCPS PPC_OPCODE_PPCPS
#define PPCVEC PPC_OPCODE_ALTIVEC
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
+{ "dcbz_l", X(4,1014), XRT_MASK, PPCPS, { RA, RB } },
+{ "ps_cmpu0", X(4 ,0), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{ "psq_lx", XW(4,6,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stx", XW(4,7,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_sum0", A(4 ,10,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum0.", A(4 ,10,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1", A(4 ,11,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1.", A(4 ,11,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_muls0", A(4 ,12,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls0.", A(4 ,12,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls1", A(4 ,13,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_muls1.", A(4 ,13,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_madds0", A(4 ,14,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds0.", A(4 ,14,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1", A(4 ,15,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1.", A(4 ,15,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_div", A(4,18,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_div.", A(4,18,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sub", A(4,20,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sub.", A(4,20,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_add", A(4,21,0), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_add.", A(4,21,1), AFRC_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_sel", A(4,23,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_sel.", A(4,23,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_res", A(4,24,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_res.", A(4,24,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_mul", A(4,25,0), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_mul.", A(4,25,1), AFRB_MASK, PPCPS, { FRT, FRA, FRC } },
+{ "ps_rsqrte", A(4 ,26,0), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_rsqrte.", A(4 ,26,1), AFRAFRC_MASK, PPCPS, { FRT, FRB } },
+{ "ps_madd", A(4,29,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_madd.", A(4,29,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_msub", A(4,28,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_msub.", A(4,28,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub", A(4,30,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub.", A(4,30,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd", A(4,31,0), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd.", A(4,31,1), A_MASK, PPCPS, { FRT,FRA,FRC,FRB } },
+{ "ps_cmpo0", X(4 ,32), X_MASK|(3<<21),PPCPS, { BF, FRA, FRB } },
+{ "psq_lux", XW(4,38,0), XW_MASK, PPCPS, { FRT, RA, RB, PSWM, PSQM } },
+{ "psq_stux", XW(4,39,0), XW_MASK, PPCPS, { FRS, RA, RB, PSWM, PSQM } },
+{ "ps_neg", XRC(4 ,40,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_neg.", XRC(4 ,40,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_cmpu1", X(4 ,64), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{ "ps_mr", XRC(4 ,72,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_mr.", XRC(4 ,72,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_cmpo1", X(4 ,96), X_MASK|(3<<21), PPCPS, { BF, FRA, FRB } },
+{ "ps_nabs", XRC(4 ,136,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_nabs.", XRC(4 ,136,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_abs", XRC(4,264,0), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_abs.", XRC(4,264,1), XRA_MASK, PPCPS, { FRT, FRB } },
+{ "ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge00.",XOPS(4,528,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge01.",XOPS(4,560,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge10.",XOPS(4,592,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
+{ "ps_merge11.",XOPS(4,624,1), XOPS_MASK, PPCPS, { FRT, FRA, FRB } },
{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
+{ "psq_l", OP(56), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
+
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
+{ "psq_lu", OP(57), OP_MASK, PPCPS, { FRT, PSD, RA, PSW, PSQ } },
+
{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
+{ "psq_st", OP(60), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+{ "psq_stu", OP(61), OP_MASK, PPCPS, { FRS, PSD, RA, PSW, PSQ } },
+
{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
projects / thirdparty / binutils-gdb.git / commitdiff
