[RFA] Fix for mcore simulator

I was looking for cases where a GCC patch under evaluation would cause test
results to change.  Quite surprisingly the mcore-elf port showed test
differences.   After a fair amount of digging my conclusion was the sequences
before/after the patch should have been semantically the same.

Of course if the code is supposed to behave the same, then that points to
problems elsewhere (assembler, linker, simulator).  Sure enough the mcore
simulator was mis-handling the sign extension instructions.  The simulator
implementation of sextb is via paired shift-by-24 operations. Similarly the
simulator implements sexth via paired shift-by-16 operations.

The temporary holding the value was declared as a "long" thus this approach
worked fine for hosts with a 32 bit wide long and failed miserably for hosts
with a 64 bit wide long.

This patch makes the shift count automatically adjust based on the size of the
temporary.  It includes a simple test for sextb and sexth.  I have _not_ done a
full audit of the mcore simulator for more 32->64 bit issues.

This also fixes 443 execution tests in the GCC testsuite

diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 53cfdad050b4d3b4cbb6e938f160a85a50074bb8..48d9ff8645a786d221513195840be16e56777821 100644 (file)
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -641,8 +641,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
              {
                long tmp;
                tmp = gr[RD];
-               tmp <<= 24;
-               tmp >>= 24;
+               tmp <<= (sizeof (tmp) * 8) - 8;
+               tmp >>= (sizeof (tmp) * 8) - 8;
                gr[RD] = tmp;
              }
              break;
@@ -653,8 +653,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
              {
                long tmp;
                tmp = gr[RD];
-               tmp <<= 16;
-               tmp >>= 16;
+               tmp <<= (sizeof (tmp) * 8) - 16;
+               tmp >>= (sizeof (tmp) * 8) - 16;
                gr[RD] = tmp;
              }
              break;

diff --git a/sim/testsuite/mcore/sextb.s b/sim/testsuite/mcore/sextb.s
new file mode 100644 (file)
index 0000000..5500f7a
--- /dev/null
+++ b/sim/testsuite/mcore/sextb.s
@@ -0,0 +1,25 @@
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+       start
+       # Construct -120 using bgeni+addi+sext
+       bgeni   r2, 7
+       addi    r2,8
+       sextb   r2
+
+       # Construct -120 using movi+not
+       movi    r7,119
+       not     r7
+
+       # Compare them, they should be equal
+       cmpne   r2,r7
+       jbt     .L1
+       pass
+.L1:
+       fail
+
+
+
+

diff --git a/sim/testsuite/mcore/sexth.s b/sim/testsuite/mcore/sexth.s
new file mode 100644 (file)
index 0000000..97279c4
--- /dev/null
+++ b/sim/testsuite/mcore/sexth.s
@@ -0,0 +1,27 @@
+# check that sext.b/sext.h work correctly
+# mach: mcore
+
+.include "testutils.inc"
+
+       start
+       # Construct -32760 using bgeni+addi+sext
+       bgeni   r2, 15
+       addi    r2,8
+       sexth   r2
+
+       # Construct -32760 using bmask+subi+not
+        bmaski  r7,15
+        subi    r7,8    // 32759 0x7ff7
+       not     r7
+
+
+       # Compare them, they should be equal
+       cmpne   r2,r7
+       jbt     .L1
+       pass
+.L1:
+       fail
+
+
+
+