i386: Emulate MMX mmx_uavgv4hi3 with SSE

Emulate MMX mmx_uavgv4hi3 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
	TARGET_MMX_WITH_SSE.
	(*mmx_uavgv4hi3): Add SSE emulation.

From-SVN: r271236

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0857df4a3a590a25d249660292fd7e4cbb3f2316..eefdecdb602e5e8ebaff52eba7d66b4797638af1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89021
+       * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
+       TARGET_MMX_WITH_SSE.
+       (*mmx_uavgv4hi3): Add SSE emulation.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/89021

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 9f14d0d015d6e9eae25083111b1c6e266360c3dd..338f77e59f8ac4e2ee1bb007c7cad1f3904865e2 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1761,33 +1761,39 @@
            (plus:V4SI
              (plus:V4SI
                (zero_extend:V4SI
-                 (match_operand:V4HI 1 "nonimmediate_operand"))
+                 (match_operand:V4HI 1 "register_mmxmem_operand"))
                (zero_extend:V4SI
-                 (match_operand:V4HI 2 "nonimmediate_operand")))
+                 (match_operand:V4HI 2 "register_mmxmem_operand")))
              (const_vector:V4SI [(const_int 1) (const_int 1)
                                  (const_int 1) (const_int 1)]))
            (const_int 1))))]
-  "TARGET_SSE || TARGET_3DNOW_A"
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && (TARGET_SSE || TARGET_3DNOW_A)"
   "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
 
 (define_insn "*mmx_uavgv4hi3"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
        (truncate:V4HI
          (lshiftrt:V4SI
            (plus:V4SI
              (plus:V4SI
                (zero_extend:V4SI
-                 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+                 (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv"))
                (zero_extend:V4SI
-                 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+                 (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))
              (const_vector:V4SI [(const_int 1) (const_int 1)
                                  (const_int 1) (const_int 1)]))
            (const_int 1))))]
-  "(TARGET_SSE || TARGET_3DNOW_A)
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && (TARGET_SSE || TARGET_3DNOW_A)
    && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
-  "pavgw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxshft")
-   (set_attr "mode" "DI")])
+  "@
+   pavgw\t{%2, %0|%0, %2}
+   pavgw\t{%2, %0|%0, %2}
+   vpavgw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxshft,sseiadd,sseiadd")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "mmx_psadbw"
   [(set (match_operand:V1DI 0 "register_operand" "=y")