]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
rockchip: rk3588: Map SCMI shared memory area as non-cacheable
authorJonas Karlman <jonas@kwiboo.se>
Sun, 16 Nov 2025 01:45:29 +0000 (01:45 +0000)
committerTom Rini <trini@konsulko.com>
Mon, 24 Nov 2025 13:40:08 +0000 (07:40 -0600)
The SCMI shared memory area is no longer automatically marked as
non-cacheable after the commit a5a0134570c8 ("firmware: scmi: Drop
mmu_set_region_dcache_behaviour() misuse").

This change in behavior cause Rockchip RK3588 boards to fail boot with:

  SoC:   RK3588
  DRAM:  8 GiB
  scmi-over-smccc scmi: Channel unexpectedly busy
  scmi_base_drv scmi-base.0: getting protocol version failed
  scmi-over-smccc scmi: failed to probe base protocol
  initcall_run_r(): initcall initr_dm() failed
  ### ERROR ### Please RESET the board ###

Update the memory mapping on RK3588 to mark the SCMI shared memory area
as non-cacheable to fix the SCMI shared memory based transport issue
that prevented RK3588 boards from booting.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/rk3588/rk3588.c

index c01a400208960b3db4dc43e317c31c247b72c7b6..55d2caab4fecdf67e15841ace4a4a89b256df3a0 100644 (file)
@@ -63,7 +63,20 @@ static struct mm_region rk3588_mem_map[] = {
        {
                .virt = 0x0UL,
                .phys = 0x0UL,
-               .size = 0xf0000000UL,
+               .size = 0x10f000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               /* SCMI shared memory area must be mapped as non-cacheable. */
+               .virt = 0x10f000UL,
+               .phys = 0x10f000UL,
+               .size = 0x1000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x110000UL,
+               .phys = 0x110000UL,
+               .size = 0xefef0000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
                         PTE_BLOCK_INNER_SHARE
        }, {