gas/testsuite/

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.s: Add tests for movq.
	* gas/i386/x86_64.s: Likewise.

	* gas/i386/i386.d Updated.
	* gas/i386/x86_64.d: Likewise.

opcodes/

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 03e19d03fccc37edfa68bc50edf8b7fe6539045c..5c6e1e2ca88d8a288738a299cc5be8fc1c350252 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/i386/i386.s: Add tests for movq.
+       * gas/i386/x86_64.s: Likewise.
+
+       * gas/i386/i386.d Updated.
+       * gas/i386/x86_64.d: Likewise.
+
 2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/5534

diff --git a/gas/testsuite/gas/i386/i386.d b/gas/testsuite/gas/i386/i386.d
index fbdcb219c59a095844bc9d7a8b2fff4d7a9cfe51..ddfc5229c8b99539843a6840b513bb02c2f82058 100644 (file)
--- a/gas/testsuite/gas/i386/i386.d
+++ b/gas/testsuite/gas/i386/i386.d
@@ -25,3 +25,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f b6 10                movzbl \(%eax\),%edx
 [      ]*[a-f0-9]+:    66 0f b6 10             movzbw \(%eax\),%dx
 [      ]*[a-f0-9]+:    0f b7 10                movzwl \(%eax\),%edx
+[      ]*[a-f0-9]+:    f3 0f 7e 0c 24          movq   \(%esp\),%xmm1
+[      ]*[a-f0-9]+:    f3 0f 7e 0c 24          movq   \(%esp\),%xmm1
+[      ]*[a-f0-9]+:    66 0f d6 0c 24          movq   %xmm1,\(%esp\)
+[      ]*[a-f0-9]+:    66 0f d6 0c 24          movq   %xmm1,\(%esp\)
+#pass

diff --git a/gas/testsuite/gas/i386/i386.s b/gas/testsuite/gas/i386/i386.s
index 077664d0df7f831c0a56c6ae4201f00103b76f1f..8eb5e53f3be50216dd23e09490d21d85dac60d74 100644 (file)
--- a/gas/testsuite/gas/i386/i386.s
+++ b/gas/testsuite/gas/i386/i386.s
@@ -24,3 +24,8 @@
        movzx   edx,BYTE PTR [eax]
        movzx   dx,BYTE PTR [eax]
        movzx   edx,WORD PTR [eax]
+
+       movq    xmm1,QWORD PTR [esp]
+       movq    xmm1,[esp]
+       movq    QWORD PTR [esp],xmm1
+       movq    [esp],xmm1

diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index cdae47f062bf56bfdbc845509734bba3c981450c..b21d0af08d6692771ef069f5174d87c784eafcf6 100644 (file)
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -187,5 +187,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 0f b6 10             movzbw \(%rax\),%dx
 [      ]*[a-f0-9]+:    0f b7 10                movzwl \(%rax\),%edx
 [      ]*[a-f0-9]+:    48 0f b7 10             movzwq \(%rax\),%rdx
-       ...
+[      ]*[a-f0-9]+:    f3 0f 7e 0c 24          movq   \(%rsp\),%xmm1
+[      ]*[a-f0-9]+:    f3 0f 7e 0c 24          movq   \(%rsp\),%xmm1
+[      ]*[a-f0-9]+:    66 0f d6 0c 24          movq   %xmm1,\(%rsp\)
+[      ]*[a-f0-9]+:    66 0f d6 0c 24          movq   %xmm1,\(%rsp\)
 #pass

diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s
index d4e9d5d79eaf24184ea3fdc71264f1ec3cc2bad6..fbf4b31fc6fcba3fdfa4213ddae6ff8d19c747d9 100644 (file)
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -228,5 +228,10 @@ cmpxchg16b oword ptr [rax]
        movzx   edx,WORD PTR [rax]
        movzx   rdx,WORD PTR [rax]
 
+       movq    xmm1,QWORD PTR [rsp]
+       movq    xmm1,[rsp]
+       movq    QWORD PTR [rsp],xmm1
+       movq    [rsp],xmm1
+
 # Get a good alignment.
  .p2align      4,0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ba93eefda1d97232f0c35a56d3d21fa638df6912..23ad98c45f142f4b20e2b083d6d8c001b4af4dd0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.h: Update comments.
+
 2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 90387306d57f986cb64a894932a62e1c602cfafd..c77ae3c9ada45abd9c4037e5ba2bdeda748a46d2 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -175,7 +175,8 @@ typedef union i386_cpu_flags
 #define Size32                 (Size16 + 1)
 /* needs size prefix if in 64-bit mode */
 #define Size64                 (Size32 + 1)
-/* instruction ignores operand size prefix and mnemonic size suffix */
+/* instruction ignores operand size prefix and in Intel mode ignores
+   mnemonic size suffix check.  */
 #define IgnoreSize             (Size64 + 1)
 /* default insn size depends on mode */
 #define DefaultSize            (IgnoreSize + 1)
@@ -193,18 +194,17 @@ typedef union i386_cpu_flags
 #define No_ldSuf               (No_qSuf + 1)
 /* x suffix on instruction illegal */
 #define No_xSuf                        (No_ldSuf + 1)
-/* check PTR size on instruction in Intel mode.
-   FIXME: Can it be merged with IgnoreSize? */
+/* check memory size on instruction in Intel mode if it is specified.  */
 #define CheckSize              (No_xSuf + 1)
-/* BYTE PTR on instruction */
+/* BYTE memory on instruction */
 #define Byte                   (CheckSize + 1)
-/* WORD PTR on instruction */
+/* WORD memory on instruction */
 #define Word                   (Byte + 1)
-/* DWORD PTR on instruction */
+/* DWORD memory on instruction */
 #define Dword                  (Word + 1)
-/* QWORD PTR on instruction */
+/* QWORD memory on instruction */
 #define Qword                  (Dword + 1)
-/* XMMWORD PTR on instruction */
+/* XMMWORD memory on instruction */
 #define Xmmword                        (Qword + 1)
 /* instruction needs FWAIT */
 #define FWait                  (Xmmword + 1)