drm/amd/powerplay: add interface to get uclk dpm table

dc needs get uclk dpm table for bandwidth calculation

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8acc179735778b7aa271b06c4b77b4c9a764e127..ccb41fc4f74fdf04156106f527f2c2165bcd0b26 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -611,6 +611,7 @@ struct pptable_funcs {
                                             enum smu_clk_type clk_type,
                                             uint32_t *value);
        int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
+       int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
 };
 
 struct smu_funcs
@@ -897,6 +898,8 @@ struct smu_funcs
        ((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
 #define smu_set_azalia_d3_pme(smu) \
        ((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+       ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
 
 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
                                   uint16_t *size, uint8_t *frev, uint8_t *crev,

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index b16ee40da7c832e54fb2e31f9d6f4cbf994b7fa8..5b4332392cf59b0c0e6435c35c472f936f96d0d6 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1248,6 +1248,35 @@ static int navi10_read_sensor(struct smu_context *smu,
        return ret;
 }
 
+static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
+{
+       uint32_t num_discrete_levels = 0;
+       uint16_t *dpm_levels = NULL;
+       uint16_t i = 0;
+       struct smu_table_context *table_context = &smu->smu_table;
+       PPTable_t *driver_ppt = NULL;
+
+       if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
+               return -EINVAL;
+
+       driver_ppt = table_context->driver_pptable;
+       num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
+       dpm_levels = driver_ppt->FreqTableUclk;
+
+       if (num_discrete_levels == 0 || dpm_levels == NULL)
+               return -EINVAL;
+
+       *num_states = num_discrete_levels;
+       for (i = 0; i < num_discrete_levels; i++) {
+               /* convert to khz */
+               *clocks_in_khz = (*dpm_levels) * 1000;
+               clocks_in_khz++;
+               dpm_levels++;
+       }
+
+       return 0;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
        .tables_init = navi10_tables_init,
        .alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1281,6 +1310,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
        .set_watermarks_table = navi10_set_watermarks_table,
        .read_sensor = navi10_read_sensor,
+       .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)