bfd/

	* archures.c (bfd_mach_mips_loongson_3a): Defined.
	* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
	* cpu-mips.c (I_loongson_3a): New add.
	(arch_info_struct): Add loongson_3a.
	* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
	(mips_set_isa_flags): Add loongson_3a.
	(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.

	binutils/
	* readelf.c (get_machine_flags): Add loongson-3a.

	gas/
	* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
	* doc/c-mips.texi (MIPS cpu): Add loongson3a.

	include/
	* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
	* opcode/mips.h (INSN_LOONGSON_3A): Defined.
	(CPU_LOONGSON_3A): Defined.
	(OPCODE_IS_MEMBER): Add LOONGSON_3A.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add loongson3a.
	* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
	(mips_builtin_opcodes): Modify some instructions' membership from
	IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index e87744af709cea2cc4f0b58af2471a7ecd8d0fd5..aab75e9f868881aa7eff4c7404af04305f564aca 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,13 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * archures.c (bfd_mach_mips_loongson_3a): Defined.
+       * bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
+       * cpu-mips.c (I_loongson_3a): New add.
+       (arch_info_struct): Add loongson_3a.
+       * elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
+       (mips_set_isa_flags): Add loongson_3a.
+       (mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
+
 2010-11-10  Richard Sandiford  <richard.sandiford@linaro.org>
 
        * elf32-arm.c (elf32_arm_merge_eabi_attributes): Remove unused

diff --git a/bfd/archures.c b/bfd/archures.c
index 1867154382141e67399d19415338ac1af995d789..1d61ae3109afc9312d88629d2a5b5e9268175310 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -173,6 +173,7 @@ DESCRIPTION
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips_loongson_2e      3001
 .#define bfd_mach_mips_loongson_2f      3002
+.#define bfd_mach_mips_loongson_3a      3003
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .#define bfd_mach_mips_octeon          6501
 .#define bfd_mach_mips_xlr              887682   {* decimal 'XLR'  *}

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index f3e2b457913fe2a4a045e3fd74871c14f4a614c2..e7805b61392f0d87bcfd2ad4cf8eaae16c30147c 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1860,6 +1860,7 @@ enum bfd_architecture
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips_loongson_2e      3001
 #define bfd_mach_mips_loongson_2f      3002
+#define bfd_mach_mips_loongson_3a      3003
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
 #define bfd_mach_mips_octeon           6501
 #define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 4718dd4db6734c19b4ff007113558d3105e11adc..cfbb06e7a195c255fd7a90a1c1e751dabb05448f 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -5946,6 +5946,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_LS2F:
       return bfd_mach_mips_loongson_2f;
 
+    case E_MIPS_MACH_LS3A:
+      return bfd_mach_mips_loongson_3a;
+
     case E_MIPS_MACH_OCTEON:
       return bfd_mach_mips_octeon;
 
@@ -10556,6 +10559,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
       break;
 
+    case bfd_mach_mips_loongson_3a:
+      val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
+      break;
+
     case bfd_mach_mips_sb1:
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
       break;
@@ -12258,6 +12265,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
   { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
   { bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
   { bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
+  { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64 },
 
   /* MIPS V extensions.  */
   { bfd_mach_mipsisa64, bfd_mach_mips5 },

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index bacb077779637a80b7e30c8c285a41e78ec1da3f..7f32615adc9a76bd563fb0af4cffa7abc15c00a1 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * readelf.c (get_machine_flags): Add loongson-3a.
+
 2010-11-10  Nick Clifton  <nickc@redhat.com>
 
        * po/ja.po: Updated Japanese translation.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index 0ed5c7c1ed4880b0b161e8f5d12029fd11236205..22ca25c558b22a3452c13359d8baf978a35c99bb 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2427,6 +2427,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
            case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
            case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
            case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
+           case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
            case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
            case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
            case E_MIPS_MACH_XLR:  strcat (buf, ", xlr"); break;

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9fee27310388a08198efd08ceb62cb82ecfacfa6..732a72640d130b7abb0f0725b091d457e47a0ac4 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
+       * doc/c-mips.texi (MIPS cpu): Add loongson3a.
+
 2010-11-10  Richard Sandiford  <richard.sandiford@linaro.org>
 
        * config/tc-arm.c (do_t_branch): Treat (PLT) branches as wide.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9fa4ccee18a82f28d959ab2cb2eb51513f448063..ddeb51356ad5a6c245a7ae48500414c1c3f64c35 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -15359,6 +15359,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "5kf",            0,                       ISA_MIPS64,     CPU_MIPS64 },
   { "20kc",           MIPS_CPU_ASE_MIPS3D,     ISA_MIPS64,     CPU_MIPS64 },
   { "25kf",           MIPS_CPU_ASE_MIPS3D,     ISA_MIPS64,     CPU_MIPS64 },
+  { "loongson3a",     0,                       ISA_MIPS64,     CPU_LOONGSON_3A },
 
   /* Broadcom SB-1 CPU core */
   { "sb1",            MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 715091eff60d218ac60fa81eee2ba04d8abf3b76..974a3f097de133d62f0e98e3842318bfc016d0fd 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -303,6 +303,7 @@ sb1,
 sb1a,
 loongson2e,
 loongson2f,
+loongson3a,
 octeon,
 xlr
 @end quotation

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 39de1ff9feafb9974253bd8bb580085d3e413c5f..47a884e210b7f806db00faaf489a9b0dcd8fd9d5 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * mips.h (E_MIPS_MACH_LS3A): Defined.
+
 2010-11-02  Joseph Myers  <joseph@codesourcery.com>
 
        * tic6x-attrs.h (Tag_ABI_wchar_t, Tag_ABI_stack_align_needed,

diff --git a/include/elf/mips.h b/include/elf/mips.h
index 6f0c022122e2c306672db3d548111996022b2907..c60e8fe24ba3eda04b957d6e180f0655ba8bf61f 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -222,6 +222,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_9000       0x00990000
 #define E_MIPS_MACH_LS2E        0x00A00000
 #define E_MIPS_MACH_LS2F        0x00A10000
+#define E_MIPS_MACH_LS3A        0x00A20000
 \f
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index d7e7c626871c5e7ec76ebef710c70fa27c5d609b..fa689e599af0f977167cfb27d134b82703c678ef 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * mips.h (INSN_LOONGSON_3A): Defined.
+       (CPU_LOONGSON_3A): Defined.
+       (OPCODE_IS_MEMBER): Add LOONGSON_3A.
+
 2010-10-09  Matt Rice  <ratmice@gmail.com>
 
        * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 2fb96720be9a447d9851ff8c076f7ec200ad1800..8817ce302bb094e8f01dba22f3644ce26054acd7 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -594,6 +594,8 @@ static const unsigned int mips_isa_table[] =
 #define INSN_LOONGSON_2E          0x40000000
 /* ST Microelectronics Loongson 2F.  */
 #define INSN_LOONGSON_2F          0x80000000
+/* Loongson 3A.  */
+#define INSN_LOONGSON_3A          0x80000400
 /* RMI Xlr instruction */
 #define INSN_XLR                 0x00000020
 
@@ -647,6 +649,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
+#define CPU_LOONGSON_3A 3003
 #define CPU_OCTEON     6501
 #define CPU_XLR        887682          /* decimal 'XLR'   */
 
@@ -680,6 +683,8 @@ static const unsigned int mips_isa_table[] =
          && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
      || (cpu == CPU_LOONGSON_2F                                         \
          && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
+     || (cpu == CPU_LOONGSON_3A                                         \
+         && ((insn)->membership & INSN_LOONGSON_3A) != 0)               \
      || (cpu == CPU_OCTEON                                             \
         && ((insn)->membership & INSN_OCTEON) != 0)                    \
      || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 74ed7e676561c6ee11969409f46bed074e0bf9cf..519d40689fea41f5ec7901e32a8cde4c51dd457a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+       * mips-dis.c (mips_arch_choices): Add loongson3a.
+       * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
+       (mips_builtin_opcodes): Modify some instructions' membership from
+       IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
+
 2010-11-10  Nick Clifton  <nickc@redhat.com>
 
        * po/fi.po: Updated Finnish translation.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index c0cfed671ed8422d48dbfe0ae0c1e02d2f25a8e7..a528e9650e7cab04e66116ecb66bccb94b0ebede 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -512,6 +512,10 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 
     NULL, 0, mips_hwr_names_numeric },
 
+  { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
+    ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric, 
+    NULL, 0, mips_hwr_names_numeric },
+
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
     mips_hwr_names_numeric },

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 7a3666655c08bcac554b7290b815cf3df03ac08a..0fa86c6f279b934d7ccc276408eded172bb1d312 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -107,6 +107,7 @@
 
 #define IL2E    (INSN_LOONGSON_2E)
 #define IL2F    (INSN_LOONGSON_2F)
+#define IL3A    (INSN_LOONGSON_3A)
 
 #define P3     INSN_4650
 #define L1     INSN_4010
@@ -1860,123 +1861,123 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmodu.g",    "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
 {"dmodu.g",    "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
 {"packsshb",   "D,S,T",        0x47400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"packsshb",   "D,S,T",        0x4b400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packsshb",   "D,S,T",        0x4b400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"packsswh",   "D,S,T",        0x47200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"packsswh",   "D,S,T",        0x4b200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packsswh",   "D,S,T",        0x4b200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"packushb",   "D,S,T",        0x47600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"packushb",   "D,S,T",        0x4b600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packushb",   "D,S,T",        0x4b600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddb",      "D,S,T",        0x47c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddb",      "D,S,T",        0x4bc00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddb",      "D,S,T",        0x4bc00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddh",      "D,S,T",        0x47400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddh",      "D,S,T",        0x4b400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddh",      "D,S,T",        0x4b400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddw",      "D,S,T",        0x47600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddw",      "D,S,T",        0x4b600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddw",      "D,S,T",        0x4b600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddd",      "D,S,T",        0x47e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddd",      "D,S,T",        0x4be00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddd",      "D,S,T",        0x4be00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddsb",     "D,S,T",        0x47800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddsb",     "D,S,T",        0x4b800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsb",     "D,S,T",        0x4b800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddsh",     "D,S,T",        0x47000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddsh",     "D,S,T",        0x4b000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsh",     "D,S,T",        0x4b000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddusb",    "D,S,T",        0x47a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddusb",    "D,S,T",        0x4ba00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddusb",    "D,S,T",        0x4ba00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"paddush",    "D,S,T",        0x47200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"paddush",    "D,S,T",        0x4b200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddush",    "D,S,T",        0x4b200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pandn",      "D,S,T",        0x47e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pandn",      "D,S,T",        0x4be00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pandn",      "D,S,T",        0x4be00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pavgb",      "D,S,T",        0x46600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pavgb",      "D,S,T",        0x4b200008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgb",      "D,S,T",        0x4b200008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pavgh",      "D,S,T",        0x46400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pavgh",      "D,S,T",        0x4b000008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgh",      "D,S,T",        0x4b000008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpeqb",    "D,S,T",        0x46c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpeqb",    "D,S,T",        0x4b800009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqb",    "D,S,T",        0x4b800009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpeqh",    "D,S,T",        0x46800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpeqh",    "D,S,T",        0x4b400009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqh",    "D,S,T",        0x4b400009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpeqw",    "D,S,T",        0x46400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpeqw",    "D,S,T",        0x4b000009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqw",    "D,S,T",        0x4b000009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpgtb",    "D,S,T",        0x46e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpgtb",    "D,S,T",        0x4ba00009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtb",    "D,S,T",        0x4ba00009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpgth",    "D,S,T",        0x46a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpgth",    "D,S,T",        0x4b600009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgth",    "D,S,T",        0x4b600009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pcmpgtw",    "D,S,T",        0x46600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pcmpgtw",    "D,S,T",        0x4b200009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtw",    "D,S,T",        0x4b200009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pextrh",     "D,S,T",        0x45c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pextrh",     "D,S,T",        0x4b40000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pextrh",     "D,S,T",        0x4b40000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pinsrh_0",   "D,S,T",        0x47800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pinsrh_0",   "D,S,T",        0x4b800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_0",   "D,S,T",        0x4b800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pinsrh_1",   "D,S,T",        0x47a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pinsrh_1",   "D,S,T",        0x4ba00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_1",   "D,S,T",        0x4ba00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pinsrh_2",   "D,S,T",        0x47c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pinsrh_2",   "D,S,T",        0x4bc00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_2",   "D,S,T",        0x4bc00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pinsrh_3",   "D,S,T",        0x47e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pinsrh_3",   "D,S,T",        0x4be00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_3",   "D,S,T",        0x4be00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmaddhw",    "D,S,T",        0x45e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmaddhw",    "D,S,T",        0x4b60000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaddhw",    "D,S,T",        0x4b60000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmaxsh",     "D,S,T",        0x46800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmaxsh",     "D,S,T",        0x4b400008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxsh",     "D,S,T",        0x4b400008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmaxub",     "D,S,T",        0x46c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmaxub",     "D,S,T",        0x4b800008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxub",     "D,S,T",        0x4b800008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pminsh",     "D,S,T",        0x46a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pminsh",     "D,S,T",        0x4b600008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminsh",     "D,S,T",        0x4b600008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pminub",     "D,S,T",        0x46e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pminub",     "D,S,T",        0x4ba00008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminub",     "D,S,T",        0x4ba00008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmovmskb",   "D,S",          0x46a00005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
-{"pmovmskb",   "D,S",          0x4ba0000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"pmovmskb",   "D,S",          0x4ba0000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F|IL3A       },
 {"pmulhuh",    "D,S,T",        0x46e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmulhuh",    "D,S,T",        0x4ba0000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmulhuh",    "D,S,T",        0x4ba0000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmulhh",     "D,S,T",        0x46a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmulhh",     "D,S,T",        0x4b60000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmulhh",     "D,S,T",        0x4b60000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmullh",     "D,S,T",        0x46800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmullh",     "D,S,T",        0x4b40000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmullh",     "D,S,T",        0x4b40000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pmuluw",     "D,S,T",        0x46c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pmuluw",     "D,S,T",        0x4b80000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmuluw",     "D,S,T",        0x4b80000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"pasubub",    "D,S,T",        0x45a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pasubub",    "D,S,T",        0x4b20000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pasubub",    "D,S,T",        0x4b20000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"biadd",      "D,S",          0x46800005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
-{"biadd",      "D,S",          0x4b80000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"biadd",      "D,S",          0x4b80000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F|IL3A       },
 {"pshufh",     "D,S,T",        0x47000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"pshufh",     "D,S,T",        0x4b000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pshufh",     "D,S,T",        0x4b000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psllh",      "D,S,T",        0x46600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psllh",      "D,S,T",        0x4b20000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllh",      "D,S,T",        0x4b20000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psllw",      "D,S,T",        0x46400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psllw",      "D,S,T",        0x4b00000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllw",      "D,S,T",        0x4b00000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psrah",      "D,S,T",        0x46a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psrah",      "D,S,T",        0x4b60000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrah",      "D,S,T",        0x4b60000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psraw",      "D,S,T",        0x46800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psraw",      "D,S,T",        0x4b40000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psraw",      "D,S,T",        0x4b40000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psrlh",      "D,S,T",        0x46600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psrlh",      "D,S,T",        0x4b20000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlh",      "D,S,T",        0x4b20000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psrlw",      "D,S,T",        0x46400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psrlw",      "D,S,T",        0x4b00000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlw",      "D,S,T",        0x4b00000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubb",      "D,S,T",        0x47c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubb",      "D,S,T",        0x4bc00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubb",      "D,S,T",        0x4bc00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubh",      "D,S,T",        0x47400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubh",      "D,S,T",        0x4b400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubh",      "D,S,T",        0x4b400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubw",      "D,S,T",        0x47600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubw",      "D,S,T",        0x4b600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubw",      "D,S,T",        0x4b600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubd",      "D,S,T",        0x47e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubd",      "D,S,T",        0x4be00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubd",      "D,S,T",        0x4be00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubsb",     "D,S,T",        0x47800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubsb",     "D,S,T",        0x4b800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsb",     "D,S,T",        0x4b800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubsh",     "D,S,T",        0x47000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubsh",     "D,S,T",        0x4b000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsh",     "D,S,T",        0x4b000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubusb",    "D,S,T",        0x47a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubusb",    "D,S,T",        0x4ba00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubusb",    "D,S,T",        0x4ba00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"psubush",    "D,S,T",        0x47200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"psubush",    "D,S,T",        0x4b200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubush",    "D,S,T",        0x4b200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpckhbh",  "D,S,T",        0x47600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpckhbh",  "D,S,T",        0x4b600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhbh",  "D,S,T",        0x4b600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpckhhw",  "D,S,T",        0x47200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpckhhw",  "D,S,T",        0x4b200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhhw",  "D,S,T",        0x4b200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpckhwd",  "D,S,T",        0x46e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpckhwd",  "D,S,T",        0x4ba0000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhwd",  "D,S,T",        0x4ba0000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpcklbh",  "D,S,T",        0x47400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpcklbh",  "D,S,T",        0x4b400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklbh",  "D,S,T",        0x4b400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpcklhw",  "D,S,T",        0x47000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpcklhw",  "D,S,T",        0x4b000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklhw",  "D,S,T",        0x4b000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"punpcklwd",  "D,S,T",        0x46c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
-{"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F|IL3A       },
 {"sequ",       "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
-{"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
+{"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F|IL3A       },
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the