PR 10186

        * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
        instruction.

        * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.

        * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
        instruction.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5ddad8d5f1693af18f9af53b0b8ae6adc87da6cc..04e73ad94466ad997e112a4e3a10228ee2107b09 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2009-06-15  Nick Clifton  <nickc@redhat.com>
+
+       PR 10186
+       * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
+       instruction.
+
 2009-06-13  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/10269

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index eaaaf06faf48a4c2b712cc711789086c6b66858c..67d8cc998f720ecdaa58990fb3f6847bafd46de4 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8429,7 +8429,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(yield, bf10, f3af8001),                    \
   X(wfe,   bf20, f3af8002),                    \
   X(wfi,   bf30, f3af8003),                    \
-  X(sev,   bf40, f3af9004), /* typo, 8004? */
+  X(sev,   bf40, f3af8004), 
 
 /* To catch errors in encoding functions, the codes are all offset by
    0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2d92d0575de8607e840e128d8280a126b64558b6..b2fba43ebe0507d911e524493494f4c9c2fbe7c4 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-06-15  Nick Clifton  <nickc@redhat.com>
+
+       PR gas/10186
+       * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.
+
 2009-06-09  Jakub Jelinek  <jakub@redhat.com>
 
        PR gas/10255

diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index c508b2129e141f99b3d403af4a5879dc6cb00c6d..9637022b2d68538efbc4c615f4db590418f3986a 100644 (file)
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -359,7 +359,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3af 8001   yield\.w
 0[0-9a-f]+ <[^>]+> f3af 8002   wfe\.w
 0[0-9a-f]+ <[^>]+> f3af 8003   wfi\.w
-0[0-9a-f]+ <[^>]+> f3af 9004   sev\.w
+0[0-9a-f]+ <[^>]+> f3af 8004   sev\.w
 0[0-9a-f]+ <[^>]+> bf90        nop     \{9\}
 0[0-9a-f]+ <[^>]+> f3af 8081   nop\.w  \{129\}
 0[0-9a-f]+ <[^>]+> bf08        it      eq

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5fd7db07162c97d81f0d4bca15d6c6834a0475a5..05966313ada8cb3c189af85ea6a639e48c055df0 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
 2009-06-15  Nick Clifton  <nickc@redhat.com>
 
+       PR 10186
+       * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
+       instruction.
+
        PR 10173
        * cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.
 

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index cb3bc9985157090a387ed623d5fe737a6dbfcdbf..ce724a5f6a792efad839db1597aa0d7408ff8453 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1245,7 +1245,7 @@ static const struct opcode32 thumb32_opcodes[] =
   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
-  {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
+  {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
 
   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},