From: Nathan Sidwell <nathan@codesourcery.com>
Date: Fri, 27 Apr 2007 16:24:18 +0000 (+0000)
Subject: 	* ld-m68k/plt1-isac.d: New.
X-Git-Tag: binutils-2_18-branchpoint~927
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=353a0210f9176de1be2638d3774d9b6e93b89aa0;p=thirdparty%2Fbinutils-gdb.git

	* ld-m68k/plt1-isac.d: New.
	* ld-m68k/m68k.exp: Add it.
---

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index ed2466c8e23..885b706dec1 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2007-04-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-m68k/plt1-isac.d: New.
+	* ld-m68k/m68k.exp: Add it.
+
 2007-04-26  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/4430
diff --git a/ld/testsuite/ld-m68k/m68k.exp b/ld/testsuite/ld-m68k/m68k.exp
index ca096f5fac1..bf89a607c12 100644
--- a/ld/testsuite/ld-m68k/m68k.exp
+++ b/ld/testsuite/ld-m68k/m68k.exp
@@ -56,7 +56,7 @@ run_dump_test "merge-ok-1b"
 run_dump_test "merge-ok-1c"
 
 foreach { id sources } { a { plt1.s } b { plt1-empty.s plt1.s } } {
-    foreach arch { 68020 cpu32 isab } {
+    foreach arch { 68020 cpu32 isab isac } {
 	run_ld_link_tests [list \
 	    [list "PLT 1$id ($arch)" "-shared -T plt1.ld" "-m$arch" \
 		 $sources [list [list objdump -dr plt1-$arch.d]] \
diff --git a/ld/testsuite/ld-m68k/plt1-isac.d b/ld/testsuite/ld-m68k/plt1-isac.d
new file mode 100644
index 00000000000..ae299ce92b3
--- /dev/null
+++ b/ld/testsuite/ld-m68k/plt1-isac.d
@@ -0,0 +1,44 @@
+
+.*:     file format elf32-m68k
+
+Disassembly of section \.plt:
+
+00020800 <f.@plt-0x18>:
+# _GLOBAL_OFFSET_TABLE_ + 4 == 0x30404 == 0x20802 + 0xfc02
+   20800:	203c 0000 fc02 	movel #64514,%d0
+   20806:	2ebb 08fa      	movel %pc@\(20802 <f.@plt-0x16>,%d0:l\),%sp@
+# _GLOBAL_OFFSET_TABLE_ + 8 == 0x30408 == 0x2080c + 0xfbfc
+   2080a:	203c 0000 fbfc 	movel #64508,%d0
+   20810:	207b 08fa      	moveal %pc@\(2080c <f.@plt-0xc>,%d0:l\),%a0
+   20814:	4ed0           	jmp %a0@
+   20816:	4e71           	nop
+
+00020818 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 12 == 0x3040c == 0x2081a + 0xfbf2
+   20818:	203c 0000 fbf2 	movel #64498,%d0
+   2081e:	207b 08fa      	moveal %pc@\(2081a <f.@plt\+0x2>,%d0:l\),%a0
+   20822:	4ed0           	jmp %a0@
+   20824:	2f3c 0000 0000 	movel #0,%sp@-
+   2082a:	61ff ffff ffd4 	bsrl 20800 <f.@plt-0x18>
+
+00020830 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 16 == 0x30410 == 0x20832 + 0xfbde
+   20830:	203c 0000 fbde 	movel #64478,%d0
+   20836:	207b 08fa      	moveal %pc@\(20832 <f.@plt\+0x2>,%d0:l\),%a0
+   2083a:	4ed0           	jmp %a0@
+   2083c:	2f3c 0000 000c 	movel #12,%sp@-
+   20842:	61ff ffff ffbc 	bsrl 20800 <f.@plt-0x18>
+
+00020848 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 20 == 0x30414 == 0x2084a + 0xfbca
+   20848:	203c 0000 fbca 	movel #64458,%d0
+   2084e:	207b 08fa      	moveal %pc@\(2084a <f.@plt\+0x2>,%d0:l\),%a0
+   20852:	4ed0           	jmp %a0@
+   20854:	2f3c 0000 0018 	movel #24,%sp@-
+   2085a:	61ff ffff ffa4 	bsrl 20800 <f.@plt-0x18>
+Disassembly of section \.text:
+
+00020c00 <.*>:
+   20c00:	61ff ffff fc.. 	bsrl 208.. <f1@plt>
+   20c06:	61ff ffff fc.. 	bsrl 208.. <f2@plt>
+   20c0c:	61ff ffff fc.. 	bsrl 208.. <f3@plt>