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2024-01-03  Jakub JelinekUpdate copyright years.
2023-11-09  Jin MaRISC-V: Fix the illegal operands for the XTheadMemidx...
2023-09-30  Jivan HakobyanRISC-V: Add type attribute in *<optab>_not_const<mode...
2023-09-29  Jivan HakobyanRISC-V: Replace not + bitwise_imm with li + bitwise_not
2023-09-12  Christoph Müllnerriscv: Add support for str(n)cmp inline expansion
2023-09-08  Christoph Müllnerriscv: bitmanip: Remove duplicate zero_extendhi<GPR...
2023-09-05  Jeff LawRISC-V: Expose bswapsi for TARGET_64BIT
2023-08-23  Zhangjin Liao[PATCH] RISC-V:add a more appropriate type attribute
2023-08-21  Edwin Lu[PATCH] RISC-V: Add Types to Missing Bitmanip Instructions
2023-06-07  Jeff LawRISC-V: Eliminate extension after for *w instructions
2023-05-20  Raphael Moreira... Add bext pattern for ZBS
2023-05-20  Raphael Moreira... RISC-V: Fix CTZ unnecessary sign extension [PR #106888]
2023-05-17  Jivan HakobyanRISC-V: Remove masking third operand of rotate instructions
2023-04-28  Karen SargsyanRISC-V: Added support clmul[r,h] instructions for Zbc...
2023-04-28  Jivan HakobyanRISC-V: Eliminate redundant zero extension of minu...
2023-04-26  Jivan Hakobyanavoid splitting small constants in bcrli_nottwobits...
2023-04-20  Raphael Zinsly[PR target/108248] [RISC-V] Break down some bitmanip...
2023-04-18  Sinan LinAdd TARGET_ZBKB to the condition of bswapsi2, bswapdi2...
2023-04-17  Feng WangRISC-V: Optimze the reverse conditions of rotate shift
2023-03-15  Christoph Müllnerriscv: thead: Add support for the XTheadBb ISA extension
2023-03-05  Liao ShihuaRISC-V: Implement ZBKB, ZBKC and ZBKX extensions
2023-03-05  Lin SinanRISC-V: Allow const0_rtx operand in max/min
2023-03-05  Lin SinanRISC-V: Fix wrong partial subreg check for bsetidisi
2023-01-16  Jakub JelinekUpdate copyright years.
2022-11-18  Philipp TomsichRISC-V: No extensions for SImode min/max against safe...
2022-11-18  Philipp TomsichRISC-V: Handle "(a & twobits) == singlebit" in branches...
2022-11-18  Philipp TomsichRISC-V: Use bseti/bclri/binvi to extend reach of ori...
2022-11-18  Philipp TomsichRISC-V: Optimize slli(.uw)? + addw + zext.w into sh...
2022-11-18  Philipp TomsichRISC-V: split to allow formation of sh[123]add before...
2022-11-18  Philipp TomsichRISC-V: allow bseti on SImode without sign-extension
2022-11-17  Philipp TomsichRISC-V: Optimize masking with two clear bits not a...
2022-11-17  Philipp TomsichRISC-V: bitmanip: add splitter to use bexti for "(a...
2022-11-16  Philipp TomsichRISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext...
2022-11-16  Philipp TomsichRISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext...
2022-11-14  Philipp Tomsichriscv: bitmanip: add orc.b as an unspec
2022-11-13  Philipp TomsichRISC-V: optimize '(a >= 0) ? b : 0' to srai + andn...
2022-08-24  Andrew Pinski[RISCV] Fix PR 106632 and PR 106588 a few constraints...
2022-08-24  Andrew Pinski[RISCV] Add constraints for not_single_bit_mask_operand...
2022-08-24  Andrew Pinski[RISCV] Use a constraint for bset<mode>_mask and bset...
2022-08-24  Andrew Pinski[RISCV] Use constraints/predicates instead of checking...
2022-08-24  Andrew Pinski[RISCV] Add %~ to print w if TARGET_64BIT and use it
2022-08-24  Andrew Pinski[RISCV] Move iterators from bitmanip.md to iterators.md
2022-08-24  Andrew PinskiFix PR 106601: __builtin_bswap16 code gen could be...
2022-08-24  Andrew PinskiFix PR 106600: __builtin_bswap32 is not hooked up for...
2022-06-17  Kito ChengRISC-V: Supress warning for comparison of integer expre...
2022-06-14  Philipp TomsichRISC-V: Split slli+sh[123]add.uw opportunities to avoid...
2022-01-03  Jakub JelinekUpdate copyright years.
2021-10-25  Jim WilsonRISC-V: Implement instruction patterns for ZBS extension.
2021-10-25  Jim WilsonRISC-V: Implement instruction patterns for ZBB extension.
2021-10-25  Jim WilsonRISC-V: Implement instruction patterns for ZBA extension.