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[thirdparty/gcc.git] / gcc / config / riscv / riscv-vector-switch.def

2024-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw
2023-10-21	Pan Li	RISC-V: Support partial VLS mode when preference fixed...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Juzhe-Zhong	RISC-V: Remove unreasonable TARGET_64BIT for VLS modes...	blob \| commitdiff \| raw \| diff to current
2023-07-27	Juzhe-Zhong	RISC-V: Enable basic VLS modes support	blob \| commitdiff \| raw \| diff to current
2023-07-20	Juzhe-Zhong	RISC-V: Refactor RVV machine modes	blob \| commitdiff \| raw \| diff to current
2023-07-05	yulong	RISC-V:Add float16 tuple type support	blob \| commitdiff \| raw \| diff to current
2023-06-25	Pan Li	Revert "RISC-V:Add float16 tuple type support"	blob \| commitdiff \| raw \| diff to current
2023-06-18	yulong	RISC-V:Add float16 tuple type support	blob \| commitdiff \| raw \| diff to current
2023-06-01	Pan Li	RISC-V: Introduce vfloat16m{f}*_t and their machine...	blob \| commitdiff \| raw \| diff to current
2023-05-03	Ju-Zhe Zhong	RISC-V: Add tuple types support	blob \| commitdiff \| raw \| diff to current
2023-04-19	Juzhe-Zhong	RISC-V: Support 128 bit vector chunk	blob \| commitdiff \| raw \| diff to current
2023-04-12	Ju-Zhe Zhong	RISC-V: Fix supporting data type according to RVV ISA...	blob \| commitdiff \| raw \| diff to current
2023-01-16	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2022-12-19	Ju-Zhe Zhong	RISC-V: Fix RVV machine mode attribute configuration	blob \| commitdiff \| raw \| diff to current
2022-12-01	Ju-Zhe Zhong	RISC-V: Add attributes for VSETVL PASS	blob \| commitdiff \| raw \| diff to current
2022-10-24	Ju-Zhe Zhong	RISC-V: Remove unused TI/TF vector modes.	blob \| commitdiff \| raw \| diff to current
2022-09-28	Ju-Zhe Zhong	RISC-V: Add ABI-defined RVV types.	blob \| commitdiff \| raw \| diff to current

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