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[thirdparty/gcc.git] / gcc / config / riscv / riscv.h

2024-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw
2023-11-27	Tsukasa OI	RISC-V: Initial RV64E and LP64E support	blob \| commitdiff \| raw \| diff to current
2023-11-16	Kito Cheng	RISC-V: Implement target attribute	blob \| commitdiff \| raw \| diff to current
2023-10-31	Christoph Müllner	riscv: thead: Add support for the XTheadFMemIdx ISA...	blob \| commitdiff \| raw \| diff to current
2023-10-31	Christoph Müllner	riscv: thead: Add support for the XTheadMemIdx ISA...	blob \| commitdiff \| raw \| diff to current
2023-10-13	Kito Cheng	RISC-V: Fix the riscv_legitimize_poly_move issue on...	blob \| commitdiff \| raw \| diff to current
2023-10-10	Andrew Waterman	RISC-V: far-branch: Handle far jumps and branches for...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-3: Output .variant_cc directive for vector...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-2: Save/Restore vector registers which...	blob \| commitdiff \| raw \| diff to current
2023-09-06	Lehua Ding	RISC-V: Part-1: Select suitable vector registers for...	blob \| commitdiff \| raw \| diff to current
2023-08-30	Fei Gao	RISC-V: support cm.push cm.pop cm.popret in zcmp	blob \| commitdiff \| raw \| diff to current
2023-08-29	Edwin Lu	RISC-V: generate builtin macro for compilation with...	blob \| commitdiff \| raw \| diff to current
2023-08-14	Jiawei	RISC-V: Enable compressible features when use ZC* exten...	blob \| commitdiff \| raw \| diff to current
2023-08-10	Pan Li	RISC-V: Refactor RVV frm_mode attr for rounding mode...	blob \| commitdiff \| raw \| diff to current
2023-07-20	Juzhe-Zhong	RISC-V: Refactor RVV machine modes	blob \| commitdiff \| raw \| diff to current
2023-07-12	Christoph Müllner	riscv: Prepare backend for index registers	blob \| commitdiff \| raw \| diff to current
2023-07-12	Christoph Müllner	riscv: Define Xmode macro	blob \| commitdiff \| raw \| diff to current
2023-06-29	Pan Li	RISC-V: Support vfadd static rounding mode by mode...	blob \| commitdiff \| raw \| diff to current
2023-06-13	Yanzhang Wang	RISC-V: Add vector psabi checking.	blob \| commitdiff \| raw \| diff to current
2023-05-29	Pan Li	RISC-V: Using merge approach to optimize repeating...	blob \| commitdiff \| raw \| diff to current
2023-05-17	Jin Ma	RISC-V: Remove trailing spaces on lines.	blob \| commitdiff \| raw \| diff to current
2023-05-17	Juzhe-Zhong	RISC-V: Add mode switching target hook to insert roundi...	blob \| commitdiff \| raw \| diff to current
2023-05-16	Juzhe-Zhong	RISC-V: Add FRM and rounding mode operand into floating...	blob \| commitdiff \| raw \| diff to current
2023-05-15	Juzhe-Zhong	RISC-V: Add rounding mode operand for fixed-point patterns	blob \| commitdiff \| raw \| diff to current
2023-05-05	Pan Li	RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to...	blob \| commitdiff \| raw \| diff to current
2023-04-20	Juzhe-Zhong	RISC-V: Fix RVV register order	blob \| commitdiff \| raw \| diff to current
2023-03-23	Pan Li	RISC-V: Bugfix for rvv bool mode size adjustment	blob \| commitdiff \| raw \| diff to current
2023-03-07	Pan Li	RISC-V: Bugfix for rvv bool mode precision adjustment	blob \| commitdiff \| raw \| diff to current
2023-02-13	Kito Cheng	RISC-V: Handle vlenb correctly in unwinding	blob \| commitdiff \| raw \| diff to current
2023-02-12	Ju-Zhe Zhong	RISC-V: Add integer widening instructions	blob \| commitdiff \| raw \| diff to current
2023-02-10	Ju-Zhe Zhong	RISC-V: Add binary vx C/C++ support	blob \| commitdiff \| raw \| diff to current
2023-02-03	Monk Chiang	RISC-V: Remove unnecessary register class.	blob \| commitdiff \| raw \| diff to current
2023-01-02	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2022-12-01	Ju-Zhe Zhong	RISC-V: Add duplicate vector support.	blob \| commitdiff \| raw \| diff to current
2022-11-18	Philipp Tomsich	RISC-V: Use bseti/bclri/binvi to extend reach of ori...	blob \| commitdiff \| raw \| diff to current
2022-11-11	Ju-Zhe Zhong	RISC-V: Add RVV registers register spilling	blob \| commitdiff \| raw \| diff to current
2022-10-26	Ju-Zhe Zhong	RISC-V: ADJUST_NUNITS according to -march.	blob \| commitdiff \| raw \| diff to current
2022-10-26	Ju-Zhe Zhong	RISC-V: Support load/store in mov<mode> pattern for...	blob \| commitdiff \| raw \| diff to current
2022-10-24	Ju-Zhe Zhong	RISC-V: Fix REG_CLASS_CONTENTS.	blob \| commitdiff \| raw \| diff to current
2022-10-05	Ju-Zhe Zhong	RISC-V: Introduce RVV header to enable builtin types	blob \| commitdiff \| raw \| diff to current
2022-09-23	Vineet Gupta	RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand	blob \| commitdiff \| raw \| diff to current
2022-09-02	Iain Buclaw	d: Fix #error You must define PREFERRED_DEBUGGING_TYPE...	blob \| commitdiff \| raw \| diff to current
2022-09-02	Kito Cheng	RISC-V: Implement TARGET_COMPUTE_MULTILIB	blob \| commitdiff \| raw \| diff to current
2022-09-01	zhongjuzhe	RISC-V: Fix comment in riscv.h	blob \| commitdiff \| raw \| diff to current
2022-09-01	zhongjuzhe	RISC-V: Fix riscv_vector_chunks configuration according...	blob \| commitdiff \| raw \| diff to current
2022-08-29	zhongjuzhe	RISC-V: Add RVV registers	blob \| commitdiff \| raw \| diff to current
2022-08-24	Andrew Pinski	[RISCV] Fix PR 106586: riscv32 vs ZBS	blob \| commitdiff \| raw \| diff to current
2022-08-18	zhongjuzhe	RISC-V: Add runtime invariant support	blob \| commitdiff \| raw \| diff to current
2022-06-02	Philipp Tomsich	RISC-V: bitmanip: improve constant-loading for (1ULL...	blob \| commitdiff \| raw \| diff to current
2022-05-23	Vineet Gupta	RISC-V: Enable TARGET_SUPPORTS_WIDE_INT	blob \| commitdiff \| raw \| diff to current
2022-05-13	Philipp Tomsich	RISC-V: Implement C[LT]Z_DEFINED_VALUE_AT_ZERO	blob \| commitdiff \| raw \| diff to current
2022-02-05	Kito Cheng	RISC-V: Always pass -misa-spec to assembler [PR104219]	blob \| commitdiff \| raw \| diff to current
2022-01-17	Martin Liska	Change references of .c files to .cc files	blob \| commitdiff \| raw \| diff to current
2022-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2021-10-25	Jim Wilson	RISC-V: Implement instruction patterns for ZBS extension.	blob \| commitdiff \| raw \| diff to current
2021-05-25	Kito Cheng	RISC-V: Pass -mno-relax to assembler	blob \| commitdiff \| raw \| diff to current
2021-04-30	LevyHsu	RISC-V: Add patterns for builtin overflow.	blob \| commitdiff \| raw \| diff to current
2021-04-14	Iain Buclaw	d: Add TARGET_D_REGISTER_CPU_TARGET_INFO	blob \| commitdiff \| raw \| diff to current
2021-03-23	Marcus Comstedt	RISC-V: Add riscv{32,64}be with big endian as default	blob \| commitdiff \| raw \| diff to current
2021-03-23	Marcus Comstedt	RISC-V: Support -mlittle-endian and -mbig-endian	blob \| commitdiff \| raw \| diff to current
2021-01-04	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2020-11-30	Kito Cheng	RISC-V: Always define MULTILIB_DEFAULTS	blob \| commitdiff \| raw \| diff to current
2020-11-18	Kito Cheng	RISC-V: Support version controling for ISA standard...	blob \| commitdiff \| raw \| diff to current
2020-11-14	Monk Chiang	PR target/97682 - Fix to reuse t1 register between...	blob \| commitdiff \| raw \| diff to current
2020-10-15	Kito Cheng	RISC-V: Add support for -mcpu option.	blob \| commitdiff \| raw \| diff to current
2020-09-17	Yeting Kuo	RISC-V: fix a typo in riscv.h	blob \| commitdiff \| raw \| diff to current
2020-06-22	Kito Cheng	RISC-V: Normalize arch string in driver time	blob \| commitdiff \| raw \| diff to current
2020-05-19	Kito Cheng	RISC-V: Handle implied extension for -march parser.	blob \| commitdiff \| raw \| diff to current
2020-05-12	Craig Blackmore	RISC-V: Add shorten_memrefs pass.	blob \| commitdiff \| raw \| diff to current
2020-02-08	Jim Wilson	RISC-V: Improve caller-save code generation.	blob \| commitdiff \| raw \| diff to current
2020-01-21	Kito Cheng	RISC-V: Disallow regrenme if the TO register never...	blob \| commitdiff \| raw \| diff to current
2020-01-01	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2019-10-28	Andrew Burgess	gcc/riscv: Add a mechanism to remove some calls to...	blob \| commitdiff \| raw \| diff to current
2019-10-16	Andrew Burgess	RISC-V: Include more registers in SIBCALL_REGS.	blob \| commitdiff \| raw \| diff to current
2019-07-23	Ilia Diachkov	RISC-V: Add -malign-data= option.	blob \| commitdiff \| raw \| diff to current
2019-06-27	Aaron Sawdey	builtins.c (get_memory_rtx): Fix comment.	blob \| commitdiff \| raw \| diff to current
2019-06-06	Jim Wilson	RISC-V: Move STARTFILE_PREFIX_SPEC into target OS files.	blob \| commitdiff \| raw \| diff to current
2019-04-30	Andrew Waterman	RISC-V: Short-forward-branch opt for SiFive 7 series...	blob \| commitdiff \| raw \| diff to current
2019-01-01	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2018-10-28	Iain Buclaw	Add D front-end, libphobos library, and D2 testsuite.	blob \| commitdiff \| raw \| diff to current
2018-09-26	Jim Wilson	RISC-V: Delete obsolete MIPS comment.	blob \| commitdiff \| raw \| diff to current
2018-09-25	Jim Wilson	RISC-V: Fix problems with ilp32e ABI support.	blob \| commitdiff \| raw \| diff to current
2018-05-25	Jim Wilson	RISC-V: Add interrupt attribute support.	blob \| commitdiff \| raw \| diff to current
2018-05-18	Kito Cheng	RISC-V: Add RV32E support.	blob \| commitdiff \| raw \| diff to current
2018-04-02	Jim Wilson	RISC-V: Fix for combine bug with shift and AND operations.	blob \| commitdiff \| raw \| diff to current
2018-03-19	Jim Wilson	RISC-V: Fix bootstrap failure.	blob \| commitdiff \| raw \| diff to current
2018-02-15	Jim Wilson	RISC-V: Change sp subtracts so prologue stores can...	blob \| commitdiff \| raw \| diff to current
2018-01-27	Jim Wilson	RISC-V: Allow register pairs for 64-bit target.	blob \| commitdiff \| raw \| diff to current
2018-01-23	Andrew Waterman	RISC-V: Add -mpreferred-stack-boundary option.	blob \| commitdiff \| raw \| diff to current
2018-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2017-12-04	Jim Wilson	Fix typos in riscv register save/restore.	blob \| commitdiff \| raw \| diff to current
2017-11-12	Tom de Vries	[riscv] Wrap ASM_OUTPUT_LABELREF in do {} while (0)	blob \| commitdiff \| raw \| diff to current
2017-11-08	Kito Cheng	RISC-V: Fix build error	blob \| commitdiff \| raw \| diff to current
2017-11-07	Andrew Waterman	RISC-V: Implement movmemsi	blob \| commitdiff \| raw \| diff to current
2017-11-05	Andrew Waterman	RISC-V: Set SLOW_BYTE_ACCESS=1	blob \| commitdiff \| raw \| diff to current
2017-10-23	Richard Sandiford	Convert STARTING_FRAME_OFFSET to a hook	blob \| commitdiff \| raw \| diff to current
2017-09-25	Richard Sandiford	Turn CONSTANT_ALIGNMENT into a hook	blob \| commitdiff \| raw \| diff to current
2017-09-15	Richard Sandiford	Turn TRULY_NOOP_TRUNCATION into a hook	blob \| commitdiff \| raw \| diff to current
2017-09-15	Richard Sandiford	Turn CANNOT_CHANGE_MODE_CLASS into a hook	blob \| commitdiff \| raw \| diff to current
2017-09-13	Richard Sandiford	Turn SECONDARY_MEMORY_NEEDED into a hook	blob \| commitdiff \| raw \| diff to current
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