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[thirdparty/gcc.git] / gcc / config / riscv / riscv.md

2023-01-16	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw
2022-12-27	Jeff Law	Commit right version of last patch (missing modes)	blob \| commitdiff \| raw \| diff to current
2022-12-27	Raphael Moreira...	RISC-V: Produce better code with complex constants...	blob \| commitdiff \| raw \| diff to current
2022-12-27	Christoph Müllner	riscv: attr: Synchronize comments with code	blob \| commitdiff \| raw \| diff to current
2022-11-21	Philipp Tomsich	RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equal...	blob \| commitdiff \| raw \| diff to current
2022-11-18	Philipp Tomsich	RISC-V: Optimize branches testing a bit-range or a...	blob \| commitdiff \| raw \| diff to current
2022-11-15	Philipp Tomsich	RISC-V: Zihintpause: add __builtin_riscv_pause	blob \| commitdiff \| raw \| diff to current
2022-11-14	Philipp Tomsich	riscv: bitmanip: add orc.b as an unspec	blob \| commitdiff \| raw \| diff to current
2022-10-27	Jiawei	RISC-V: Target support for z*inx extension.	blob \| commitdiff \| raw \| diff to current
2022-10-26	Ju-Zhe Zhong	RISC-V: Support load/store in mov<mode> pattern for...	blob \| commitdiff \| raw \| diff to current
2022-10-21	Monk Chiang	RISC-V: Add type attribute for atomic instructions.	blob \| commitdiff \| raw \| diff to current
2022-10-21	Ju-Zhe Zhong	RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.	blob \| commitdiff \| raw \| diff to current
2022-10-11	Ju-Zhe Zhong	RISC-V: Add missing vsetvl instruction type.	blob \| commitdiff \| raw \| diff to current
2022-09-05	Kito Cheng	RISC-V: Fix division instructions for `m` with `zmmul...	blob \| commitdiff \| raw \| diff to current
2022-09-05	LiaoShihua	RISC-V: Support Zmmul extension	blob \| commitdiff \| raw \| diff to current
2022-09-01	zhongjuzhe	RISC-V: Add csrr vlenb instruction.	blob \| commitdiff \| raw \| diff to current
2022-08-29	zhongjuzhe	RISC-V: Add RVV registers	blob \| commitdiff \| raw \| diff to current
2022-08-29	zhongjuzhe	RISC-V: Add RVV instructions classification	blob \| commitdiff \| raw \| diff to current
2022-08-24	Andrew Pinski	[RISCV] Add %~ to print w if TARGET_64BIT and use it	blob \| commitdiff \| raw \| diff to current
2022-08-24	Andrew Pinski	[RISCV] Add the list of operand modifiers to riscv...	blob \| commitdiff \| raw \| diff to current
2022-08-24	Andrew Pinski	[RISCV] Move iterators from riscv.md to iterators.md	blob \| commitdiff \| raw \| diff to current
2022-08-18	Maciej W. Rozycki	RISC-V: Standardize formatting of SFB ALU conditional...	blob \| commitdiff \| raw \| diff to current
2022-08-18	zhongjuzhe	RISC-V: Add runtime invariant support	blob \| commitdiff \| raw \| diff to current
2022-08-16	Kito Cheng	RISC-V: Support zfh and zfhmin extension	blob \| commitdiff \| raw \| diff to current
2022-08-16	Kito Cheng	RISC-V: Support _Float16 type.	blob \| commitdiff \| raw \| diff to current
2022-07-28	Maciej W. Rozycki	RISC-V: Split unordered FP comparisons into individual...	blob \| commitdiff \| raw \| diff to current
2022-07-27	Maciej W. Rozycki	RISC-V: Remove duplicate backslashes from `stack_protec...	blob \| commitdiff \| raw \| diff to current
2022-06-13	Maciej W. Rozycki	RISC-V: Reset the length to the default of 4 for FP...	blob \| commitdiff \| raw \| diff to current
2022-06-09	Maciej W. Rozycki	RISC-V: Use a tab rather than space with FSFLAGS	blob \| commitdiff \| raw \| diff to current
2022-05-24	ShiYulong	RISC-V: Cache Management Operation instructions	blob \| commitdiff \| raw \| diff to current
2022-05-10	Maciej W. Rozycki	RISC-V: Provide `fmin'/`fmax' RTL patterns	blob \| commitdiff \| raw \| diff to current
2022-01-28	Maciej W. Rozycki	RISC-V: Document `auipc' and `bitmanip' `type' attributes	blob \| commitdiff \| raw \| diff to current
2022-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2021-10-28	Kito Cheng	RISC-V: Fix wrong predicator for zero_extendsidi2_inter...	blob \| commitdiff \| raw \| diff to current
2021-10-25	Jim Wilson	RISC-V: Implement instruction patterns for ZBB extension.	blob \| commitdiff \| raw \| diff to current
2021-10-25	Jim Wilson	RISC-V: Implement instruction patterns for ZBA extension.	blob \| commitdiff \| raw \| diff to current
2021-09-28	Geng Qi	RISC-V: Pattern name fix mul3_highpart -> smul3_highpart.	blob \| commitdiff \| raw \| diff to current
2021-05-06	Christoph Muellner	RISC-V: Generate helpers for cbranch4.	blob \| commitdiff \| raw \| diff to current
2021-04-30	LevyHsu	RISC-V: Add patterns for builtin overflow.	blob \| commitdiff \| raw \| diff to current
2021-03-23	Marcus Comstedt	RISC-V: Fix matches against subreg with a bytenum of...	blob \| commitdiff \| raw \| diff to current
2021-01-04	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2020-11-18	Kito Cheng	RISC-V: Support zicsr and zifencei extension for -march.	blob \| commitdiff \| raw \| diff to current
2020-07-30	Cooper Qu	RISC-V: Add support for TLS stack protector canary...	blob \| commitdiff \| raw \| diff to current
2020-07-09	Kito Cheng	RISC-V: Implement __builtin_thread_pointer	blob \| commitdiff \| raw \| diff to current
2020-06-11	Kito Cheng	RISC-V: Unify the output asm pattern between gpr_save...	blob \| commitdiff \| raw \| diff to current
2020-06-11	Kito Cheng	RISC-V: Describe correct USEs for gpr_save pattern...	blob \| commitdiff \| raw \| diff to current
2020-05-31	Jim Wilson	RISC-V: Optimize si to di zero-extend followed by left...	blob \| commitdiff \| raw \| diff to current
2020-01-01	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2019-09-19	Jim Wilson	RISC-V: Fix more splitters accidentally calling gen_reg...	blob \| commitdiff \| raw \| diff to current
2019-09-05	Jakub Jelinek	RISC-V: Fix bad insn splits with paradoxical subregs.	blob \| commitdiff \| raw \| diff to current
2019-07-08	Jim Wilson	RISC-V: Fix splitter for 32-bit AND on 64-bit target.	blob \| commitdiff \| raw \| diff to current
2019-07-08	Richard Sandiford	[riscv] Fix ambiguous .md attribute uses	blob \| commitdiff \| raw \| diff to current
2019-06-27	Aaron Sawdey	builtins.c (get_memory_rtx): Fix comment.	blob \| commitdiff \| raw \| diff to current
2019-04-30	Andrew Waterman	RISC-V: Short-forward-branch opt for SiFive 7 series...	blob \| commitdiff \| raw \| diff to current
2019-04-27	Jim Wilson	RISC-V: Promode modes of constant loads for store insns.	blob \| commitdiff \| raw \| diff to current
2019-03-26	Andrew Waterman	RISC-V: Add sifive-7 pipeline description.	blob \| commitdiff \| raw \| diff to current
2019-01-01	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2018-10-05	Andrew Waterman	RISC-V: Fix -fsignaling-nans for glibc testsuite.	blob \| commitdiff \| raw \| diff to current
2018-09-26	Jim Wilson	RISC-V: Add missing negate patterns.	blob \| commitdiff \| raw \| diff to current
2018-08-29	Jim Wilson	Rewrite pic.md to improve medany and pic code size.	blob \| commitdiff \| raw \| diff to current
2018-07-03	Jim Wilson	RISC-V: Fix interrupt support for -g.	blob \| commitdiff \| raw \| diff to current
2018-06-30	Jim Wilson	RISC-V: Add patterns to convert AND mask to two shifts.	blob \| commitdiff \| raw \| diff to current
2018-06-06	Jim Wilson	RISC-V: Add interrupt attribute modes.	blob \| commitdiff \| raw \| diff to current
2018-06-04	Jim Wilson	RISC-V: Don't clobber retval when __builtin_eh_return...	blob \| commitdiff \| raw \| diff to current
2018-05-25	Jim Wilson	RISC-V: Add interrupt attribute support.	blob \| commitdiff \| raw \| diff to current
2018-05-16	Jim Wilson	RISC-V: Minor pattern name cleanup.	blob \| commitdiff \| raw \| diff to current
2018-04-02	Jim Wilson	RISC-V: Fix for combine bug with shift and AND operations.	blob \| commitdiff \| raw \| diff to current
2018-01-10	Kito Cheng	RISC-V: Add naked function support.	blob \| commitdiff \| raw \| diff to current
2018-01-03	Jakub Jelinek	Update copyright years.	blob \| commitdiff \| raw \| diff to current
2018-01-02	Andrew Waterman	RISC-V: Fix for icache flush issue on multicore processors.	blob \| commitdiff \| raw \| diff to current
2017-11-29	Jim Wilson	Riscv patterns to optimize away some redundant zero...	blob \| commitdiff \| raw \| diff to current
2017-11-07	Andrew Waterman	RISC-V: Implement movmemsi	blob \| commitdiff \| raw \| diff to current
2017-11-05	Michael Clark	RISC-V: Emit "i" suffix for instructions with immediate...	blob \| commitdiff \| raw \| diff to current
2017-10-25	Palmer Dabbelt	RISC-V: Add Sign/Zero extend patterns for PIC loads	blob \| commitdiff \| raw \| diff to current
2017-09-15	Richard Sandiford	Turn TRULY_NOOP_TRUNCATION into a hook	blob \| commitdiff \| raw \| diff to current
2017-05-05	Kito Cheng	RISC-V: Unify indention in riscv.md	blob \| commitdiff \| raw \| diff to current
2017-02-06	Palmer Dabbelt	RISC-V Port: gcc	blob \| commitdiff \| raw \| diff to current

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