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[thirdparty/binutils-gdb.git] / include / opcode / riscv-opc.h

7 days ago	Hau Hsu	RISC-V: Add SiFive cease extension v1.0	commit \| commitdiff
7 days ago	Gianluca Guida	RISC-V: Support Zacas extension.	commit \| commitdiff
13 days ago	Jiawei	RISC-V: Support S[sm]csrind extension csrs.	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zvfbfwma extension	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zvfbfmin extension	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zfbfmin extension	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVmem extension in CV32E40P	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVbi extension in CV32E40P	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVelw extension in CV32E40P	commit \| commitdiff
2024-04-09	Jiawei	RISC-V: Support Zcmp push/pop instructions.	commit \| commitdiff
2024-03-28	Nelson Chu	RISC-V: Removed privileged spec 1.9.1 support in assembler.	commit \| commitdiff
2024-03-08	Jiawei	RISC-V: Support Zabha extension.	commit \| commitdiff
2024-01-04	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2023-12-14	Jin Ma	RISC-V: Fix the wrong encoding and operand of the XThea...	commit \| commitdiff
2023-12-01	Nelson Chu	RISC-V: Add SiFive custom vector coprocessor interface...	commit \| commitdiff
2023-12-01	Christoph Müllner	RISC-V: Zv*: Add support for Zvkb ISA extension	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add vector permutation instructions for T-Head...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add vector mask instructions for T-Head VECTOR...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add floating-point arithmetic instructions...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add fixed-point arithmetic instructions for...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add integer arithmetic instructions for T-Head...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add load/store segment instructions for T-Head...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add load/store instructions for T-Head VECTOR...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add CSRs for T-Head VECTOR vendor extension	commit \| commitdiff
2023-11-07	Mary Bennett	RISC-V: Add support for XCValu extension in CV32E40P	commit \| commitdiff
2023-11-07	Mary Bennett	RISC-V: Add support for XCVmac extension in CV32E40P	commit \| commitdiff
2023-10-19	Tsukasa OI	RISC-V: Remove semicolons from DECLARE_INSN	commit \| commitdiff
2023-10-17	Tsukasa OI	RISC-V: Fix typo	commit \| commitdiff
2023-09-05	Tsukasa OI	RISC-V: Add 'Smcntrpmf' extension and its CSRs	commit \| commitdiff
2023-08-15	Tsukasa OI	RISC-V: Add support for the 'Zihintntl' extension	commit \| commitdiff
2023-08-02	Sam James	Revert "2.41 Release sources"	commit \| commitdiff
2023-08-02	Nick Clifton	2.41 Release sources binutils-2_41-release	commit \| commitdiff
2023-07-18	Jiawei	RISC-V: Supports Zcb extension.	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksh ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksed ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvknh[a,b] ISA extensions	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkned ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkg ISA extension	commit \| commitdiff
2023-07-01	Nathan Huckleberry	RISC-V: Add support for the Zvbc extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvbb ISA extension	commit \| commitdiff
2023-06-30	Christoph Müllner	RISC-V: Add support for the Zfa extension	commit \| commitdiff
2023-06-27	Philipp Tomsich	RISC-V: Support Zicond extension	commit \| commitdiff
2023-04-26	Philipp Tomsich	RISC-V: Support XVentanaCondOps extension	commit \| commitdiff
2023-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2022-12-27	Christoph Müllner	RISC-V: Fix T-Head Fmv vendor extension encoding	commit \| commitdiff
2022-11-25	Christoph Müllner	riscv: Add AIA extension support (Smaia, Ssaia)	commit \| commitdiff
2022-11-19	Tsukasa OI	RISC-V: Add 'Ssstateen' extension and its CSRs	commit \| commitdiff
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Int vendor extension	commit \| commitdiff
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Fmv vendor extension	commit \| commitdiff
2022-09-23	Christoph Müllner	RISC-V: Add Zawrs ISA extension support	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemPair vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemIdx vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head FMemIdx vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MAC vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CondMov vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head Bitmanip vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head SYNC vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CMO vendor extension	commit \| commitdiff
2022-06-28	Tsukasa OI	RISC-V: Add 'Sstc' extension and its CSRs	commit \| commitdiff
2022-06-28	Tsukasa OI	RISC-V: Add 'Sscofpmf' extension with its CSRs	commit \| commitdiff
2022-06-28	Tsukasa OI	RISC-V: Add 'Smstateen' extension and its CSRs	commit \| commitdiff
2022-06-22	Nelson Chu	RISC-V: Use single h extension to control hypervisor...	commit \| commitdiff
2022-05-20	Tsukasa OI	RISC-V: Remove RV128-only fmv instructions	commit \| commitdiff
2022-05-17	Nelson Chu	RISC-V: Added half-precision floating-point v1.0 instru...	commit \| commitdiff
2022-04-22	Christoph Muellner	RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}	commit \| commitdiff
2022-03-18	Tsukasa OI	RISC-V: Cache management instructions	commit \| commitdiff
2022-03-18	Tsukasa OI	RISC-V: Prefetch hint instructions and operand set	commit \| commitdiff
2022-02-23	Nelson Chu	RISC-V: Updated CSRs to privileged spec v1.12 and debug...	commit \| commitdiff
2022-02-23	Tsukasa OI	RISC-V: Add Privileged Architecture 1.12 CSRs	commit \| commitdiff
2022-01-02	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2021-12-24	Vineet Gupta	RISC-V: Hypervisor ext: support Privileged Spec 1.12	commit \| commitdiff
2021-12-24	Vineet Gupta	RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1...	commit \| commitdiff
2021-12-16	Nelson Chu	RISC-V: Support svinval extension with frozen version...	commit \| commitdiff
2021-11-17	Nelson Chu	RISC-V: Support rvv extension with released version...	commit \| commitdiff
2021-11-16	jiawei	RISC-V: Scalar crypto instructions and operand set.	commit \| commitdiff
2021-10-07	Philipp Tomsich	RISC-V: Add support for Zbs instructions	commit \| commitdiff
2021-03-16	Kuan-Lin Chen	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	commit \| commitdiff
2021-02-05	Nelson Chu	RISC-V: PR27348, Remove obsolete Xcustom support.	commit \| commitdiff
2021-02-04	Nelson Chu	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct...	commit \| commitdiff
2021-01-15	Nelson Chu	RISC-V: Comments tidy and improvement.	commit \| commitdiff
2021-01-07	Philipp Tomsich	RISC-V: Add pause hint instruction.	commit \| commitdiff
2021-01-07	Claire Xenia Wolf	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr...	commit \| commitdiff
2021-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2020-06-30	Nelson Chu	RISC-V: Support debug and float CSR as the unprivileged...	commit \| commitdiff
2020-06-30	Nelson Chu	RISC-V: Cleanup the include/opcode/riscv-opc.h.	commit \| commitdiff
2020-06-12	Nelson Chu	RISC-V: Drop the privileged spec v1.9 support.	commit \| commitdiff
2020-05-20	Nelson Chu	[PATCH v2 0/9] RISC-V: Support version controling for...	commit \| commitdiff
2020-03-30	Nelson Chu	RISC-V: Update CSR to privileged spec 1.11.	commit \| commitdiff
2020-02-21	Nelson Chu	RISC-V: Support the ISA-dependent CSR checking.	commit \| commitdiff
2018-10-02	Palmer Dabbelt	RISC-V: Add fence.tso instruction	commit \| commitdiff
2018-05-08	Jim Wilson	RISC-V: Add missing hint instructions from RV128I.	commit \| commitdiff
2018-01-04	Jim Wilson	RISC-V: Add 2 missing privileged registers.	commit \| commitdiff
2017-12-28	Jim Wilson	RISC-V: Add missing privileged spec registers.	commit \| commitdiff
2017-11-07	Palmer Dabbelt	RISC-V: Add satp as an alias for sptbr	commit \| commitdiff
2017-03-31	Andrew Waterman	RISC-V: Add physical memory protection CSRs	commit \| commitdiff
2017-02-24	Andrew Waterman	Add new counter-enable CSRs	commit \| commitdiff
2017-02-15	Andrew Waterman	Add SFENCE.VMA instruction	commit \| commitdiff
2017-01-03	Kito Cheng	Add support for the Q extension to the RISCV ISA.	commit \| commitdiff
2016-11-01	Nick Clifton	Add support for RISC-V architecture.	commit \| commitdiff

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