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[thirdparty/binutils-gdb.git] / include / opcode / riscv.h

7 days ago	Hau Hsu	RISC-V: Add SiFive cease extension v1.0	commit \| commitdiff
7 days ago	Gianluca Guida	RISC-V: Support Zacas extension.	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zvfbfwma extension	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zvfbfmin extension	commit \| commitdiff
2024-06-06	Xiao Zeng	RISC-V: Add support for Zfbfmin extension	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVmem extension in CV32E40P	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVbi extension in CV32E40P	commit \| commitdiff
2024-06-05	Mary Bennett	RISC-V: Add support for XCVelw extension in CV32E40P	commit \| commitdiff
2024-05-08	Nelson Chu	RISC-V: Support B, Zaamo and Zalrsc extensions.	commit \| commitdiff
2024-04-09	Jiawei	RISC-V: Support Zcmp push/pop instructions.	commit \| commitdiff
2024-03-08	Jiawei	RISC-V: Support Zabha extension.	commit \| commitdiff
2024-01-05	Jin Ma	RISC-V: T-HEAD: Fix wrong instruction encoding for...	commit \| commitdiff
2024-01-04	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2023-12-01	Nelson Chu	RISC-V: Add SiFive custom vector coprocessor interface...	commit \| commitdiff
2023-12-01	Christoph Müllner	RISC-V: Zv*: Add support for Zvkb ISA extension	commit \| commitdiff
2023-11-24	Jan Beulich	RISC-V: reduce redundancy in sign/zero extension macro...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR...	commit \| commitdiff
2023-11-23	Jin Ma	RISC-V: Add T-Head VECTOR vendor extension.	commit \| commitdiff
2023-11-07	Mary Bennett	RISC-V: Add support for XCValu extension in CV32E40P	commit \| commitdiff
2023-11-07	Mary Bennett	RISC-V: Add support for XCVmac extension in CV32E40P	commit \| commitdiff
2023-11-03	Jan Beulich	RISC-V: reduce redundancy in load/store macro insn...	commit \| commitdiff
2023-09-05	Jan Beulich	RISC-V: fold duplicate code in vector_macro()	commit \| commitdiff
2023-08-15	Tsukasa OI	RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'	commit \| commitdiff
2023-08-15	Tsukasa OI	RISC-V: Add support for the 'Zihintntl' extension	commit \| commitdiff
2023-08-15	Jan Beulich	RISC-V: remove indirection from register tables	commit \| commitdiff
2023-08-02	Sam James	Revert "2.41 Release sources"	commit \| commitdiff
2023-08-02	Nick Clifton	2.41 Release sources binutils-2_41-release	commit \| commitdiff
2023-07-18	Jiawei	RISC-V: Supports Zcb extension.	commit \| commitdiff
2023-07-03	Christoph Müllner	RISC-V: Zvkh[a,b]: Remove individual instruction class	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksh ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvksed ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvknh[a,b] ISA extensions	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkned ISA extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvkg ISA extension	commit \| commitdiff
2023-07-01	Nathan Huckleberry	RISC-V: Add support for the Zvbc extension	commit \| commitdiff
2023-07-01	Christoph Müllner	RISC-V: Add support for the Zvbb ISA extension	commit \| commitdiff
2023-06-30	Christoph Müllner	RISC-V: Add support for the Zfa extension	commit \| commitdiff
2023-06-27	Philipp Tomsich	RISC-V: Support Zicond extension	commit \| commitdiff
2023-06-01	Jim Wilson	RISC-V: PR30449, Add lga assembler macro support.	commit \| commitdiff
2023-04-26	Philipp Tomsich	RISC-V: Support XVentanaCondOps extension	commit \| commitdiff
2023-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Int vendor extension	commit \| commitdiff
2022-11-17	Christoph Müllner	RISC-V: Add T-Head Fmv vendor extension	commit \| commitdiff
2022-10-14	Tsukasa OI	RISC-V: Move certain arrays to riscv-opc.c	commit \| commitdiff
2022-10-04	Tsukasa OI	RISC-V: Fix buffer overflow on print_insn_riscv	commit \| commitdiff
2022-10-04	Nelson Chu	RISC-V: Renamed INSN_CLASS for floating point in intege...	commit \| commitdiff
2022-10-04	Jan Beulich	RISC-V/gas: allow generating up to 176-bit instructions...	commit \| commitdiff
2022-09-23	Christoph Müllner	RISC-V: Add Zawrs ISA extension support	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemPair vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MemIdx vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head FMemIdx vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head MAC vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CondMov vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head Bitmanip vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add support for arbitrary immediate encoding...	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head SYNC vendor extension	commit \| commitdiff
2022-09-22	Christoph Müllner	RISC-V: Add T-Head CMO vendor extension	commit \| commitdiff
2022-08-30	Tsukasa OI	RISC-V: Add 'Zmmul' extension in assembler.	commit \| commitdiff
2022-07-07	Tsukasa OI	RISC-V: Added Zfhmin and Zhinxmin.	commit \| commitdiff
2022-06-22	Nelson Chu	RISC-V: Use single h extension to control hypervisor...	commit \| commitdiff
2022-05-30	jiawei	RISC-V: Add zhinx extension supports.	commit \| commitdiff
2022-05-17	Nelson Chu	RISC-V: Added half-precision floating-point v1.0 instru...	commit \| commitdiff
2022-03-18	Tsukasa OI	RISC-V: Cache management instructions	commit \| commitdiff
2022-03-18	Tsukasa OI	RISC-V: Prefetch hint instructions and operand set	commit \| commitdiff
2022-01-02	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2021-12-16	Nelson Chu	RISC-V: Support svinval extension with frozen version...	commit \| commitdiff
2021-11-30	Nelson Chu	RISC-V: The vtype immediate with more than the defined...	commit \| commitdiff
2021-11-18	jiawei	RISC-V: Add instructions and operand set for z[fdq]inx	commit \| commitdiff
2021-11-17	Nelson Chu	RISC-V: Support rvv extension with released version...	commit \| commitdiff
2021-11-16	jiawei	RISC-V: Scalar crypto instructions and operand set.	commit \| commitdiff
2021-10-07	Philipp Tomsich	RISC-V: Add support for Zbs instructions	commit \| commitdiff
2021-08-30	Nelson Chu	RISC-V: PR27916, Support mapping symbols.	commit \| commitdiff
2021-03-16	Kuan-Lin Chen	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	commit \| commitdiff
2021-02-19	Nelson Chu	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL...	commit \| commitdiff
2021-02-18	Nelson Chu	RISC-V: Add bfd/cpu-riscv.h to support all spec version...	commit \| commitdiff
2021-02-05	Nelson Chu	RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.	commit \| commitdiff
2021-02-04	Nelson Chu	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct...	commit \| commitdiff
2021-01-15	Nelson Chu	RISC-V: Indent and GNU coding standards tidy, also...	commit \| commitdiff
2021-01-15	Nelson Chu	RISC-V: Comments tidy and improvement.	commit \| commitdiff
2021-01-07	Philipp Tomsich	RISC-V: Add pause hint instruction.	commit \| commitdiff
2021-01-07	Claire Xenia Wolf	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr...	commit \| commitdiff
2021-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2020-12-10	Nelson Chu	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	commit \| commitdiff
2020-12-10	Nelson Chu	RISC-V: Control fence.i and csr instructions by zifence...	commit \| commitdiff
2020-12-01	Nelson Chu	RISC-V: Support to add implicit extensions for G.	commit \| commitdiff
2020-12-01	Nelson Chu	RISC-V: Improve the version parsing for arch string.	commit \| commitdiff
2020-08-31	Alan Modra	PR26493 UBSAN: elfnn-riscv.c left shift of negative...	commit \| commitdiff
2020-06-30	Nelson Chu	RISC-V: Support debug and float CSR as the unprivileged...	commit \| commitdiff
2020-06-22	Nelson Chu	RISC-V: Report warning when linking the objects with...	commit \| commitdiff
2020-06-12	Nelson Chu	RISC-V: Drop the privileged spec v1.9 support.	commit \| commitdiff
2020-06-03	Nelson Chu	RISC-V: Fix the error when building RISC-V linux native...	commit \| commitdiff
2020-05-20	Nelson Chu	[PATCH v2 0/9] RISC-V: Support version controling for...	commit \| commitdiff
2020-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2019-09-18	Jim Wilson	RISC-V: Gate opcode tables by enum rather than string.	commit \| commitdiff
2019-01-01	Alan Modra	Update year range in copyright notice of binutils files	commit \| commitdiff
2018-12-06	Andrew Burgess	opcodes/riscv: Hide '.L0 ' fake symbols	commit \| commitdiff
2018-12-03	Jim Wilson	RISC-V: Accept version, supervisor ext and more than...	commit \| commitdiff
2018-11-27	Jim Wilson	RISC-V: Add .insn CA support.	commit \| commitdiff
2018-08-30	Jim Wilson	RISC-V: Allow instruction require more than one extension	commit \| commitdiff
2018-07-30	Jim Wilson	RISC-V: Set insn info fields correctly when disassembling.	commit \| commitdiff
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