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Use signal information to determine SIGTRAP type for FreeBSD.
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2018-03-03  Alan Modraopcodes error messages
2018-03-01  H.J. Lux86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128
2018-02-28  Alan ModraAdd missing translations to ALL_LINGUAS
2018-02-27  Thomas Preud'homme[ARM] Remove ARM_FEATURE_COPY macro
2018-02-27  H.J. Lux86: Add -O[2|s] assembler command-line options
2018-02-26  Alan Modracrx string overflow warning
2018-02-22  Jim WilsonRISC-V: Make disassebler work for --enable-targets...
2018-02-22  H.J. Lux86: Add {rex} pseudo prefix
2018-02-20  Maciej W. RozyckiMIPS16/opcodes: Free up `M' operand code
2018-02-19  Thomas Preud'homme[ARM] Fix bxns mask
2018-02-13  Nick CliftonFix compile time warning messages from gcc version...
2018-02-13  Maciej W. RozyckiWebAssembly: Correct an `index' global shadowing error...
2018-02-12  Henry WongMIPS: Fix encoding for MIPSr6 sigrie instruction.
2018-02-05  Nick CliftonUpdated Brazillian portuguese and Russian translation
2018-01-23  Igor TsimbalistEnable Intel PCONFIG instruction.
2018-01-23  Igor TsimbalistEnable Intel WBNOINVD instruction.
2018-01-17  Jim WilsonRISC-V: Fix bug in prior addi/c.nop patch.
2018-01-17  Igor TsimbalistReplace CET bit with IBT and SHSTK bits.
2018-01-16  Nick CliftonUpdate translations for various binutils components.
2018-01-15  Jim WilsonRISC-V: Add support for addi that compresses to c.nop.
2018-01-15  Nick CliftonUpdate Ukranian translations for bfd, binutils, gas...
2018-01-13  Nick CliftonUpdate pot files
2018-01-13  Nick CliftonBump version number to 2.30.51
2018-01-13  Nick CliftonAdd note about 2.30 branch creation to changelogs
2018-01-11  Igor TsimbalistRemove VL variants for 4FMAPS and 4VNNIW insns.
2018-01-10  Jan Beulichx86: fix Disp8 handling for scalar AVX512_4FMAPS insns
2018-01-10  Jan Beulichx86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants
2018-01-10  Jim WilsonRISC-V: Disassemble x0 based addresses as 0.
2018-01-09  James Greenhalgh[Arm] Add CSDB instruction
2018-01-09  James GreenhalghAdd support for the AArch64's CSDB instruction.
2018-01-08  H.J. Lux86: Properly encode vmovd with 64-bit memeory
2018-01-06  Jim WilsonRISC-V: Print symbol address for jalr w/ zero offset.
2018-01-03  Alan ModraUpdate year range in copyright notice of binutils files
2018-01-03  Alan ModraChangeLog rotation
2018-01-02  Jan Beulichx86: partial revert of 10c17abdd0
2017-12-20  Jim WilsonRISC-V: Add compressed instruction hints, and a few...
2017-12-19  Tamar ChristinaCorrect disassembly of dot product instructions.
2017-12-19  Tamar ChristinaAdd support for V_4B so we can properly reject it.
2017-12-18  Jan Beulichx86: fold certain AVX and AVX2 templates
2017-12-18  Jan Beulichx86: fold RegXMM/RegYMM/RegZMM into RegSIMD
2017-12-18  Jan Beulichx86: drop FloatReg and FloatAcc
2017-12-18  Jan Beulichx86: replace Reg8, Reg16, Reg32, and Reg64
2017-12-15  Dimitar DimitrovFix disassembly for PowerPC
2017-12-15  Jan Beulichx86: drop stray CheckRegSize uses
2017-12-13  Jim WilsonAdd missing RISC-V fsrmi and fsflagsi instructions.
2017-12-13  Dimitar DimitrovThis patch enables disassembler_needs_relocs for PRU...
2017-12-11  Renlin Li[Binutils][Objdump]Check symbol section information...
2017-12-03  Alan ModraFix "FAIL: VLE relocations 3"
2017-12-01  Peter BergnerUse consistent types for holding instructions, instruct...
2017-11-30  Jan Beulichx86: derive DispN from BaseIndex
2017-11-30  Jan Beulichx86: drop Vec_Disp8
2017-11-29  Stefan StroeSupport --localedir, --datarootdir and --datadir
2017-11-27  Nick CliftonUpdate the simplified Chinese translation of the messag...
2017-11-24  Jan Beulichx86: don't omit disambiguating suffixes from "fi*"
2017-11-23  Igor TsimbalistAdd Disp8MemShift for AVX512 VAES instructions.
2017-11-23  Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23  Jan Beulichx86: correct UDn
2017-11-22  Igor TsimbalistRemove Vec_Disp8 field for vgf2p8mulb for AVX flavor.
2017-11-22  Igor TsimbalistUpdate ChangeLog
2017-11-22  Igor TsimbalistRemove Vec_Disp8 from vpcompressb and vpexpandb.
2017-11-22  claziss[ARC] Fix handling of ARCv2 H-register class.
2017-11-21  claziss[ARC] Improve printing of pc-relative instructions.
2017-11-16  Tamar ChristinaAdd new AArch64 FP16 FM{A|S} instructions.
2017-11-16  Tamar ChristinaCorrect AArch64 crypto dependencies.
2017-11-16  Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-16  Jan Beulichx86: ignore high register select bit(s) in 32- and...
2017-11-15  Jan Beulichx86: use correct register names
2017-11-15  Jan Beulichx86: drop VEXI4_Fixup()
2017-11-15  Jan Beulichx86-64: don't allow use of %axl as accumulator
2017-11-14  Jan Beulichx86: add disassembler support for XOP VPCOM* pseudo-ops
2017-11-14  Jan Beulichx86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
2017-11-14  Jan Beulichx86: string insns don't allow displacements
2017-11-13  Jan Beulichx86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should...
2017-11-09  Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-09  Tamar ChristinaAdd the operand encoding types for the new Armv8.2...
2017-11-09  Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09  Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
2017-11-08  Nick CliftonSplit the AArch64 Crypto instructions for AES and SHA1...
2017-11-08  Jiong WangAdds command line support for Armv8.4-A, via the new...
2017-11-07  Andrew Burgessopcodes/arc: Fix incorrect insn_class for some nps...
2017-11-07  Alan Modrangettext support
2017-11-03  claziss[ARC] Force the disassam to use the hexadecimal number...
2017-11-03  claziss[ARC] Sync opcode data base.
2017-10-25  Alan ModraPR22348, conflicting global vars in crx and cr16
2017-10-24  Andrew WatermanRISC-V: Fix disassembly of c.addi4spn, c.addi16sp,...
2017-10-23  Igor TsimbalistAdd missing ChangeLog entries
2017-10-23  Igor TsimbalistFix the master due to bad regenerated files
2017-10-23  Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23  Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23  Igor TsimbalistEnable Intel VAES instructions.
2017-10-23  Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-10-18  Eric Botcazou[Visium] Disassemble the operands of the stop instruction.
2017-10-13  James BowmanFT32: support for FT32B processor - part 1
2017-10-09  Andreas KrebbelS/390: Sync with latest POP - 3 new instructions
2017-10-09  Andreas KrebbelS/390: Sync with IBM z14 POP - SI_RD format
2017-10-01  Alexander FedotovAdd new mnemonics for VLE multiple load instructions
2017-09-27  Nick CliftonAdd support for the new names of the RISC-V fmv.x.s...
2017-09-26  Nick CliftonAllow the macw and macl instructions to be used on...
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