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6 weeks ago[AArch64]: Do not allow SIMD clones with simdlen 1 [PR113552]
Tamar Christina [Mon, 15 Apr 2024 11:32:24 +0000 (12:32 +0100)] 
[AArch64]: Do not allow SIMD clones with simdlen 1 [PR113552]

This is a backport of g:306713c953d509720dc394c43c0890548bb0ae07.

The AArch64 vector PCS does not allow simd calls with simdlen 1,
however due to a bug we currently do allow it for num == 0.

This causes us to emit a symbol that doesn't exist and we fail to link.

gcc/ChangeLog:

PR tree-optimization/113552
* config/aarch64/aarch64.c
(aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.

gcc/testsuite/ChangeLog:

PR tree-optimization/113552
* gcc.target/aarch64/pr113552.c: New test.
* gcc.target/aarch64/simd_pcs_attribute-3.c: Remove bogus check.

6 weeks agomiddle-end/114599 - fix bitmap allocation for check_ifunc_callee_symtab_nodes
Richard Biener [Fri, 5 Apr 2024 08:16:41 +0000 (10:16 +0200)] 
middle-end/114599 - fix bitmap allocation for check_ifunc_callee_symtab_nodes

There's no default bitmap obstack during global CTORs, so allocate the
bitmap locally.

PR middle-end/114599
PR gcov-profile/114115
* symtab.c (ifunc_ref_map): Do not use auto_bitmap.
(is_caller_ifunc_resolver): Optimize bitmap_bit_p/bitmap_set_bit
pair.
(symtab_node::check_ifunc_callee_symtab_nodes): Properly
allocate ifunc_ref_map here.

(cherry picked from commit 9ab8fdfeef5b1a47b358e08a98177b2fad65fed9)

6 weeks agotree-profile: Disable indirect call profiling for IFUNC resolvers
H.J. Lu [Mon, 26 Feb 2024 16:38:58 +0000 (08:38 -0800)] 
tree-profile: Disable indirect call profiling for IFUNC resolvers

We can't profile indirect calls to IFUNC resolvers nor their callees as
it requires TLS which hasn't been set up yet when the dynamic linker is
resolving IFUNC symbols.

Add an IFUNC resolver caller marker to cgraph_node and set it if the
function is called by an IFUNC resolver.  Disable indirect call profiling
for IFUNC resolvers and their callees.

Tested with profiledbootstrap on Fedora 39/x86-64.

gcc/ChangeLog:

PR tree-optimization/114115
* cgraph.h (symtab_node): Add check_ifunc_callee_symtab_nodes.
(cgraph_node): Add called_by_ifunc_resolver.
* cgraphunit.c (symbol_table::compile): Call
symtab_node::check_ifunc_callee_symtab_nodes.
* symtab.c (check_ifunc_resolver): New.
(ifunc_ref_map): Likewise.
(is_caller_ifunc_resolver): Likewise.
(symtab_node::check_ifunc_callee_symtab_nodes): Likewise.
* tree-profile.c (gimple_gen_ic_func_profiler): Disable indirect
call profiling for IFUNC resolvers and their callees.

gcc/testsuite/ChangeLog:

PR tree-optimization/114115
* gcc.dg/pr114115.c: New test.

(cherry picked from commit cab32bacaea268ec062b1fb4fc662d90c9d1cfce)

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7 weeks agoRISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
Kito Cheng [Wed, 28 Feb 2024 08:01:52 +0000 (16:01 +0800)] 
RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

atomic_compare_and_swapsi will use lr.w to do obtain the original value,
which sign extends to DI.  RV64 only has DI comparisons, so we also need
to sign extend the expected value to DI as otherwise the comparison will
fail when the expected value has the 32nd bit set.

gcc/ChangeLog:

PR target/114130
* config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
extend the expected value if needed.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr114130.c: New.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit fd07a29e39f5347d6cef3e7042a32306f97a1719)

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8 weeks agoFortran: fix DATA and derived types with pointer components [PR114474]
Harald Anlauf [Wed, 27 Mar 2024 20:18:04 +0000 (21:18 +0100)] 
Fortran: fix DATA and derived types with pointer components [PR114474]

When matching actual arguments in match_actual_arg, these are initially
treated as a possible dummy procedure, assuming that the correct type is
determined later.  This resolution could fail when the procedure is a
derived type constructor with a pointer component and appears in a DATA
statement, where the pointer shall be associated with an initial data
target.  Check for those cases where the type obviously has not been
resolved yet, and which were missed because there was no component
reference.

gcc/fortran/ChangeLog:

PR fortran/114474
* primary.c (gfc_variable_attr): Catch variables used in structure
constructors within DATA statements that are still tagged with a
temporary type BT_PROCEDURE from match_actual_arg and which have the
target attribute, and fix their typespec.

gcc/testsuite/ChangeLog:

PR fortran/114474
* gfortran.dg/data_pointer_3.f90: New test.

(cherry picked from commit bbb7c513dddc5c9b2d5e9b78bc1c2f85a0cfe07e)

8 weeks agofortran: Fix setting of array lower bound for named arrays
Chung-Lin Tang [Fri, 3 Dec 2021 09:27:17 +0000 (17:27 +0800)] 
fortran: Fix setting of array lower bound for named arrays

This patch fixes a case of setting array low-bounds, found for particular uses
of SOURCE=/MOLD=. This adjusts the relevant part in gfc_trans_allocate() to
set e3_has_nodescriptor only for non-named arrays.

2021-12-03  Tobias Burnus  <tobias@codesourcery.com>

gcc/fortran/ChangeLog:

* trans-stmt.c (gfc_trans_allocate): Set e3_has_nodescriptor to true
only for non-named arrays.

gcc/testsuite/ChangeLog:

* gfortran.dg/allocate_with_source_26.f90: Adjust testcase.
* gfortran.dg/allocate_with_mold_4.f90: New testcase.

(cherry picked from commit 6262e3a22b3d86afc116480bc59a7bb30b0cfd40)

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2 months agoFix SSA corruption due to widening_mul opt on conflict across an abnormal edge [PR111407]
Qing Zhao [Mon, 25 Mar 2024 14:17:56 +0000 (14:17 +0000)] 
Fix SSA corruption due to widening_mul opt on conflict across an abnormal edge [PR111407]

This is a bug in tree-ssa-math-opts.c, when applying the widening mul
optimization, the compiler needs to check whether the operand is in a
ABNORMAL PHI, if YES, we should avoid the transformation.

PR tree-optimization/111407

gcc/ChangeLog:

* tree-ssa-math-opts.c (convert_mult_to_widen): Avoid the transform
when one of the operands is subject to abnormal coalescing.

gcc/testsuite/ChangeLog:

* gcc.dg/pr111407.c: New test.

(cherry picked from commit 4aca1cfd6235090e48a53dab734437740671bbf3)

2 months agofortran: Ignore use statements on error [PR107426]
Mikael Morin [Thu, 21 Mar 2024 16:27:54 +0000 (17:27 +0100)] 
fortran: Ignore use statements on error [PR107426]

This fixes an access to freed memory on the testcase from the PR.
The problem comes from an invalid subroutine statement in an interface,
which is ignored and causes the following statements forming the procedure
body to be rejected.  One of them use-associates the intrinsic ISO_C_BINDING
module, which imports new symbols in a namespace that is freed at the time
the statement is rejected.  However, this creates dangling pointers as
ISO_C_BINDING is special and its import creates a reference to the imported
C_PTR symbol in the return type of the global intrinsic symbol for C_LOC
(see the function create_intrinsic_function).

This change saves and restores the list of use statements, so that rejected
use statements are removed before they have a chance to be applied to the
current namespace and create dangling pointers.

PR fortran/107426

gcc/fortran/ChangeLog:

* gfortran.h (gfc_save_module_list, gfc_restore_old_module_list):
New declarations.
* module.c (old_module_list_tail): New global variable.
(gfc_save_module_list, gfc_restore_old_module_list): New functions.
(gfc_use_modules): Set module_list and old_module_list_tail.
* parse.c (next_statement): Save module_list before doing any work.
(reject_statement): Restore module_list to its saved value.

gcc/testsuite/ChangeLog:

* gfortran.dg/pr89943_3.f90: Update error pattern.
* gfortran.dg/pr89943_4.f90: Likewise.
* gfortran.dg/use_31.f90: New test.

(cherry picked from commit a44d7e8a52007c2d45217709ca02947c6600de87)

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2 months agoObjective-C, NeXT: Fix messenging non-aggregate return-in-memory.
Iain Sandoe [Mon, 16 Aug 2021 20:22:13 +0000 (21:22 +0100)] 
Objective-C, NeXT: Fix messenging non-aggregate return-in-memory.

When a method returns a type that the platform ABI says should be
returned in memory, and that is done by a hidden 'sret' parameter,
the message send calls must be adjusted to inform the runtime that
the sret parameter is present.  As reported in the PR, this is not
working for non-aggregate types that use this mechanism.  The fix
here is to adjust the logic such that all return values that flag
'in memory' are considered to use the mechanism *unless* they
provide a struct_value_rtx *and* the return object is an aggregate.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
PR objc/101718 - Objective-C frontend emits wrong code to call methods returning scalar types returned in memory

PR objc/101718

gcc/objc/ChangeLog:

* objc-next-runtime-abi-02.c (build_v2_build_objc_method_call):
Revise for cases where scalar objects use an sret parameter.
(next_runtime_abi_02_build_objc_method_call): Likwise.

(cherry picked from commit 1cef3039b880a21fbdf4153e6fc42026619fd4ad)

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2 months agoFortran: fix NULL pointer dereference on overlapping initialization [PR50410]
Harald Anlauf [Thu, 28 Mar 2024 21:34:40 +0000 (22:34 +0100)] 
Fortran: fix NULL pointer dereference on overlapping initialization [PR50410]

gcc/fortran/ChangeLog:

PR fortran/50410
* trans-expr.c (gfc_conv_structure): Check for NULL pointer.

gcc/testsuite/ChangeLog:

PR fortran/50410
* gfortran.dg/data_initialized_4.f90: New test.

(cherry picked from commit 6fb253a25dff13253d63553f02e0fe72c5e3ab4e)

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2 months agoasan: Handle poly-int sizes in ASAN_MARK [PR97696]
Richard Sandiford [Wed, 27 Mar 2024 19:26:57 +0000 (19:26 +0000)] 
asan: Handle poly-int sizes in ASAN_MARK [PR97696]

This patch makes the expansion of IFN_ASAN_MARK let through
poly-int-sized objects.  The expansion itself was already generic
enough, but the tests for the fast path were too strict.

gcc/
PR sanitizer/97696
* asan.c (asan_expand_mark_ifn): Allow the length to be a poly_int.

gcc/testsuite/
PR sanitizer/97696
* gcc.target/aarch64/sve/pr97696.c: New test.

(cherry picked from commit fca6f6fddb22b8665e840f455a7d0318d4575227)

2 months agoaarch64: Fix vld1/st1_x4 intrinsic definitions
Richard Sandiford [Wed, 27 Mar 2024 19:26:56 +0000 (19:26 +0000)] 
aarch64: Fix vld1/st1_x4 intrinsic definitions

The vld1_x4 and vst1_x4 patterns use XI registers for both 64-bit and
128-bit vectors.  This has the nice property that each individual
vector is within a separate 16-byte subreg of the XI, which should
reduce the number of memory spills needed.  However, it means that the
64-bit vector forms must convert between the native 4x64-bit structure
layout and the padded 4x128-bit XI layout.

The vld4 and vst4 functions did this correctly.  But the vld1x4 and
vst1x4 functions used a union between the native and padded layouts,
even though the layouts are different sizes.

This patch makes vld1x4 and vst1x4 use the same approach as vld4
and vst4.  It also fixes some uses of variables in the user namespace.

gcc/
* config/aarch64/arm_neon.h (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4):
(vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_f16_x4, vld1_f32_x4):
(vld1_p8_x4, vld1_p16_x4, vld1_s64_x4, vld1_u64_x4, vld1_p64_x4):
(vld1_f64_x4): Avoid using a union of a 256-bit structure and 512-bit
XImode integer.  Instead use the same approach as the vld4 intrinsics.
(vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_u8_x4, vst1_u16_x4):
(vst1_u32_x4, vst1_f16_x4, vst1_f32_x4, vst1_p8_x4, vst1_p16_x4):
(vst1_s64_x4, vst1_u64_x4, vst1_p64_x4, vst1_f64_x4, vld1_bf16_x4):
(vst1_bf16_x4): Likewise for stores.
(vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_u8_x4, vst1q_u16_x4):
(vst1q_u32_x4, vst1q_f16_x4, vst1q_f32_x4, vst1q_p8_x4, vst1q_p16_x4):
(vst1q_s64_x4, vst1q_u64_x4, vst1q_p64_x4, vst1q_f64_x4)
(vst1q_bf16_x4): Rename val parameter to __val.

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2 months agoFortran: error recovery in frontend optimization [PR103715]
Harald Anlauf [Mon, 18 Mar 2024 18:36:59 +0000 (19:36 +0100)] 
Fortran: error recovery in frontend optimization [PR103715]

gcc/fortran/ChangeLog:

PR fortran/103715
* frontend-passes.c (check_externals_expr): Prevent invalid read
in case of mismatch of external subroutine with function.

gcc/testsuite/ChangeLog:

PR fortran/103715
* gfortran.dg/pr103715.f90: New test.

(cherry picked from commit 3be2b8f475f22c531d6cef1b041c0573b3ea5133)

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2 months agoDarwin, Objective-C: Support -fconstant-cfstrings [PR108743].
Iain Sandoe [Sun, 2 Jul 2023 13:18:04 +0000 (14:18 +0100)] 
Darwin, Objective-C: Support -fconstant-cfstrings [PR108743].

This support the -fconstant-cfstrings option as used by clang (and
expect by some build scripts) as an alias to the target-specific
-mconstant-cfstrings.

The documentation is also updated to reflect that the 'f' option is
only available on Darwin, and to add the 'm' option to the Darwin
section of the invocation text.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
PR target/108743

gcc/ChangeLog:

* config/darwin.opt: Add fconstant-cfstrings alias to
mconstant-cfstrings.
* doc/invoke.texi: Amend invocation descriptions to reflect
that the fconstant-cfstrings is a target-option alias and to
add the missing mconstant-cfstrings option description to the
Darwin section.

(cherry picked from commit cdd4b3c0f0f428678c24de74b1f626628450799c)

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2 months agoFix bogus error on allocator for array type with Dynamic_Predicate
Eric Botcazou [Thu, 7 Mar 2024 14:05:54 +0000 (15:05 +0100)] 
Fix bogus error on allocator for array type with Dynamic_Predicate

This is a regression present on all active branches: the compiler gives
a bogus error on an allocator for an unconstrained array type declared
with a Dynamic_Predicate because Apply_Predicate_Check is invoked directly
on a subtype reference, which it cannot handle.

This moves the check to the resulting access value (after dereference) like
in Expand_Allocator_Expression.

gcc/ada/
PR ada/113979
* exp_ch4.adb (Expand_N_Allocator): In the subtype indication case,
remove call to Apply_Predicate_Check.

gcc/testsuite/
* gnat.dg/predicate15.adb: New test.

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3 months agoSH: Fix 101737
Oleg Endo [Sun, 3 Mar 2024 05:58:58 +0000 (14:58 +0900)] 
SH: Fix 101737

gcc/ChangeLog:
PR target/101737
* config/sh/sh.c (sh_is_nott_insn): Handle case where the input
is not an insn, but e.g. a code label.

3 months agod: Fix gdc -O2 -mavx generates misaligned vmovdqa instruction [PR114171]
Iain Buclaw [Sun, 3 Mar 2024 01:26:37 +0000 (02:26 +0100)] 
d: Fix gdc -O2 -mavx generates misaligned vmovdqa instruction [PR114171]

PR d/114171

gcc/d/ChangeLog:

* d-codegen.cc (lower_struct_comparison): Keep alignment of original
type in reinterpret cast for comparison.

gcc/testsuite/ChangeLog:

* gdc.dg/torture/pr114171.d: New test.

(cherry picked from commit 623f52775e677bb3d6e9e7ef97196741dd904b1e)

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3 months agod: Fix callee destructor call invalidates the live object [PR113758]
Iain Buclaw [Sun, 4 Feb 2024 21:04:14 +0000 (22:04 +0100)] 
d: Fix callee destructor call invalidates the live object [PR113758]

When generating the argument, check the isCalleeDestroyingArgs hook, and
force a TARGET_EXPR to be created if true, so that a reference to the
live object isn't passed directly to the function that runs dtors.

When instead dealing with caller running destructors, two temporaries
were being generated, one explicit temporary generated by the D
front-end, and another implicitly by the code generator.  This has been
reduced to one by setting DECL_VALUE_EXPR on the explicit temporary to
bind it to the implicit slot created for the TARGET_EXPR, as that has
the shorter lifetime of the two.

PR d/113758

gcc/d/ChangeLog:

* d-codegen.cc (d_build_call): Force a TARGET_EXPR when callee
destorys its arguments.
* decl.cc (DeclVisitor::visit (VarDeclaration *)): Set
SET_DECL_VALUE_EXPR on the temporary variable to make it a placeholder
for the TARGET_EXPR_SLOT.

gcc/testsuite/ChangeLog:

* gdc.dg/torture/pr113758.d: New test.

(cherry picked from commit 3c57b1c12a8e34d50bdf6aaf44146760db6d1b33)

3 months agod: Fix internal compiler error: in make_import, at d/imports.cc:48 [PR113125]
Iain Buclaw [Mon, 12 Feb 2024 15:59:12 +0000 (16:59 +0100)] 
d: Fix internal compiler error: in make_import, at d/imports.cc:48 [PR113125]

The cause of the ICE was that TYPE_DECLs were only being generated for
structs with members, not opaque structs.

PR d/113125

gcc/d/ChangeLog:

* types.cc (TypeVisitor::visit (TypeStruct *)): Generate TYPE_DECL and
apply UDAs to opaque struct declarations.

gcc/testsuite/ChangeLog:

* gdc.dg/imports/pr113125.d: New test.
* gdc.dg/pr113125.d: New test.

(cherry picked from commit b0efb1c35724e3332ee5993976efb98200c1a154)

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3 months agox86: Properly implement AMX-TILE load/store intrinsics
H.J. Lu [Sun, 25 Feb 2024 18:21:04 +0000 (10:21 -0800)] 
x86: Properly implement AMX-TILE load/store intrinsics

ldtilecfg and sttilecfg take a 512-byte memory block.  With
_tile_loadconfig implemented as

extern __inline void
__attribute__((__gnu_inline__, __always_inline__, __artificial__))
_tile_loadconfig (const void *__config)
{
  __asm__ volatile ("ldtilecfg\t%X0" :: "m" (*((const void **)__config)));
}

GCC sees:

(parallel [
  (asm_operands/v ("ldtilecfg %X0") ("") 0
   [(mem/f/c:DI (plus:DI (reg/f:DI 77 virtual-stack-vars)
                         (const_int -64 [0xffffffffffffffc0])) [1 MEM[(const void * *)&tile_data]+0 S8 A128])]
   [(asm_input:DI ("m"))]
   (clobber (reg:CC 17 flags))])

and the memory operand size is 1 byte.  As the result, the rest of 511
bytes is ignored by GCC.  Implement ldtilecfg and sttilecfg intrinsics
with a pointer to XImode to honor the 512-byte memory block.

gcc/ChangeLog:

PR target/114098
* config/i386/amxtileintrin.h (_tile_loadconfig): Use
__builtin_ia32_ldtilecfg.
(_tile_storeconfig): Use __builtin_ia32_sttilecfg.
* config/i386/i386-builtin.def (BDESC): Add
__builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
* config/i386/i386-expand.c (ix86_expand_builtin): Handle
IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
* config/i386/i386.md (ldtilecfg): New pattern.
(sttilecfg): Likewise.

gcc/testsuite/ChangeLog:

PR target/114098
* gcc.target/i386/amxtile-4.c: New test.

(cherry picked from commit 4972f97a265c574d51e20373ddefd66576051e5c)

3 months agors6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]
Jeevitha [Thu, 31 Aug 2023 10:40:18 +0000 (05:40 -0500)] 
rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

There are no instructions that do traditional AltiVec addresses (i.e.
with the low four bits of the address masked off) for OOmode and XOmode
objects. The solution is to modify the constraints used in the movoo and
movxo pattern to disallow these types of addresses, which assists LRA in
resolving this issue. Furthermore, the mode size 16 check has been
removed in vsx_quad_dform_memory_operand to allow OOmode and XOmode, and
quad_address_p already handles less than size 16.

2023-08-31  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>

gcc/
PR target/110411
* config/rs6000/mma.md (define_insn_and_split movoo): Disallow
AltiVec address operands.
(define_insn_and_split movxo): Likewise.
* config/rs6000/predicates.md (vsx_quad_dform_memory_operand): Remove
redundant mode size check.

gcc/testsuite/
PR target/110411
* gcc.target/powerpc/pr110411-1.c: New testcase.
* gcc.target/powerpc/pr110411-2.c: New testcase.

(cherry picked from commit 9ea1248604d7b65009af32103814332f35bd33e2)

3 months agoDaily bump.
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3 months agoFinalization of object allocated by anonymous access designating local type
Eric Botcazou [Mon, 26 Feb 2024 12:13:34 +0000 (13:13 +0100)] 
Finalization of object allocated by anonymous access designating local type

The finalization of objects dynamically allocated through an anonymous
access type is deferred to the enclosing library unit in the current
implementation and a warning is given on each of them.

However this cannot be done if the designated type is local, because this
would generate dangling references to the local finalization routine, so
the finalization needs to be dropped in this case and the warning adjusted.

gcc/ada/
PR ada/113893
* exp_ch7.adb (Build_Anonymous_Master): Do not build the master
for a local designated type.
* exp_util.adb (Build_Allocate_Deallocate_Proc): Force Needs_Fin
to false if no finalization master is attached to an access type
and assert that it is anonymous in this case.
* sem_res.adb (Resolve_Allocator): Mention that the object might
not be finalized at all in the warning given when the type is an
anonymous access-to-controlled type.

gcc/testsuite/
* gnat.dg/access10.adb: New test.

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3 months agoarm: fix ICE with vectorized reciprocal division [PR108120]
Richard Earnshaw [Thu, 22 Feb 2024 16:47:20 +0000 (16:47 +0000)] 
arm: fix ICE with vectorized reciprocal division [PR108120]

The expand pattern for reciprocal division was enabled for all math
optimization modes, but the patterns it was generating were not
enabled unless -funsafe-math-optimizations were enabled, this leads to
an ICE when the pattern we generate cannot be recognized.

Fixed by only enabling vector division when doing unsafe math.

gcc:

PR target/108120
* config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
Gate with ARM_HAVE_NEON_<MODE>_ARITH.

gcc/testsuite:
PR target/108120
* gcc.target/arm/neon-recip-div-1.c: New file.

(cherry picked from commit 016c4eed368b80a97101f6156ed99e4c5474fbb7)

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3 months agoaarch64: Avoid out-of-range shrink-wrapped saves [PR111677]
Alex Coplan [Tue, 30 Jan 2024 09:39:59 +0000 (09:39 +0000)] 
aarch64: Avoid out-of-range shrink-wrapped saves [PR111677]

The PR shows us ICEing due to an unrecognizable TFmode save emitted by
aarch64_process_components.  The problem is that for T{I,F,D}mode we
conservatively require mems to be in range for x-register ldp/stp.  That
is because (at least for TImode) it can be allocated to both GPRs and
FPRs, and in the GPR case that is an x-reg ldp/stp, and the FPR case is
a q-register load/store.

As Richard pointed out in the PR, aarch64_get_separate_components
already checks that the offsets are suitable for a single load, so we
just need to choose a mode in aarch64_reg_save_mode that gives the full
q-register range.  In this patch, we choose V16QImode as an alternative
16-byte "bag-of-bits" mode that doesn't have the artificial range
restrictions imposed on T{I,F,D}mode.

Unlike for GCC 14 we need additional handling in the load/store pair
code as various cases are not expecting to see V16QImode (particularly
the writeback patterns, but also aarch64_gen_load_pair).

gcc/ChangeLog:

PR target/111677
* config/aarch64/aarch64.c (aarch64_reg_save_mode): Use
V16QImode for the full 16-byte FPR saves in the vector PCS case.
(aarch64_gen_storewb_pair): Handle V16QImode.
(aarch64_gen_loadwb_pair): Likewise.
(aarch64_gen_load_pair): Likewise.
* config/aarch64/aarch64.md (loadwb_pair<TX:mode>_<P:mode>):
Rename to ...
(loadwb_pair<TX_V16QI:mode>_<P:mode>): ... this, extending to
V16QImode.
(storewb_pair<TX:mode>_<P:mode>): Rename to ...
(storewb_pair<TX_V16QI:mode>_<P:mode>): ... this, extending to
V16QImode.
* config/aarch64/iterators.md (TX_V16QI): New.

gcc/testsuite/ChangeLog:

PR target/111677
* gcc.target/aarch64/torture/pr111677.c: New test.

(cherry picked from commit fddce05d67f34174be0f306e1015d3868bbe7c31)

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3 months agotestsuite: Require lra effective target for pr107385.c
Jakub Jelinek [Thu, 15 Feb 2024 19:04:01 +0000 (20:04 +0100)] 
testsuite: Require lra effective target for pr107385.c

Old reload doesn't support asm goto with output operands.
We have lra effective target (though, strangely it returns
0 just for 2 targets out of at least 16 targets with no LRA support),
so this patch uses it, similarly how it is done in other asm goto
tests with output operands.

2024-02-15  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/107385
* gcc.dg/pr107385.c: Require lra effective target.

(cherry picked from commit 0d5d1c75f5c68b6064640c3154ae5f4c0b464905)

3 months agotestsuite: Add testcase for already fixed PR [PR107385]
Jakub Jelinek [Thu, 15 Feb 2024 14:55:25 +0000 (15:55 +0100)] 
testsuite: Add testcase for already fixed PR [PR107385]

This testcase has been fixed by the PR113921 fix, but unlike testcase
in there this one is not target specific.

2024-02-15  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/107385
* gcc.dg/pr107385.c: New test.

(cherry picked from commit 5459a9074afabf700f055fc8164f88dadb1c39b0)

3 months agoexpand: Fix handling of asm goto outputs vs. PHI argument adjustments [PR113921]
Jakub Jelinek [Thu, 15 Feb 2024 14:53:01 +0000 (15:53 +0100)] 
expand: Fix handling of asm goto outputs vs. PHI argument adjustments [PR113921]

The Linux kernel and the following testcase distilled from it is
miscompiled, because tree-outof-ssa.cc (eliminate_phi) emits some
fixups on some of the edges (but doesn't commit edge insertions).
Later expand_asm_stmt emits further instructions on the same edge.
Now the problem is that expand_asm_stmt uses insert_insn_on_edge
to add its own fixups, but that function appends to the existing
sequence on the edge if any.  And the bug triggers when the
fixup sequence emitted by eliminate_phi uses a pseudo which the
fixup sequence emitted by expand_asm_stmt later on sets.
So, we end up with
  (set (reg A) (asm_operands ...))
and on one of the edges queued sequence
  (set (reg C) (reg B)) // added by eliminate_phi
  (set (reg B) (reg A)) // added by expand_asm_stmt
That is wrong, what we emit by expand_asm_stmt needs to be as close
to the asm_operands as possible (they aren't known until expand_asm_stmt
is called, the PHI fixup code assumes it is reg B which holds the right
value) and the PHI adjustments need to be done after it.

So, the following patch introduces a prepend_insn_to_edge function and
uses it from expand_asm_stmt, so that we queue
  (set (reg B) (reg A)) // added by expand_asm_stmt
  (set (reg C) (reg B)) // added by eliminate_phi
instead and so the value from the asm_operands output propagates correctly
to the PHI result.

2024-02-15  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/113921
* cfgrtl.h (prepend_insn_to_edge): New declaration.
* cfgrtl.c (insert_insn_on_edge): Clarify behavior in function
comment.
(prepend_insn_to_edge): New function.
* cfgexpand.c (expand_asm_stmt): Use prepend_insn_to_edge instead of
insert_insn_on_edge.

* gcc.target/i386/pr113921.c: New test.

(cherry picked from commit 2b4efc5db2aedb59196987300e14951d08cd7106)

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3 months agolibgfortran: avoid duplicate libraries in spec
Francois-Xavier Coudert [Sun, 11 Feb 2024 13:51:39 +0000 (14:51 +0100)] 
libgfortran: avoid duplicate libraries in spec

The linking of libgcc is already present in %(liborig), so the current
situation duplicates libraries. This was not an issue until macOS's new
linker started giving warnings for such cases.

libgfortran/ChangeLog:

PR libfortran/110651
* libgfortran.spec.in: Remove duplicate libraries.

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3 months agoFortran: fix bounds-checking errors for CLASS array dummies [PR104908]
Harald Anlauf [Sat, 27 Jan 2024 16:41:43 +0000 (17:41 +0100)] 
Fortran: fix bounds-checking errors for CLASS array dummies [PR104908]

Commit r11-1235 addressed issues with bounds of unlimited polymorphic array
dummies.  However, using the descriptor from sym->backend_decl does break
the case of CLASS array dummies.  The obvious solution is to restrict the
fix to the unlimited polymorphic case, thus keeping the original descriptor
in the ordinary case.

gcc/fortran/ChangeLog:

PR fortran/104908
* trans-array.c (gfc_conv_array_ref): Restrict use of transformed
descriptor (sym->backend_decl) to the unlimited polymorphic case.

gcc/testsuite/ChangeLog:

PR fortran/104908
* gfortran.dg/pr104908.f90: New test.

(cherry picked from commit ce61de1b8a1bb3a22118e900376f380768f2ba59)

3 months agosra: Disqualify bases of operands of asm gotos
Martin Jambor [Fri, 9 Feb 2024 17:58:43 +0000 (18:58 +0100)] 
sra: Disqualify bases of operands of asm gotos

PR 110422 shows that SRA can ICE assuming there is a single edge
outgoing from a block terminated with an asm goto.  We need that for
BB-terminating statements so that any adjustments they make to the
aggregates can be copied over to their replacements.  Because we can't
have that after ASM gotos, we need to punt.

gcc/ChangeLog:

2024-01-17  Martin Jambor  <mjambor@suse.cz>

PR tree-optimization/110422
* tree-sra.c (scan_function): Disqualify bases of operands of asm
gotos.

gcc/testsuite/ChangeLog:

2024-01-17  Martin Jambor  <mjambor@suse.cz>

PR tree-optimization/110422
* gcc.dg/torture/pr110422.c: New test.

(cherry picked from commit 2b7204c52392c1c0da9c91a5feae0c44018a6f37)

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3 months agomips: Fix missing mode in neg<mode:MSA>2
Xi Ruoyao [Mon, 5 Feb 2024 12:17:25 +0000 (20:17 +0800)] 
mips: Fix missing mode in neg<mode:MSA>2

I was too sleepy writting this :(.

gcc/ChangeLog:

* config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
neg.

(cherry picked from commit 55357960fbddd261e32f088f5dd328d58b0f25b3)

3 months agoMIPS: Fix wrong MSA FP vector negation
Xi Ruoyao [Fri, 2 Feb 2024 19:35:07 +0000 (03:35 +0800)] 
MIPS: Fix wrong MSA FP vector negation

We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
fail when Python is built with MSA enabled.

Use the bnegi.df instructions to simply reverse the sign bit instead.

gcc/ChangeLog:

* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
(neg<mode>2): Change the mode iterator from MSA to IMSA because
in FP arithmetic we cannot use (0 - x) for -x.
(neg<mode>2): New define_insn to implement FP vector negation,
using a bnegi instruction to negate the sign bit.

(cherry picked from commit 4d7fe3cf82505b45719356a2e51b1480b5ee21d6)