From 971ea24b9a143d19114aba224fcd550e7981f403 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 23 Apr 2024 09:34:18 -0700 Subject: [PATCH] 6.8-stable patches added patches: net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch --- ...g-eee-on-mt7531-switch-on-all-boards.patch | 101 ++++++++++++++++++ ...s-on-all-25mhz-and-40mhz-xtal-mt7530.patch | 79 ++++++++++++++ queue-6.8/series | 2 + 3 files changed, 182 insertions(+) create mode 100644 queue-6.8/net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch create mode 100644 queue-6.8/net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch diff --git a/queue-6.8/net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch b/queue-6.8/net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch new file mode 100644 index 0000000000..b52f0936f9 --- /dev/null +++ b/queue-6.8/net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch @@ -0,0 +1,101 @@ +From 06dfcd4098cfdc4d4577d94793a4f9125386da8b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Mon, 8 Apr 2024 10:08:53 +0300 +Subject: net: dsa: mt7530: fix enabling EEE on MT7531 switch on all boards +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Arınç ÜNAL + +commit 06dfcd4098cfdc4d4577d94793a4f9125386da8b upstream. + +The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") +brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is +enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board +(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting +the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to +SkyLake Huang (黃啟澤) from MediaTek for providing information on the +internal EEE switch bit. + +There are existing boards that were not designed to pull the pin low. +Because of that, the EEE status currently depends on the board design. + +The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually +used to control an LED. Once the bit is unset, the pin will be low. That +will make the active low LED turn on. The pin is controlled by the switch +PHY. It seems that the PHY controls the pin in the way that it inverts the +pin state. That means depending on the wiring of the LED connected to +LAN2LED0 on the board, the LED may be on without an active link. + +To not cause this unwanted behaviour whilst enabling EEE on all boards, set +the internal EEE switch bit on the CORE_PLL_GROUP4 register. + +My testing on MT7531 shows a certain amount of traffic loss when EEE is +enabled. That said, I haven't come across a board that enables EEE. So +enable EEE on the switch MACs but disable EEE advertisement on the switch +PHYs. This way, we don't change the behaviour of the majority of the boards +that have this switch. The mediatek-ge PHY driver already disables EEE +advertisement on the switch PHYs but my testing shows that it is somehow +enabled afterwards. Disabling EEE advertisement before the PHY driver +initialises keeps it off. + +With this change, EEE can now be enabled using ethtool. + +Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features") +Reviewed-by: Florian Fainelli +Signed-off-by: Arınç ÜNAL +Tested-by: Daniel Golle +Reviewed-by: Daniel Golle +Link: https://lore.kernel.org/r/20240408-for-net-mt7530-fix-eee-for-mt7531-mt7988-v3-1-84fdef1f008b@arinc9.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Arınç ÜNAL +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/dsa/mt7530.c | 17 ++++++++++++----- + drivers/net/dsa/mt7530.h | 1 + + 2 files changed, 13 insertions(+), 5 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2712,18 +2712,25 @@ mt7531_setup(struct dsa_switch *ds) + priv->p5_interface = PHY_INTERFACE_MODE_NA; + priv->p6_interface = PHY_INTERFACE_MODE_NA; + +- /* Enable PHY core PLL, since phy_device has not yet been created +- * provided for phy_[read,write]_mmd_indirect is called, we provide +- * our own mt7531_ind_mmd_phy_[read,write] to complete this +- * function. ++ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since ++ * phy_device has not yet been created provided for ++ * phy_[read,write]_mmd_indirect is called, we provide our own ++ * mt7531_ind_mmd_phy_[read,write] to complete this function. + */ + val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, + MDIO_MMD_VEND2, CORE_PLL_GROUP4); +- val |= MT7531_PHY_PLL_BYPASS_MODE; ++ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE; + val &= ~MT7531_PHY_PLL_OFF; + mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, + CORE_PLL_GROUP4, val); + ++ /* Disable EEE advertisement on the switch PHYs. */ ++ for (i = MT753X_CTRL_PHY_ADDR; ++ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) { ++ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV, ++ 0); ++ } ++ + mt7531_setup_common(ds); + + /* Setup VLAN ID 0 for VLAN-unaware bridges */ +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -634,6 +634,7 @@ enum mt7531_clk_skew { + #define RG_SYSPLL_DDSFBK_EN BIT(12) + #define RG_SYSPLL_BIAS_EN BIT(11) + #define RG_SYSPLL_BIAS_LPF_EN BIT(10) ++#define MT7531_RG_SYSPLL_DMY2 BIT(6) + #define MT7531_PHY_PLL_OFF BIT(5) + #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) + diff --git a/queue-6.8/net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch b/queue-6.8/net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch new file mode 100644 index 0000000000..ef8b801fd0 --- /dev/null +++ b/queue-6.8/net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch @@ -0,0 +1,79 @@ +From 5f563c31ff0c40ce395d0bae7daa94c7950dac97 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= +Date: Wed, 20 Mar 2024 23:45:30 +0300 +Subject: net: dsa: mt7530: fix improper frames on all 25MHz and 40MHz XTAL MT7530 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Arınç ÜNAL + +commit 5f563c31ff0c40ce395d0bae7daa94c7950dac97 upstream. + +The MT7530 switch after reset initialises with a core clock frequency that +works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock +frequency must be set to 500MHz. + +The mt7530_pll_setup() function is responsible of setting the core clock +frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This +causes MT7530 switch with 25MHz XTAL to egress and ingress frames +improperly. + +Introduce a check to run it only on MT7530 with 40MHz XTAL. + +The core clock frequency is set by writing to a switch PHY's register. +Access to the PHY's register is done via the MDIO bus the switch is also +on. Therefore, it works only when the switch makes switch PHYs listen on +the MDIO bus the switch is on. This is controlled either by the state of +the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the +modifiable trap register. + +When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means +accessing PHY registers via the PHY indirect access control register of the +switch. + +When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means +accessing PHY registers via the MDIO bus the switch is on. + +For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high, +the core clock frequency won't be set to 500MHz, causing the switch to +egress and ingress frames improperly. + +Run mt7530_pll_setup() after PHY direct access is set on the modifiable +trap register. + +With these two changes, all MT7530 switches with 25MHz and 40MHz, and +P1_LED_1 pulled high or low, will egress and ingress frames properly. + +Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039 +Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") +Signed-off-by: Arınç ÜNAL +Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com +Signed-off-by: Paolo Abeni +Signed-off-by: Arınç ÜNAL +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/dsa/mt7530.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2471,8 +2471,6 @@ mt7530_setup(struct dsa_switch *ds) + SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | + SYS_CTRL_REG_RST); + +- mt7530_pll_setup(priv); +- + /* Lower Tx driving for TRGMII path */ + for (i = 0; i < NUM_TRGMII_CTRL; i++) + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), +@@ -2490,6 +2488,9 @@ mt7530_setup(struct dsa_switch *ds) + + priv->p6_interface = PHY_INTERFACE_MODE_NA; + ++ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) ++ mt7530_pll_setup(priv); ++ + mt753x_trap_frames(priv); + + /* Enable and reset MIB counters */ diff --git a/queue-6.8/series b/queue-6.8/series index 4839a2eee1..dbd5bf1f0f 100644 --- a/queue-6.8/series +++ b/queue-6.8/series @@ -148,3 +148,5 @@ bootconfig-use-memblock_free_late-to-free-xbc-memory-to-buddy.patch squashfs-check-the-inode-number-is-not-the-invalid-value-of-zero.patch nilfs2-fix-oob-in-nilfs_set_de_type.patch fork-defer-linking-file-vma-until-vma-is-fully-initialized.patch +net-dsa-mt7530-fix-improper-frames-on-all-25mhz-and-40mhz-xtal-mt7530.patch +net-dsa-mt7530-fix-enabling-eee-on-mt7531-switch-on-all-boards.patch -- 2.39.2