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b7e8f433 VK |
1 | // SPDX-License-Identifier: BSD-3-Clause |
2 | /* | |
4f23d2a5 | 3 | * Copyright (c) 2020, Linaro Limited |
b7e8f433 VK |
4 | */ |
5 | ||
6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
6d91e201 | 7 | #include <dt-bindings/clock/qcom,gcc-sm8350.h> |
b7e8f433 | 8 | #include <dt-bindings/clock/qcom,rpmh.h> |
f0360a7c | 9 | #include <dt-bindings/gpio/gpio.h> |
84c856d0 | 10 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
b7e8f433 | 11 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
b7e8f433 VK |
12 | #include <dt-bindings/power/qcom-rpmpd.h> |
13 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> | |
20f9d94e | 14 | #include <dt-bindings/thermal/thermal.h> |
f11d3e7d | 15 | #include <dt-bindings/interconnect/qcom,sm8350.h> |
b7e8f433 VK |
16 | |
17 | / { | |
18 | interrupt-parent = <&intc>; | |
19 | ||
20 | #address-cells = <2>; | |
21 | #size-cells = <2>; | |
22 | ||
23 | chosen { }; | |
24 | ||
25 | clocks { | |
26 | xo_board: xo-board { | |
27 | compatible = "fixed-clock"; | |
28 | #clock-cells = <0>; | |
29 | clock-frequency = <38400000>; | |
30 | clock-output-names = "xo_board"; | |
31 | }; | |
32 | ||
33 | sleep_clk: sleep-clk { | |
34 | compatible = "fixed-clock"; | |
35 | clock-frequency = <32000>; | |
36 | #clock-cells = <0>; | |
37 | }; | |
38 | }; | |
39 | ||
40 | cpus { | |
41 | #address-cells = <2>; | |
42 | #size-cells = <0>; | |
43 | ||
44 | CPU0: cpu@0 { | |
45 | device_type = "cpu"; | |
46 | compatible = "qcom,kryo685"; | |
47 | reg = <0x0 0x0>; | |
48 | enable-method = "psci"; | |
49 | next-level-cache = <&L2_0>; | |
ccbb3abb | 50 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
51 | power-domains = <&CPU_PD0>; |
52 | power-domain-names = "psci"; | |
20f9d94e | 53 | #cooling-cells = <2>; |
b7e8f433 VK |
54 | L2_0: l2-cache { |
55 | compatible = "cache"; | |
56 | next-level-cache = <&L3_0>; | |
57 | L3_0: l3-cache { | |
58 | compatible = "cache"; | |
59 | }; | |
60 | }; | |
61 | }; | |
62 | ||
63 | CPU1: cpu@100 { | |
64 | device_type = "cpu"; | |
65 | compatible = "qcom,kryo685"; | |
66 | reg = <0x0 0x100>; | |
67 | enable-method = "psci"; | |
68 | next-level-cache = <&L2_100>; | |
ccbb3abb | 69 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
70 | power-domains = <&CPU_PD1>; |
71 | power-domain-names = "psci"; | |
20f9d94e | 72 | #cooling-cells = <2>; |
b7e8f433 VK |
73 | L2_100: l2-cache { |
74 | compatible = "cache"; | |
75 | next-level-cache = <&L3_0>; | |
76 | }; | |
77 | }; | |
78 | ||
79 | CPU2: cpu@200 { | |
80 | device_type = "cpu"; | |
81 | compatible = "qcom,kryo685"; | |
82 | reg = <0x0 0x200>; | |
83 | enable-method = "psci"; | |
84 | next-level-cache = <&L2_200>; | |
ccbb3abb | 85 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
86 | power-domains = <&CPU_PD2>; |
87 | power-domain-names = "psci"; | |
20f9d94e | 88 | #cooling-cells = <2>; |
b7e8f433 VK |
89 | L2_200: l2-cache { |
90 | compatible = "cache"; | |
91 | next-level-cache = <&L3_0>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | CPU3: cpu@300 { | |
96 | device_type = "cpu"; | |
97 | compatible = "qcom,kryo685"; | |
98 | reg = <0x0 0x300>; | |
99 | enable-method = "psci"; | |
100 | next-level-cache = <&L2_300>; | |
ccbb3abb | 101 | qcom,freq-domain = <&cpufreq_hw 0>; |
07ddb302 BA |
102 | power-domains = <&CPU_PD3>; |
103 | power-domain-names = "psci"; | |
20f9d94e | 104 | #cooling-cells = <2>; |
b7e8f433 VK |
105 | L2_300: l2-cache { |
106 | compatible = "cache"; | |
107 | next-level-cache = <&L3_0>; | |
108 | }; | |
109 | }; | |
110 | ||
111 | CPU4: cpu@400 { | |
112 | device_type = "cpu"; | |
113 | compatible = "qcom,kryo685"; | |
114 | reg = <0x0 0x400>; | |
115 | enable-method = "psci"; | |
116 | next-level-cache = <&L2_400>; | |
ccbb3abb | 117 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
118 | power-domains = <&CPU_PD4>; |
119 | power-domain-names = "psci"; | |
20f9d94e | 120 | #cooling-cells = <2>; |
b7e8f433 VK |
121 | L2_400: l2-cache { |
122 | compatible = "cache"; | |
123 | next-level-cache = <&L3_0>; | |
124 | }; | |
125 | }; | |
126 | ||
127 | CPU5: cpu@500 { | |
128 | device_type = "cpu"; | |
129 | compatible = "qcom,kryo685"; | |
130 | reg = <0x0 0x500>; | |
131 | enable-method = "psci"; | |
132 | next-level-cache = <&L2_500>; | |
ccbb3abb | 133 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
134 | power-domains = <&CPU_PD5>; |
135 | power-domain-names = "psci"; | |
20f9d94e | 136 | #cooling-cells = <2>; |
b7e8f433 VK |
137 | L2_500: l2-cache { |
138 | compatible = "cache"; | |
139 | next-level-cache = <&L3_0>; | |
140 | }; | |
141 | ||
142 | }; | |
143 | ||
144 | CPU6: cpu@600 { | |
145 | device_type = "cpu"; | |
146 | compatible = "qcom,kryo685"; | |
147 | reg = <0x0 0x600>; | |
148 | enable-method = "psci"; | |
149 | next-level-cache = <&L2_600>; | |
ccbb3abb | 150 | qcom,freq-domain = <&cpufreq_hw 1>; |
07ddb302 BA |
151 | power-domains = <&CPU_PD6>; |
152 | power-domain-names = "psci"; | |
20f9d94e | 153 | #cooling-cells = <2>; |
b7e8f433 VK |
154 | L2_600: l2-cache { |
155 | compatible = "cache"; | |
156 | next-level-cache = <&L3_0>; | |
157 | }; | |
158 | }; | |
159 | ||
160 | CPU7: cpu@700 { | |
161 | device_type = "cpu"; | |
162 | compatible = "qcom,kryo685"; | |
163 | reg = <0x0 0x700>; | |
164 | enable-method = "psci"; | |
165 | next-level-cache = <&L2_700>; | |
ccbb3abb | 166 | qcom,freq-domain = <&cpufreq_hw 2>; |
07ddb302 BA |
167 | power-domains = <&CPU_PD7>; |
168 | power-domain-names = "psci"; | |
20f9d94e | 169 | #cooling-cells = <2>; |
b7e8f433 VK |
170 | L2_700: l2-cache { |
171 | compatible = "cache"; | |
172 | next-level-cache = <&L3_0>; | |
173 | }; | |
174 | }; | |
07ddb302 BA |
175 | |
176 | cpu-map { | |
177 | cluster0 { | |
178 | core0 { | |
179 | cpu = <&CPU0>; | |
180 | }; | |
181 | ||
182 | core1 { | |
183 | cpu = <&CPU1>; | |
184 | }; | |
185 | ||
186 | core2 { | |
187 | cpu = <&CPU2>; | |
188 | }; | |
189 | ||
190 | core3 { | |
191 | cpu = <&CPU3>; | |
192 | }; | |
193 | ||
194 | core4 { | |
195 | cpu = <&CPU4>; | |
196 | }; | |
197 | ||
198 | core5 { | |
199 | cpu = <&CPU5>; | |
200 | }; | |
201 | ||
202 | core6 { | |
203 | cpu = <&CPU6>; | |
204 | }; | |
205 | ||
206 | core7 { | |
207 | cpu = <&CPU7>; | |
208 | }; | |
209 | }; | |
210 | }; | |
211 | ||
212 | idle-states { | |
213 | entry-method = "psci"; | |
214 | ||
215 | LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { | |
216 | compatible = "arm,idle-state"; | |
217 | idle-state-name = "silver-rail-power-collapse"; | |
218 | arm,psci-suspend-param = <0x40000004>; | |
219 | entry-latency-us = <355>; | |
220 | exit-latency-us = <909>; | |
221 | min-residency-us = <3934>; | |
222 | local-timer-stop; | |
223 | }; | |
224 | ||
225 | BIG_CPU_SLEEP_0: cpu-sleep-1-0 { | |
226 | compatible = "arm,idle-state"; | |
227 | idle-state-name = "gold-rail-power-collapse"; | |
228 | arm,psci-suspend-param = <0x40000004>; | |
229 | entry-latency-us = <241>; | |
230 | exit-latency-us = <1461>; | |
231 | min-residency-us = <4488>; | |
232 | local-timer-stop; | |
233 | }; | |
234 | }; | |
235 | ||
236 | domain-idle-states { | |
237 | CLUSTER_SLEEP_0: cluster-sleep-0 { | |
238 | compatible = "domain-idle-state"; | |
239 | idle-state-name = "cluster-power-collapse"; | |
240 | arm,psci-suspend-param = <0x4100c344>; | |
241 | entry-latency-us = <3263>; | |
242 | exit-latency-us = <6562>; | |
243 | min-residency-us = <9987>; | |
244 | local-timer-stop; | |
245 | }; | |
246 | }; | |
b7e8f433 VK |
247 | }; |
248 | ||
249 | firmware { | |
250 | scm: scm { | |
251 | compatible = "qcom,scm-sm8350", "qcom,scm"; | |
252 | #reset-cells = <1>; | |
253 | }; | |
254 | }; | |
255 | ||
256 | memory@80000000 { | |
257 | device_type = "memory"; | |
258 | /* We expect the bootloader to fill in the size */ | |
259 | reg = <0x0 0x80000000 0x0 0x0>; | |
260 | }; | |
261 | ||
262 | pmu { | |
263 | compatible = "arm,armv8-pmuv3"; | |
794d3e30 | 264 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
b7e8f433 VK |
265 | }; |
266 | ||
267 | psci { | |
268 | compatible = "arm,psci-1.0"; | |
269 | method = "smc"; | |
07ddb302 BA |
270 | |
271 | CPU_PD0: cpu0 { | |
272 | #power-domain-cells = <0>; | |
273 | power-domains = <&CLUSTER_PD>; | |
274 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
275 | }; | |
276 | ||
277 | CPU_PD1: cpu1 { | |
278 | #power-domain-cells = <0>; | |
279 | power-domains = <&CLUSTER_PD>; | |
280 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
281 | }; | |
282 | ||
283 | CPU_PD2: cpu2 { | |
284 | #power-domain-cells = <0>; | |
285 | power-domains = <&CLUSTER_PD>; | |
286 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
287 | }; | |
288 | ||
289 | CPU_PD3: cpu3 { | |
290 | #power-domain-cells = <0>; | |
291 | power-domains = <&CLUSTER_PD>; | |
292 | domain-idle-states = <&LITTLE_CPU_SLEEP_0>; | |
293 | }; | |
294 | ||
295 | CPU_PD4: cpu4 { | |
296 | #power-domain-cells = <0>; | |
297 | power-domains = <&CLUSTER_PD>; | |
298 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
299 | }; | |
300 | ||
301 | CPU_PD5: cpu5 { | |
302 | #power-domain-cells = <0>; | |
303 | power-domains = <&CLUSTER_PD>; | |
304 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
305 | }; | |
306 | ||
307 | CPU_PD6: cpu6 { | |
308 | #power-domain-cells = <0>; | |
309 | power-domains = <&CLUSTER_PD>; | |
310 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
311 | }; | |
312 | ||
313 | CPU_PD7: cpu7 { | |
314 | #power-domain-cells = <0>; | |
315 | power-domains = <&CLUSTER_PD>; | |
316 | domain-idle-states = <&BIG_CPU_SLEEP_0>; | |
317 | }; | |
318 | ||
319 | CLUSTER_PD: cpu-cluster0 { | |
320 | #power-domain-cells = <0>; | |
321 | domain-idle-states = <&CLUSTER_SLEEP_0>; | |
322 | }; | |
b7e8f433 VK |
323 | }; |
324 | ||
325 | reserved_memory: reserved-memory { | |
326 | #address-cells = <2>; | |
327 | #size-cells = <2>; | |
328 | ranges; | |
329 | ||
330 | hyp_mem: memory@80000000 { | |
331 | reg = <0x0 0x80000000 0x0 0x600000>; | |
332 | no-map; | |
333 | }; | |
334 | ||
335 | xbl_aop_mem: memory@80700000 { | |
336 | no-map; | |
337 | reg = <0x0 0x80700000 0x0 0x160000>; | |
338 | }; | |
339 | ||
340 | cmd_db: memory@80860000 { | |
341 | compatible = "qcom,cmd-db"; | |
342 | reg = <0x0 0x80860000 0x0 0x20000>; | |
343 | no-map; | |
344 | }; | |
345 | ||
346 | reserved_xbl_uefi_log: memory@80880000 { | |
347 | reg = <0x0 0x80880000 0x0 0x14000>; | |
348 | no-map; | |
349 | }; | |
350 | ||
351 | smem_mem: memory@80900000 { | |
352 | reg = <0x0 0x80900000 0x0 0x200000>; | |
353 | no-map; | |
354 | }; | |
355 | ||
356 | cpucp_fw_mem: memory@80b00000 { | |
357 | reg = <0x0 0x80b00000 0x0 0x100000>; | |
358 | no-map; | |
359 | }; | |
360 | ||
361 | cdsp_secure_heap: memory@80c00000 { | |
362 | reg = <0x0 0x80c00000 0x0 0x4600000>; | |
363 | no-map; | |
364 | }; | |
365 | ||
366 | pil_camera_mem: mmeory@85200000 { | |
367 | reg = <0x0 0x85200000 0x0 0x500000>; | |
368 | no-map; | |
369 | }; | |
370 | ||
371 | pil_video_mem: memory@85700000 { | |
372 | reg = <0x0 0x85700000 0x0 0x500000>; | |
373 | no-map; | |
374 | }; | |
375 | ||
376 | pil_cvp_mem: memory@85c00000 { | |
377 | reg = <0x0 0x85c00000 0x0 0x500000>; | |
378 | no-map; | |
379 | }; | |
380 | ||
381 | pil_adsp_mem: memory@86100000 { | |
382 | reg = <0x0 0x86100000 0x0 0x2100000>; | |
383 | no-map; | |
384 | }; | |
385 | ||
386 | pil_slpi_mem: memory@88200000 { | |
387 | reg = <0x0 0x88200000 0x0 0x1500000>; | |
388 | no-map; | |
389 | }; | |
390 | ||
391 | pil_cdsp_mem: memory@89700000 { | |
392 | reg = <0x0 0x89700000 0x0 0x1e00000>; | |
393 | no-map; | |
394 | }; | |
395 | ||
396 | pil_ipa_fw_mem: memory@8b500000 { | |
397 | reg = <0x0 0x8b500000 0x0 0x10000>; | |
398 | no-map; | |
399 | }; | |
400 | ||
401 | pil_ipa_gsi_mem: memory@8b510000 { | |
402 | reg = <0x0 0x8b510000 0x0 0xa000>; | |
403 | no-map; | |
404 | }; | |
405 | ||
406 | pil_gpu_mem: memory@8b51a000 { | |
407 | reg = <0x0 0x8b51a000 0x0 0x2000>; | |
408 | no-map; | |
409 | }; | |
410 | ||
411 | pil_spss_mem: memory@8b600000 { | |
412 | reg = <0x0 0x8b600000 0x0 0x100000>; | |
413 | no-map; | |
414 | }; | |
415 | ||
416 | pil_modem_mem: memory@8b800000 { | |
417 | reg = <0x0 0x8b800000 0x0 0x10000000>; | |
418 | no-map; | |
419 | }; | |
420 | ||
774890c9 VK |
421 | rmtfs_mem: memory@9b800000 { |
422 | compatible = "qcom,rmtfs-mem"; | |
423 | reg = <0x0 0x9b800000 0x0 0x280000>; | |
424 | no-map; | |
425 | ||
426 | qcom,client-id = <1>; | |
427 | qcom,vmid = <15>; | |
428 | }; | |
429 | ||
b7e8f433 VK |
430 | hyp_reserved_mem: memory@d0000000 { |
431 | reg = <0x0 0xd0000000 0x0 0x800000>; | |
432 | no-map; | |
433 | }; | |
434 | ||
435 | pil_trustedvm_mem: memory@d0800000 { | |
436 | reg = <0x0 0xd0800000 0x0 0x76f7000>; | |
437 | no-map; | |
438 | }; | |
439 | ||
440 | qrtr_shbuf: memory@d7ef7000 { | |
441 | reg = <0x0 0xd7ef7000 0x0 0x9000>; | |
442 | no-map; | |
443 | }; | |
444 | ||
445 | chan0_shbuf: memory@d7f00000 { | |
446 | reg = <0x0 0xd7f00000 0x0 0x80000>; | |
447 | no-map; | |
448 | }; | |
449 | ||
450 | chan1_shbuf: memory@d7f80000 { | |
451 | reg = <0x0 0xd7f80000 0x0 0x80000>; | |
452 | no-map; | |
453 | }; | |
454 | ||
455 | removed_mem: memory@d8800000 { | |
456 | reg = <0x0 0xd8800000 0x0 0x6800000>; | |
457 | no-map; | |
458 | }; | |
459 | }; | |
460 | ||
461 | smem: qcom,smem { | |
462 | compatible = "qcom,smem"; | |
463 | memory-region = <&smem_mem>; | |
464 | hwlocks = <&tcsr_mutex 3>; | |
465 | }; | |
466 | ||
03a41991 VK |
467 | smp2p-adsp { |
468 | compatible = "qcom,smp2p"; | |
469 | qcom,smem = <443>, <429>; | |
470 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
471 | IPCC_MPROC_SIGNAL_SMP2P | |
472 | IRQ_TYPE_EDGE_RISING>; | |
473 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
474 | IPCC_MPROC_SIGNAL_SMP2P>; | |
475 | ||
476 | qcom,local-pid = <0>; | |
477 | qcom,remote-pid = <2>; | |
478 | ||
479 | smp2p_adsp_out: master-kernel { | |
480 | qcom,entry-name = "master-kernel"; | |
481 | #qcom,smem-state-cells = <1>; | |
482 | }; | |
483 | ||
484 | smp2p_adsp_in: slave-kernel { | |
485 | qcom,entry-name = "slave-kernel"; | |
486 | interrupt-controller; | |
487 | #interrupt-cells = <2>; | |
488 | }; | |
489 | }; | |
490 | ||
491 | smp2p-cdsp { | |
492 | compatible = "qcom,smp2p"; | |
493 | qcom,smem = <94>, <432>; | |
494 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
495 | IPCC_MPROC_SIGNAL_SMP2P | |
496 | IRQ_TYPE_EDGE_RISING>; | |
497 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
498 | IPCC_MPROC_SIGNAL_SMP2P>; | |
499 | ||
500 | qcom,local-pid = <0>; | |
501 | qcom,remote-pid = <5>; | |
502 | ||
503 | smp2p_cdsp_out: master-kernel { | |
504 | qcom,entry-name = "master-kernel"; | |
505 | #qcom,smem-state-cells = <1>; | |
506 | }; | |
507 | ||
508 | smp2p_cdsp_in: slave-kernel { | |
509 | qcom,entry-name = "slave-kernel"; | |
510 | interrupt-controller; | |
511 | #interrupt-cells = <2>; | |
512 | }; | |
513 | }; | |
514 | ||
515 | smp2p-modem { | |
516 | compatible = "qcom,smp2p"; | |
517 | qcom,smem = <435>, <428>; | |
518 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
519 | IPCC_MPROC_SIGNAL_SMP2P | |
520 | IRQ_TYPE_EDGE_RISING>; | |
521 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
522 | IPCC_MPROC_SIGNAL_SMP2P>; | |
523 | ||
524 | qcom,local-pid = <0>; | |
525 | qcom,remote-pid = <1>; | |
526 | ||
527 | smp2p_modem_out: master-kernel { | |
528 | qcom,entry-name = "master-kernel"; | |
529 | #qcom,smem-state-cells = <1>; | |
530 | }; | |
531 | ||
532 | smp2p_modem_in: slave-kernel { | |
533 | qcom,entry-name = "slave-kernel"; | |
534 | interrupt-controller; | |
535 | #interrupt-cells = <2>; | |
536 | }; | |
f11d3e7d AE |
537 | |
538 | ipa_smp2p_out: ipa-ap-to-modem { | |
539 | qcom,entry-name = "ipa"; | |
540 | #qcom,smem-state-cells = <1>; | |
541 | }; | |
542 | ||
543 | ipa_smp2p_in: ipa-modem-to-ap { | |
544 | qcom,entry-name = "ipa"; | |
545 | interrupt-controller; | |
546 | #interrupt-cells = <2>; | |
547 | }; | |
03a41991 VK |
548 | }; |
549 | ||
550 | smp2p-slpi { | |
551 | compatible = "qcom,smp2p"; | |
552 | qcom,smem = <481>, <430>; | |
553 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
554 | IPCC_MPROC_SIGNAL_SMP2P | |
555 | IRQ_TYPE_EDGE_RISING>; | |
556 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
557 | IPCC_MPROC_SIGNAL_SMP2P>; | |
558 | ||
559 | qcom,local-pid = <0>; | |
560 | qcom,remote-pid = <3>; | |
561 | ||
562 | smp2p_slpi_out: master-kernel { | |
563 | qcom,entry-name = "master-kernel"; | |
564 | #qcom,smem-state-cells = <1>; | |
565 | }; | |
566 | ||
567 | smp2p_slpi_in: slave-kernel { | |
568 | qcom,entry-name = "slave-kernel"; | |
569 | interrupt-controller; | |
570 | #interrupt-cells = <2>; | |
571 | }; | |
572 | }; | |
573 | ||
b7e8f433 VK |
574 | soc: soc@0 { |
575 | #address-cells = <2>; | |
576 | #size-cells = <2>; | |
577 | ranges = <0 0 0 0 0x10 0>; | |
578 | dma-ranges = <0 0 0 0 0x10 0>; | |
579 | compatible = "simple-bus"; | |
580 | ||
581 | gcc: clock-controller@100000 { | |
582 | compatible = "qcom,gcc-sm8350"; | |
583 | reg = <0x0 0x00100000 0x0 0x1f0000>; | |
584 | #clock-cells = <1>; | |
585 | #reset-cells = <1>; | |
586 | #power-domain-cells = <1>; | |
587 | clock-names = "bi_tcxo", "sleep_clk"; | |
588 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; | |
589 | }; | |
590 | ||
591 | ipcc: mailbox@408000 { | |
592 | compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; | |
593 | reg = <0 0x00408000 0 0x1000>; | |
594 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
595 | interrupt-controller; | |
596 | #interrupt-cells = <3>; | |
597 | #mbox-cells = <2>; | |
598 | }; | |
599 | ||
e84d04a2 KD |
600 | qupv3_id_2: geniqup@8c0000 { |
601 | compatible = "qcom,geni-se-qup"; | |
602 | reg = <0x0 0x008c0000 0x0 0x6000>; | |
603 | clock-names = "m-ahb", "s-ahb"; | |
604 | clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, | |
605 | <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; | |
606 | #address-cells = <2>; | |
607 | #size-cells = <2>; | |
608 | ranges; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
87f0b434 | 612 | qupv3_id_0: geniqup@9c0000 { |
b7e8f433 VK |
613 | compatible = "qcom,geni-se-qup"; |
614 | reg = <0x0 0x009c0000 0x0 0x6000>; | |
615 | clock-names = "m-ahb", "s-ahb"; | |
6d91e201 VK |
616 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
617 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
b7e8f433 VK |
618 | #address-cells = <2>; |
619 | #size-cells = <2>; | |
620 | ranges; | |
621 | status = "disabled"; | |
622 | ||
623 | uart2: serial@98c000 { | |
624 | compatible = "qcom,geni-debug-uart"; | |
625 | reg = <0 0x0098c000 0 0x4000>; | |
626 | clock-names = "se"; | |
6d91e201 | 627 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
b7e8f433 VK |
628 | pinctrl-names = "default"; |
629 | pinctrl-0 = <&qup_uart3_default_state>; | |
630 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
631 | #address-cells = <1>; | |
632 | #size-cells = <0>; | |
633 | status = "disabled"; | |
634 | }; | |
635 | }; | |
636 | ||
06bf656e JM |
637 | qupv3_id_1: geniqup@ac0000 { |
638 | compatible = "qcom,geni-se-qup"; | |
639 | reg = <0x0 0x00ac0000 0x0 0x6000>; | |
640 | clock-names = "m-ahb", "s-ahb"; | |
641 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, | |
642 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
643 | #address-cells = <2>; | |
644 | #size-cells = <2>; | |
645 | ranges; | |
646 | status = "disabled"; | |
647 | ||
648 | i2c13: i2c@a94000 { | |
649 | compatible = "qcom,geni-i2c"; | |
650 | reg = <0 0x00a94000 0 0x4000>; | |
651 | clock-names = "se"; | |
652 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
653 | pinctrl-names = "default"; | |
654 | pinctrl-0 = <&qup_i2c13_default_state>; | |
655 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
656 | #address-cells = <1>; | |
657 | #size-cells = <0>; | |
658 | status = "disabled"; | |
659 | }; | |
660 | }; | |
661 | ||
187f65b7 VK |
662 | apps_smmu: iommu@15000000 { |
663 | compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; | |
664 | reg = <0 0x15000000 0 0x100000>; | |
665 | #iommu-cells = <2>; | |
666 | #global-interrupts = <2>; | |
667 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
668 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
669 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
670 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
671 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
672 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
673 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
674 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
675 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
676 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
677 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
678 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
679 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
680 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
681 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
682 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
683 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
684 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
685 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
686 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
687 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
688 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
689 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
690 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
691 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
692 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
693 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
694 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
695 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
696 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
697 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
698 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
699 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
700 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
701 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
702 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
703 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
704 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
705 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
706 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
707 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
708 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
709 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
710 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
711 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
712 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
713 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
714 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
715 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
716 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
717 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
718 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
719 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
720 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
721 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
722 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
723 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
724 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
725 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
726 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
727 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
728 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
729 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
730 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
731 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
732 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
733 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
734 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
735 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
736 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
737 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
738 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
739 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
740 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
741 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
742 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
743 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
744 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, | |
745 | <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
746 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
747 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, | |
748 | <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, | |
749 | <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, | |
750 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
751 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
752 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
753 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
754 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
755 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
756 | <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, | |
757 | <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, | |
758 | <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, | |
759 | <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, | |
760 | <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, | |
761 | <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, | |
762 | <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, | |
763 | <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, | |
764 | <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; | |
765 | }; | |
766 | ||
da6b2482 VK |
767 | config_noc: interconnect@1500000 { |
768 | compatible = "qcom,sm8350-config-noc"; | |
769 | reg = <0 0x01500000 0 0xa580>; | |
770 | #interconnect-cells = <1>; | |
771 | qcom,bcm-voters = <&apps_bcm_voter>; | |
772 | }; | |
773 | ||
774 | mc_virt: interconnect@1580000 { | |
775 | compatible = "qcom,sm8350-mc-virt"; | |
776 | reg = <0 0x01580000 0 0x1000>; | |
777 | #interconnect-cells = <1>; | |
778 | qcom,bcm-voters = <&apps_bcm_voter>; | |
779 | }; | |
780 | ||
781 | system_noc: interconnect@1680000 { | |
782 | compatible = "qcom,sm8350-system-noc"; | |
783 | reg = <0 0x01680000 0 0x1c200>; | |
784 | #interconnect-cells = <1>; | |
785 | qcom,bcm-voters = <&apps_bcm_voter>; | |
786 | }; | |
787 | ||
788 | aggre1_noc: interconnect@16e0000 { | |
789 | compatible = "qcom,sm8350-aggre1-noc"; | |
790 | reg = <0 0x016e0000 0 0x1f180>; | |
791 | #interconnect-cells = <1>; | |
792 | qcom,bcm-voters = <&apps_bcm_voter>; | |
793 | }; | |
794 | ||
795 | aggre2_noc: interconnect@1700000 { | |
796 | compatible = "qcom,sm8350-aggre2-noc"; | |
797 | reg = <0 0x01700000 0 0x33000>; | |
798 | #interconnect-cells = <1>; | |
799 | qcom,bcm-voters = <&apps_bcm_voter>; | |
800 | }; | |
801 | ||
802 | mmss_noc: interconnect@1740000 { | |
803 | compatible = "qcom,sm8350-mmss-noc"; | |
804 | reg = <0 0x01740000 0 0x1f080>; | |
805 | #interconnect-cells = <1>; | |
806 | qcom,bcm-voters = <&apps_bcm_voter>; | |
807 | }; | |
808 | ||
809 | lpass_ag_noc: interconnect@3c40000 { | |
810 | compatible = "qcom,sm8350-lpass-ag-noc"; | |
811 | reg = <0 0x03c40000 0 0xf080>; | |
812 | #interconnect-cells = <1>; | |
813 | qcom,bcm-voters = <&apps_bcm_voter>; | |
814 | }; | |
815 | ||
816 | compute_noc: interconnect@a0c0000{ | |
817 | compatible = "qcom,sm8350-compute-noc"; | |
818 | reg = <0 0x0a0c0000 0 0xa180>; | |
819 | #interconnect-cells = <1>; | |
820 | qcom,bcm-voters = <&apps_bcm_voter>; | |
821 | }; | |
822 | ||
f11d3e7d AE |
823 | ipa: ipa@1e40000 { |
824 | compatible = "qcom,sm8350-ipa"; | |
825 | ||
826 | iommus = <&apps_smmu 0x5c0 0x0>, | |
827 | <&apps_smmu 0x5c2 0x0>; | |
828 | reg = <0 0x1e40000 0 0x8000>, | |
829 | <0 0x1e50000 0 0x4b20>, | |
830 | <0 0x1e04000 0 0x23000>; | |
831 | reg-names = "ipa-reg", | |
832 | "ipa-shared", | |
833 | "gsi"; | |
834 | ||
835 | interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, | |
836 | <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, | |
837 | <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
838 | <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; | |
839 | interrupt-names = "ipa", | |
840 | "gsi", | |
841 | "ipa-clock-query", | |
842 | "ipa-setup-ready"; | |
843 | ||
844 | clocks = <&rpmhcc RPMH_IPA_CLK>; | |
845 | clock-names = "core"; | |
846 | ||
84173ca3 | 847 | interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, |
f11d3e7d | 848 | <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; |
84173ca3 AE |
849 | interconnect-names = "memory", |
850 | "config"; | |
f11d3e7d AE |
851 | |
852 | qcom,smem-states = <&ipa_smp2p_out 0>, | |
853 | <&ipa_smp2p_out 1>; | |
854 | qcom,smem-state-names = "ipa-clock-enabled-valid", | |
855 | "ipa-clock-enabled"; | |
856 | ||
857 | status = "disabled"; | |
858 | }; | |
859 | ||
b7e8f433 VK |
860 | tcsr_mutex: hwlock@1f40000 { |
861 | compatible = "qcom,tcsr-mutex"; | |
862 | reg = <0x0 0x01f40000 0x0 0x40000>; | |
863 | #hwlock-cells = <1>; | |
864 | }; | |
865 | ||
177fcf0a VK |
866 | mpss: remoteproc@4080000 { |
867 | compatible = "qcom,sm8350-mpss-pas"; | |
868 | reg = <0x0 0x04080000 0x0 0x4040>; | |
869 | ||
870 | interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, | |
871 | <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, | |
872 | <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, | |
873 | <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, | |
874 | <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, | |
875 | <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; | |
876 | interrupt-names = "wdog", "fatal", "ready", "handover", | |
877 | "stop-ack", "shutdown-ack"; | |
878 | ||
879 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
880 | clock-names = "xo"; | |
881 | ||
6b7cb2d2 | 882 | power-domains = <&rpmhpd 0>, |
177fcf0a | 883 | <&rpmhpd 12>; |
6b7cb2d2 | 884 | power-domain-names = "cx", "mss"; |
177fcf0a | 885 | |
84c856d0 | 886 | interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; |
da6b2482 | 887 | |
177fcf0a VK |
888 | memory-region = <&pil_modem_mem>; |
889 | ||
6b7cb2d2 SS |
890 | qcom,qmp = <&aoss_qmp>; |
891 | ||
177fcf0a VK |
892 | qcom,smem-states = <&smp2p_modem_out 0>; |
893 | qcom,smem-state-names = "stop"; | |
894 | ||
895 | status = "disabled"; | |
896 | ||
897 | glink-edge { | |
898 | interrupts-extended = <&ipcc IPCC_CLIENT_MPSS | |
899 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
900 | IRQ_TYPE_EDGE_RISING>; | |
901 | mboxes = <&ipcc IPCC_CLIENT_MPSS | |
902 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
903 | interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; | |
904 | label = "modem"; | |
905 | qcom,remote-pid = <1>; | |
906 | }; | |
907 | }; | |
908 | ||
b7e8f433 VK |
909 | pdc: interrupt-controller@b220000 { |
910 | compatible = "qcom,sm8350-pdc", "qcom,pdc"; | |
911 | reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; | |
912 | qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, | |
913 | <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, | |
914 | <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, | |
915 | <156 716 12>; | |
916 | #interrupt-cells = <2>; | |
917 | interrupt-parent = <&intc>; | |
918 | interrupt-controller; | |
919 | }; | |
920 | ||
1dee9e3b | 921 | tsens0: thermal-sensor@c263000 { |
20f9d94e RF |
922 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
923 | reg = <0 0x0c263000 0 0x1ff>, /* TM */ | |
924 | <0 0x0c222000 0 0x8>; /* SROT */ | |
925 | #qcom,sensors = <15>; | |
9e7f7b65 | 926 | interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, |
20f9d94e RF |
927 | <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; |
928 | interrupt-names = "uplow", "critical"; | |
929 | #thermal-sensor-cells = <1>; | |
930 | }; | |
931 | ||
1dee9e3b | 932 | tsens1: thermal-sensor@c265000 { |
20f9d94e RF |
933 | compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; |
934 | reg = <0 0x0c265000 0 0x1ff>, /* TM */ | |
935 | <0 0x0c223000 0 0x8>; /* SROT */ | |
936 | #qcom,sensors = <14>; | |
9e7f7b65 | 937 | interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, |
20f9d94e RF |
938 | <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; |
939 | interrupt-names = "uplow", "critical"; | |
940 | #thermal-sensor-cells = <1>; | |
941 | }; | |
942 | ||
97832fa8 | 943 | aoss_qmp: power-controller@c300000 { |
b7e8f433 | 944 | compatible = "qcom,sm8350-aoss-qmp"; |
47cb6a06 | 945 | reg = <0 0x0c300000 0 0x400>; |
b7e8f433 VK |
946 | interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP |
947 | IRQ_TYPE_EDGE_RISING>; | |
948 | mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
949 | ||
950 | #clock-cells = <0>; | |
b7e8f433 VK |
951 | }; |
952 | ||
47cb6a06 MS |
953 | sram@c3f0000 { |
954 | compatible = "qcom,rpmh-stats"; | |
955 | reg = <0 0x0c3f0000 0 0x400>; | |
956 | }; | |
957 | ||
389cd7ac VK |
958 | spmi_bus: spmi@c440000 { |
959 | compatible = "qcom,spmi-pmic-arb"; | |
960 | reg = <0x0 0xc440000 0x0 0x1100>, | |
961 | <0x0 0xc600000 0x0 0x2000000>, | |
962 | <0x0 0xe600000 0x0 0x100000>, | |
963 | <0x0 0xe700000 0x0 0xa0000>, | |
964 | <0x0 0xc40a000 0x0 0x26000>; | |
965 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
966 | interrupt-names = "periph_irq"; | |
967 | interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; | |
968 | qcom,ee = <0>; | |
969 | qcom,channel = <0>; | |
970 | #address-cells = <2>; | |
971 | #size-cells = <0>; | |
972 | interrupt-controller; | |
973 | #interrupt-cells = <4>; | |
974 | }; | |
975 | ||
b7e8f433 VK |
976 | tlmm: pinctrl@f100000 { |
977 | compatible = "qcom,sm8350-tlmm"; | |
978 | reg = <0 0x0f100000 0 0x300000>; | |
979 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
980 | gpio-controller; | |
981 | #gpio-cells = <2>; | |
982 | interrupt-controller; | |
983 | #interrupt-cells = <2>; | |
79015857 | 984 | gpio-ranges = <&tlmm 0 0 204>; |
67146f07 | 985 | wakeup-parent = <&pdc>; |
b7e8f433 VK |
986 | |
987 | qup_uart3_default_state: qup-uart3-default-state { | |
988 | rx { | |
989 | pins = "gpio18"; | |
990 | function = "qup3"; | |
991 | }; | |
992 | tx { | |
993 | pins = "gpio19"; | |
994 | function = "qup3"; | |
995 | }; | |
996 | }; | |
06bf656e JM |
997 | |
998 | qup_i2c13_default_state: qup-i2c13-default-state { | |
999 | mux { | |
1000 | pins = "gpio0", "gpio1"; | |
1001 | function = "qup13"; | |
1002 | }; | |
1003 | ||
1004 | config { | |
1005 | pins = "gpio0", "gpio1"; | |
1006 | drive-strength = <2>; | |
1007 | bias-pull-up; | |
1008 | }; | |
1009 | }; | |
b7e8f433 VK |
1010 | }; |
1011 | ||
24e3eb2e RF |
1012 | rng: rng@10d3000 { |
1013 | compatible = "qcom,prng-ee"; | |
1014 | reg = <0 0x010d3000 0 0x1000>; | |
1015 | clocks = <&rpmhcc RPMH_HWKM_CLK>; | |
1016 | clock-names = "core"; | |
1017 | }; | |
1018 | ||
b7e8f433 VK |
1019 | intc: interrupt-controller@17a00000 { |
1020 | compatible = "arm,gic-v3"; | |
1021 | #interrupt-cells = <3>; | |
1022 | interrupt-controller; | |
f4d4ca9f KD |
1023 | #redistributor-regions = <1>; |
1024 | redistributor-stride = <0 0x20000>; | |
b7e8f433 VK |
1025 | reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ |
1026 | <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ | |
1027 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
1028 | }; | |
1029 | ||
1030 | timer@17c20000 { | |
1031 | compatible = "arm,armv7-timer-mem"; | |
1032 | #address-cells = <2>; | |
1033 | #size-cells = <2>; | |
1034 | ranges; | |
1035 | reg = <0x0 0x17c20000 0x0 0x1000>; | |
1036 | clock-frequency = <19200000>; | |
1037 | ||
1038 | frame@17c21000 { | |
1039 | frame-number = <0>; | |
1040 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
1041 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
1042 | reg = <0x0 0x17c21000 0x0 0x1000>, | |
1043 | <0x0 0x17c22000 0x0 0x1000>; | |
1044 | }; | |
1045 | ||
1046 | frame@17c23000 { | |
1047 | frame-number = <1>; | |
1048 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
1049 | reg = <0x0 0x17c23000 0x0 0x1000>; | |
1050 | status = "disabled"; | |
1051 | }; | |
1052 | ||
1053 | frame@17c25000 { | |
1054 | frame-number = <2>; | |
1055 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
1056 | reg = <0x0 0x17c25000 0x0 0x1000>; | |
1057 | status = "disabled"; | |
1058 | }; | |
1059 | ||
1060 | frame@17c27000 { | |
1061 | frame-number = <3>; | |
1062 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
1063 | reg = <0x0 0x17c27000 0x0 0x1000>; | |
1064 | status = "disabled"; | |
1065 | }; | |
1066 | ||
1067 | frame@17c29000 { | |
1068 | frame-number = <4>; | |
1069 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
1070 | reg = <0x0 0x17c29000 0x0 0x1000>; | |
1071 | status = "disabled"; | |
1072 | }; | |
1073 | ||
1074 | frame@17c2b000 { | |
1075 | frame-number = <5>; | |
1076 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
1077 | reg = <0x0 0x17c2b000 0x0 0x1000>; | |
1078 | status = "disabled"; | |
1079 | }; | |
1080 | ||
1081 | frame@17c2d000 { | |
1082 | frame-number = <6>; | |
1083 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
1084 | reg = <0x0 0x17c2d000 0x0 0x1000>; | |
1085 | status = "disabled"; | |
1086 | }; | |
1087 | }; | |
1088 | ||
1089 | apps_rsc: rsc@18200000 { | |
1090 | label = "apps_rsc"; | |
1091 | compatible = "qcom,rpmh-rsc"; | |
1092 | reg = <0x0 0x18200000 0x0 0x10000>, | |
1093 | <0x0 0x18210000 0x0 0x10000>, | |
1094 | <0x0 0x18220000 0x0 0x10000>; | |
1095 | reg-names = "drv-0", "drv-1", "drv-2"; | |
1096 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
1097 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
1098 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
1099 | qcom,tcs-offset = <0xd00>; | |
1100 | qcom,drv-id = <2>; | |
1101 | qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, | |
1102 | <WAKE_TCS 3>, <CONTROL_TCS 1>; | |
1103 | ||
1104 | rpmhcc: clock-controller { | |
1105 | compatible = "qcom,sm8350-rpmh-clk"; | |
1106 | #clock-cells = <1>; | |
1107 | clock-names = "xo"; | |
1108 | clocks = <&xo_board>; | |
1109 | }; | |
1110 | ||
90f57509 VK |
1111 | rpmhpd: power-controller { |
1112 | compatible = "qcom,sm8350-rpmhpd"; | |
1113 | #power-domain-cells = <1>; | |
1114 | operating-points-v2 = <&rpmhpd_opp_table>; | |
1115 | ||
1116 | rpmhpd_opp_table: opp-table { | |
1117 | compatible = "operating-points-v2"; | |
1118 | ||
1119 | rpmhpd_opp_ret: opp1 { | |
1120 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; | |
1121 | }; | |
1122 | ||
1123 | rpmhpd_opp_min_svs: opp2 { | |
1124 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
1125 | }; | |
1126 | ||
1127 | rpmhpd_opp_low_svs: opp3 { | |
1128 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
1129 | }; | |
1130 | ||
1131 | rpmhpd_opp_svs: opp4 { | |
1132 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
1133 | }; | |
1134 | ||
1135 | rpmhpd_opp_svs_l1: opp5 { | |
1136 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
1137 | }; | |
1138 | ||
1139 | rpmhpd_opp_nom: opp6 { | |
1140 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
1141 | }; | |
1142 | ||
1143 | rpmhpd_opp_nom_l1: opp7 { | |
1144 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
1145 | }; | |
1146 | ||
1147 | rpmhpd_opp_nom_l2: opp8 { | |
1148 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; | |
1149 | }; | |
1150 | ||
1151 | rpmhpd_opp_turbo: opp9 { | |
1152 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
1153 | }; | |
1154 | ||
1155 | rpmhpd_opp_turbo_l1: opp10 { | |
1156 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
1157 | }; | |
1158 | }; | |
1159 | }; | |
da6b2482 VK |
1160 | |
1161 | apps_bcm_voter: bcm_voter { | |
1162 | compatible = "qcom,bcm-voter"; | |
1163 | }; | |
b7e8f433 | 1164 | }; |
e780fb31 | 1165 | |
ccbb3abb VK |
1166 | cpufreq_hw: cpufreq@18591000 { |
1167 | compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; | |
1168 | reg = <0 0x18591000 0 0x1000>, | |
1169 | <0 0x18592000 0 0x1000>, | |
1170 | <0 0x18593000 0 0x1000>; | |
1171 | reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; | |
1172 | ||
1173 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; | |
1174 | clock-names = "xo", "alternate"; | |
1175 | ||
1176 | #freq-domain-cells = <1>; | |
1177 | }; | |
1178 | ||
59c7cf81 VK |
1179 | ufs_mem_hc: ufshc@1d84000 { |
1180 | compatible = "qcom,sm8350-ufshc", "qcom,ufshc", | |
1181 | "jedec,ufs-2.0"; | |
1182 | reg = <0 0x01d84000 0 0x3000>; | |
1183 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
1184 | phys = <&ufs_mem_phy_lanes>; | |
1185 | phy-names = "ufsphy"; | |
1186 | lanes-per-direction = <2>; | |
1187 | #reset-cells = <1>; | |
6d91e201 | 1188 | resets = <&gcc GCC_UFS_PHY_BCR>; |
59c7cf81 VK |
1189 | reset-names = "rst"; |
1190 | ||
6d91e201 | 1191 | power-domains = <&gcc UFS_PHY_GDSC>; |
59c7cf81 VK |
1192 | |
1193 | iommus = <&apps_smmu 0xe0 0x0>; | |
1194 | ||
1195 | clock-names = | |
1196 | "ref_clk", | |
1197 | "core_clk", | |
1198 | "bus_aggr_clk", | |
1199 | "iface_clk", | |
1200 | "core_clk_unipro", | |
1201 | "ref_clk", | |
1202 | "tx_lane0_sync_clk", | |
1203 | "rx_lane0_sync_clk", | |
1204 | "rx_lane1_sync_clk"; | |
1205 | clocks = | |
1206 | <&rpmhcc RPMH_CXO_CLK>, | |
6d91e201 VK |
1207 | <&gcc GCC_UFS_PHY_AXI_CLK>, |
1208 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
1209 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
1210 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
59c7cf81 | 1211 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 VK |
1212 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
1213 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
1214 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
59c7cf81 VK |
1215 | freq-table-hz = |
1216 | <75000000 300000000>, | |
1217 | <75000000 300000000>, | |
1218 | <0 0>, | |
1219 | <0 0>, | |
1220 | <75000000 300000000>, | |
1221 | <0 0>, | |
1222 | <0 0>, | |
1223 | <75000000 300000000>, | |
1224 | <75000000 300000000>; | |
1225 | status = "disabled"; | |
1226 | }; | |
1227 | ||
1228 | ufs_mem_phy: phy@1d87000 { | |
1229 | compatible = "qcom,sm8350-qmp-ufs-phy"; | |
1230 | reg = <0 0x01d87000 0 0xe10>; | |
1231 | #address-cells = <2>; | |
1232 | #size-cells = <2>; | |
59c7cf81 VK |
1233 | ranges; |
1234 | clock-names = "ref", | |
1235 | "ref_aux"; | |
1236 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
6d91e201 | 1237 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
59c7cf81 VK |
1238 | |
1239 | resets = <&ufs_mem_hc 0>; | |
1240 | reset-names = "ufsphy"; | |
1241 | status = "disabled"; | |
1242 | ||
1351512f | 1243 | ufs_mem_phy_lanes: phy@1d87400 { |
59c7cf81 VK |
1244 | reg = <0 0x01d87400 0 0x108>, |
1245 | <0 0x01d87600 0 0x1e0>, | |
1246 | <0 0x01d87c00 0 0x1dc>, | |
1247 | <0 0x01d87800 0 0x108>, | |
1248 | <0 0x01d87a00 0 0x1e0>; | |
1249 | #phy-cells = <0>; | |
1250 | #clock-cells = <0>; | |
1251 | }; | |
1252 | }; | |
1253 | ||
177fcf0a VK |
1254 | slpi: remoteproc@5c00000 { |
1255 | compatible = "qcom,sm8350-slpi-pas"; | |
1256 | reg = <0 0x05c00000 0 0x4000>; | |
1257 | ||
1258 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, | |
1259 | <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, | |
1260 | <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, | |
1261 | <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, | |
1262 | <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; | |
1263 | interrupt-names = "wdog", "fatal", "ready", | |
1264 | "handover", "stop-ack"; | |
1265 | ||
1266 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1267 | clock-names = "xo"; | |
1268 | ||
6b7cb2d2 | 1269 | power-domains = <&rpmhpd 4>, |
177fcf0a | 1270 | <&rpmhpd 5>; |
6b7cb2d2 | 1271 | power-domain-names = "lcx", "lmx"; |
177fcf0a VK |
1272 | |
1273 | memory-region = <&pil_slpi_mem>; | |
1274 | ||
6b7cb2d2 SS |
1275 | qcom,qmp = <&aoss_qmp>; |
1276 | ||
177fcf0a VK |
1277 | qcom,smem-states = <&smp2p_slpi_out 0>; |
1278 | qcom,smem-state-names = "stop"; | |
1279 | ||
1280 | status = "disabled"; | |
1281 | ||
1282 | glink-edge { | |
1283 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
1284 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
1285 | IRQ_TYPE_EDGE_RISING>; | |
1286 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
1287 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
1288 | ||
1289 | label = "slpi"; | |
1290 | qcom,remote-pid = <3>; | |
1291 | ||
178056a4 OJ |
1292 | fastrpc { |
1293 | compatible = "qcom,fastrpc"; | |
1294 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
1295 | label = "sdsp"; | |
1296 | #address-cells = <1>; | |
1297 | #size-cells = <0>; | |
1298 | ||
1299 | compute-cb@1 { | |
1300 | compatible = "qcom,fastrpc-compute-cb"; | |
1301 | reg = <1>; | |
1302 | iommus = <&apps_smmu 0x0541 0x0>; | |
1303 | }; | |
1304 | ||
1305 | compute-cb@2 { | |
1306 | compatible = "qcom,fastrpc-compute-cb"; | |
1307 | reg = <2>; | |
1308 | iommus = <&apps_smmu 0x0542 0x0>; | |
1309 | }; | |
1310 | ||
1311 | compute-cb@3 { | |
1312 | compatible = "qcom,fastrpc-compute-cb"; | |
1313 | reg = <3>; | |
1314 | iommus = <&apps_smmu 0x0543 0x0>; | |
1315 | /* note: shared-cb = <4> in downstream */ | |
1316 | }; | |
1317 | }; | |
177fcf0a VK |
1318 | }; |
1319 | }; | |
1320 | ||
1321 | cdsp: remoteproc@98900000 { | |
1322 | compatible = "qcom,sm8350-cdsp-pas"; | |
1323 | reg = <0 0x098900000 0 0x1400000>; | |
1324 | ||
1325 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, | |
1326 | <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
1327 | <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
1328 | <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
1329 | <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
1330 | interrupt-names = "wdog", "fatal", "ready", | |
1331 | "handover", "stop-ack"; | |
1332 | ||
1333 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1334 | clock-names = "xo"; | |
1335 | ||
6b7cb2d2 | 1336 | power-domains = <&rpmhpd 0>, |
177fcf0a | 1337 | <&rpmhpd 10>; |
6b7cb2d2 | 1338 | power-domain-names = "cx", "mxc"; |
177fcf0a | 1339 | |
84c856d0 | 1340 | interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; |
da6b2482 | 1341 | |
177fcf0a VK |
1342 | memory-region = <&pil_cdsp_mem>; |
1343 | ||
6b7cb2d2 SS |
1344 | qcom,qmp = <&aoss_qmp>; |
1345 | ||
177fcf0a VK |
1346 | qcom,smem-states = <&smp2p_cdsp_out 0>; |
1347 | qcom,smem-state-names = "stop"; | |
1348 | ||
1349 | status = "disabled"; | |
1350 | ||
1351 | glink-edge { | |
1352 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
1353 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
1354 | IRQ_TYPE_EDGE_RISING>; | |
1355 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
1356 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
1357 | ||
1358 | label = "cdsp"; | |
1359 | qcom,remote-pid = <5>; | |
178056a4 OJ |
1360 | |
1361 | fastrpc { | |
1362 | compatible = "qcom,fastrpc"; | |
1363 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
1364 | label = "cdsp"; | |
1365 | #address-cells = <1>; | |
1366 | #size-cells = <0>; | |
1367 | ||
1368 | compute-cb@1 { | |
1369 | compatible = "qcom,fastrpc-compute-cb"; | |
1370 | reg = <1>; | |
1371 | iommus = <&apps_smmu 0x2161 0x0400>, | |
1372 | <&apps_smmu 0x1181 0x0420>; | |
1373 | }; | |
1374 | ||
1375 | compute-cb@2 { | |
1376 | compatible = "qcom,fastrpc-compute-cb"; | |
1377 | reg = <2>; | |
1378 | iommus = <&apps_smmu 0x2162 0x0400>, | |
1379 | <&apps_smmu 0x1182 0x0420>; | |
1380 | }; | |
1381 | ||
1382 | compute-cb@3 { | |
1383 | compatible = "qcom,fastrpc-compute-cb"; | |
1384 | reg = <3>; | |
1385 | iommus = <&apps_smmu 0x2163 0x0400>, | |
1386 | <&apps_smmu 0x1183 0x0420>; | |
1387 | }; | |
1388 | ||
1389 | compute-cb@4 { | |
1390 | compatible = "qcom,fastrpc-compute-cb"; | |
1391 | reg = <4>; | |
1392 | iommus = <&apps_smmu 0x2164 0x0400>, | |
1393 | <&apps_smmu 0x1184 0x0420>; | |
1394 | }; | |
1395 | ||
1396 | compute-cb@5 { | |
1397 | compatible = "qcom,fastrpc-compute-cb"; | |
1398 | reg = <5>; | |
1399 | iommus = <&apps_smmu 0x2165 0x0400>, | |
1400 | <&apps_smmu 0x1185 0x0420>; | |
1401 | }; | |
1402 | ||
1403 | compute-cb@6 { | |
1404 | compatible = "qcom,fastrpc-compute-cb"; | |
1405 | reg = <6>; | |
1406 | iommus = <&apps_smmu 0x2166 0x0400>, | |
1407 | <&apps_smmu 0x1186 0x0420>; | |
1408 | }; | |
1409 | ||
1410 | compute-cb@7 { | |
1411 | compatible = "qcom,fastrpc-compute-cb"; | |
1412 | reg = <7>; | |
1413 | iommus = <&apps_smmu 0x2167 0x0400>, | |
1414 | <&apps_smmu 0x1187 0x0420>; | |
1415 | }; | |
1416 | ||
1417 | compute-cb@8 { | |
1418 | compatible = "qcom,fastrpc-compute-cb"; | |
1419 | reg = <8>; | |
1420 | iommus = <&apps_smmu 0x2168 0x0400>, | |
1421 | <&apps_smmu 0x1188 0x0420>; | |
1422 | }; | |
1423 | ||
1424 | /* note: secure cb9 in downstream */ | |
1425 | }; | |
177fcf0a VK |
1426 | }; |
1427 | }; | |
1428 | ||
e780fb31 JP |
1429 | usb_1_hsphy: phy@88e3000 { |
1430 | compatible = "qcom,sm8350-usb-hs-phy", | |
1431 | "qcom,usb-snps-hs-7nm-phy"; | |
1432 | reg = <0 0x088e3000 0 0x400>; | |
1433 | status = "disabled"; | |
1434 | #phy-cells = <0>; | |
1435 | ||
1436 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1437 | clock-names = "ref"; | |
1438 | ||
6d91e201 | 1439 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
e780fb31 JP |
1440 | }; |
1441 | ||
1442 | usb_2_hsphy: phy@88e4000 { | |
1443 | compatible = "qcom,sm8250-usb-hs-phy", | |
1444 | "qcom,usb-snps-hs-7nm-phy"; | |
1445 | reg = <0 0x088e4000 0 0x400>; | |
1446 | status = "disabled"; | |
1447 | #phy-cells = <0>; | |
1448 | ||
1449 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1450 | clock-names = "ref"; | |
1451 | ||
6d91e201 | 1452 | resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
e780fb31 JP |
1453 | }; |
1454 | ||
1455 | usb_1_qmpphy: phy-wrapper@88e9000 { | |
1456 | compatible = "qcom,sm8350-qmp-usb3-phy"; | |
1457 | reg = <0 0x088e9000 0 0x200>, | |
1458 | <0 0x088e8000 0 0x20>; | |
e780fb31 | 1459 | status = "disabled"; |
e780fb31 JP |
1460 | #address-cells = <2>; |
1461 | #size-cells = <2>; | |
1462 | ranges; | |
1463 | ||
6d91e201 | 1464 | clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
e780fb31 | 1465 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 | 1466 | <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
e780fb31 JP |
1467 | clock-names = "aux", "ref_clk_src", "com_aux"; |
1468 | ||
6d91e201 VK |
1469 | resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
1470 | <&gcc GCC_USB3_PHY_PRIM_BCR>; | |
e780fb31 JP |
1471 | reset-names = "phy", "common"; |
1472 | ||
1473 | usb_1_ssphy: phy@88e9200 { | |
1474 | reg = <0 0x088e9200 0 0x200>, | |
1475 | <0 0x088e9400 0 0x200>, | |
1476 | <0 0x088e9c00 0 0x400>, | |
1477 | <0 0x088e9600 0 0x200>, | |
1478 | <0 0x088e9800 0 0x200>, | |
1479 | <0 0x088e9a00 0 0x100>; | |
1480 | #phy-cells = <0>; | |
1481 | #clock-cells = <1>; | |
6d91e201 | 1482 | clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
e780fb31 JP |
1483 | clock-names = "pipe0"; |
1484 | clock-output-names = "usb3_phy_pipe_clk_src"; | |
1485 | }; | |
1486 | }; | |
1487 | ||
1488 | usb_2_qmpphy: phy-wrapper@88eb000 { | |
1489 | compatible = "qcom,sm8350-qmp-usb3-uni-phy"; | |
1490 | reg = <0 0x088eb000 0 0x200>; | |
1491 | status = "disabled"; | |
e780fb31 JP |
1492 | #address-cells = <2>; |
1493 | #size-cells = <2>; | |
1494 | ranges; | |
1495 | ||
6d91e201 | 1496 | clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
e780fb31 | 1497 | <&rpmhcc RPMH_CXO_CLK>, |
6d91e201 VK |
1498 | <&gcc GCC_USB3_SEC_CLKREF_EN>, |
1499 | <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; | |
e780fb31 JP |
1500 | clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
1501 | ||
6d91e201 VK |
1502 | resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
1503 | <&gcc GCC_USB3_PHY_SEC_BCR>; | |
e780fb31 JP |
1504 | reset-names = "phy", "common"; |
1505 | ||
1506 | usb_2_ssphy: phy@88ebe00 { | |
1507 | reg = <0 0x088ebe00 0 0x200>, | |
1508 | <0 0x088ec000 0 0x200>, | |
1509 | <0 0x088eb200 0 0x1100>; | |
1510 | #phy-cells = <0>; | |
1511 | #clock-cells = <1>; | |
6d91e201 | 1512 | clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
e780fb31 JP |
1513 | clock-names = "pipe0"; |
1514 | clock-output-names = "usb3_uni_phy_pipe_clk_src"; | |
1515 | }; | |
1516 | }; | |
1517 | ||
1dee9e3b | 1518 | dc_noc: interconnect@90c0000 { |
da6b2482 VK |
1519 | compatible = "qcom,sm8350-dc-noc"; |
1520 | reg = <0 0x090c0000 0 0x4200>; | |
1521 | #interconnect-cells = <1>; | |
1522 | qcom,bcm-voters = <&apps_bcm_voter>; | |
1523 | }; | |
1524 | ||
1525 | gem_noc: interconnect@9100000 { | |
1526 | compatible = "qcom,sm8350-gem-noc"; | |
1527 | reg = <0 0x09100000 0 0xb4000>; | |
1528 | #interconnect-cells = <1>; | |
1529 | qcom,bcm-voters = <&apps_bcm_voter>; | |
1530 | }; | |
1531 | ||
e780fb31 JP |
1532 | usb_1: usb@a6f8800 { |
1533 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
1534 | reg = <0 0x0a6f8800 0 0x400>; | |
1535 | status = "disabled"; | |
1536 | #address-cells = <2>; | |
1537 | #size-cells = <2>; | |
1538 | ranges; | |
1539 | ||
6d91e201 VK |
1540 | clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
1541 | <&gcc GCC_USB30_PRIM_MASTER_CLK>, | |
1542 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, | |
1543 | <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, | |
1544 | <&gcc GCC_USB30_PRIM_SLEEP_CLK>; | |
e780fb31 JP |
1545 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
1546 | "sleep"; | |
1547 | ||
6d91e201 VK |
1548 | assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
1549 | <&gcc GCC_USB30_PRIM_MASTER_CLK>; | |
e780fb31 JP |
1550 | assigned-clock-rates = <19200000>, <200000000>; |
1551 | ||
1552 | interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
1553 | <&pdc 14 IRQ_TYPE_EDGE_BOTH>, | |
1554 | <&pdc 15 IRQ_TYPE_EDGE_BOTH>, | |
1555 | <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; | |
1556 | interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", | |
1557 | "dm_hs_phy_irq", "ss_phy_irq"; | |
1558 | ||
6d91e201 | 1559 | power-domains = <&gcc USB30_PRIM_GDSC>; |
e780fb31 | 1560 | |
6d91e201 | 1561 | resets = <&gcc GCC_USB30_PRIM_BCR>; |
e780fb31 | 1562 | |
2aa2b50d | 1563 | usb_1_dwc3: usb@a600000 { |
e780fb31 JP |
1564 | compatible = "snps,dwc3"; |
1565 | reg = <0 0x0a600000 0 0xcd00>; | |
1566 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
1567 | iommus = <&apps_smmu 0x0 0x0>; | |
1568 | snps,dis_u2_susphy_quirk; | |
1569 | snps,dis_enblslpm_quirk; | |
1570 | phys = <&usb_1_hsphy>, <&usb_1_ssphy>; | |
1571 | phy-names = "usb2-phy", "usb3-phy"; | |
1572 | }; | |
1573 | }; | |
1574 | ||
1575 | usb_2: usb@a8f8800 { | |
1576 | compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; | |
1577 | reg = <0 0x0a8f8800 0 0x400>; | |
1578 | status = "disabled"; | |
1579 | #address-cells = <2>; | |
1580 | #size-cells = <2>; | |
1581 | ranges; | |
1582 | ||
6d91e201 VK |
1583 | clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
1584 | <&gcc GCC_USB30_SEC_MASTER_CLK>, | |
1585 | <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, | |
1586 | <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, | |
1587 | <&gcc GCC_USB30_SEC_SLEEP_CLK>, | |
1588 | <&gcc GCC_USB3_SEC_CLKREF_EN>; | |
e780fb31 JP |
1589 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
1590 | "sleep", "xo"; | |
1591 | ||
6d91e201 VK |
1592 | assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
1593 | <&gcc GCC_USB30_SEC_MASTER_CLK>; | |
e780fb31 JP |
1594 | assigned-clock-rates = <19200000>, <200000000>; |
1595 | ||
1596 | interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
1597 | <&pdc 12 IRQ_TYPE_EDGE_BOTH>, | |
1598 | <&pdc 13 IRQ_TYPE_EDGE_BOTH>, | |
1599 | <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; | |
1600 | interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", | |
1601 | "dm_hs_phy_irq", "ss_phy_irq"; | |
1602 | ||
6d91e201 | 1603 | power-domains = <&gcc USB30_SEC_GDSC>; |
e780fb31 | 1604 | |
6d91e201 | 1605 | resets = <&gcc GCC_USB30_SEC_BCR>; |
e780fb31 | 1606 | |
2aa2b50d | 1607 | usb_2_dwc3: usb@a800000 { |
e780fb31 JP |
1608 | compatible = "snps,dwc3"; |
1609 | reg = <0 0x0a800000 0 0xcd00>; | |
1610 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
1611 | iommus = <&apps_smmu 0x20 0x0>; | |
1612 | snps,dis_u2_susphy_quirk; | |
1613 | snps,dis_enblslpm_quirk; | |
1614 | phys = <&usb_2_hsphy>, <&usb_2_ssphy>; | |
1615 | phy-names = "usb2-phy", "usb3-phy"; | |
1616 | }; | |
1617 | }; | |
177fcf0a VK |
1618 | |
1619 | adsp: remoteproc@17300000 { | |
1620 | compatible = "qcom,sm8350-adsp-pas"; | |
1621 | reg = <0 0x17300000 0 0x100>; | |
1622 | ||
1623 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, | |
1624 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
1625 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
1626 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
1627 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
1628 | interrupt-names = "wdog", "fatal", "ready", | |
1629 | "handover", "stop-ack"; | |
1630 | ||
1631 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1632 | clock-names = "xo"; | |
1633 | ||
6b7cb2d2 | 1634 | power-domains = <&rpmhpd 4>, |
177fcf0a | 1635 | <&rpmhpd 5>; |
6b7cb2d2 | 1636 | power-domain-names = "lcx", "lmx"; |
177fcf0a VK |
1637 | |
1638 | memory-region = <&pil_adsp_mem>; | |
1639 | ||
6b7cb2d2 SS |
1640 | qcom,qmp = <&aoss_qmp>; |
1641 | ||
177fcf0a VK |
1642 | qcom,smem-states = <&smp2p_adsp_out 0>; |
1643 | qcom,smem-state-names = "stop"; | |
1644 | ||
1645 | status = "disabled"; | |
1646 | ||
1647 | glink-edge { | |
1648 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
1649 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
1650 | IRQ_TYPE_EDGE_RISING>; | |
1651 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
1652 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
1653 | ||
1654 | label = "lpass"; | |
1655 | qcom,remote-pid = <2>; | |
178056a4 OJ |
1656 | |
1657 | fastrpc { | |
1658 | compatible = "qcom,fastrpc"; | |
1659 | qcom,glink-channels = "fastrpcglink-apps-dsp"; | |
1660 | label = "adsp"; | |
1661 | #address-cells = <1>; | |
1662 | #size-cells = <0>; | |
1663 | ||
1664 | compute-cb@3 { | |
1665 | compatible = "qcom,fastrpc-compute-cb"; | |
1666 | reg = <3>; | |
1667 | iommus = <&apps_smmu 0x1803 0x0>; | |
1668 | }; | |
1669 | ||
1670 | compute-cb@4 { | |
1671 | compatible = "qcom,fastrpc-compute-cb"; | |
1672 | reg = <4>; | |
1673 | iommus = <&apps_smmu 0x1804 0x0>; | |
1674 | }; | |
1675 | ||
1676 | compute-cb@5 { | |
1677 | compatible = "qcom,fastrpc-compute-cb"; | |
1678 | reg = <5>; | |
1679 | iommus = <&apps_smmu 0x1805 0x0>; | |
1680 | }; | |
1681 | }; | |
177fcf0a VK |
1682 | }; |
1683 | }; | |
b7e8f433 VK |
1684 | }; |
1685 | ||
4dcaa68e | 1686 | thermal_zones: thermal-zones { |
20f9d94e RF |
1687 | cpu0-thermal { |
1688 | polling-delay-passive = <250>; | |
1689 | polling-delay = <1000>; | |
1690 | ||
1691 | thermal-sensors = <&tsens0 1>; | |
1692 | ||
1693 | trips { | |
1694 | cpu0_alert0: trip-point0 { | |
1695 | temperature = <90000>; | |
1696 | hysteresis = <2000>; | |
1697 | type = "passive"; | |
1698 | }; | |
1699 | ||
1700 | cpu0_alert1: trip-point1 { | |
1701 | temperature = <95000>; | |
1702 | hysteresis = <2000>; | |
1703 | type = "passive"; | |
1704 | }; | |
1705 | ||
1706 | cpu0_crit: cpu_crit { | |
1707 | temperature = <110000>; | |
1708 | hysteresis = <1000>; | |
1709 | type = "critical"; | |
1710 | }; | |
1711 | }; | |
1712 | ||
1713 | cooling-maps { | |
1714 | map0 { | |
1715 | trip = <&cpu0_alert0>; | |
1716 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1717 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1718 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1719 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1720 | }; | |
1721 | map1 { | |
1722 | trip = <&cpu0_alert1>; | |
1723 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1724 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1725 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1726 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1727 | }; | |
1728 | }; | |
1729 | }; | |
1730 | ||
1731 | cpu1-thermal { | |
1732 | polling-delay-passive = <250>; | |
1733 | polling-delay = <1000>; | |
1734 | ||
1735 | thermal-sensors = <&tsens0 2>; | |
1736 | ||
1737 | trips { | |
1738 | cpu1_alert0: trip-point0 { | |
1739 | temperature = <90000>; | |
1740 | hysteresis = <2000>; | |
1741 | type = "passive"; | |
1742 | }; | |
1743 | ||
1744 | cpu1_alert1: trip-point1 { | |
1745 | temperature = <95000>; | |
1746 | hysteresis = <2000>; | |
1747 | type = "passive"; | |
1748 | }; | |
1749 | ||
1750 | cpu1_crit: cpu_crit { | |
1751 | temperature = <110000>; | |
1752 | hysteresis = <1000>; | |
1753 | type = "critical"; | |
1754 | }; | |
1755 | }; | |
1756 | ||
1757 | cooling-maps { | |
1758 | map0 { | |
1759 | trip = <&cpu1_alert0>; | |
1760 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1761 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1762 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1763 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1764 | }; | |
1765 | map1 { | |
1766 | trip = <&cpu1_alert1>; | |
1767 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1768 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1769 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1770 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1771 | }; | |
1772 | }; | |
1773 | }; | |
1774 | ||
1775 | cpu2-thermal { | |
1776 | polling-delay-passive = <250>; | |
1777 | polling-delay = <1000>; | |
1778 | ||
1779 | thermal-sensors = <&tsens0 3>; | |
1780 | ||
1781 | trips { | |
1782 | cpu2_alert0: trip-point0 { | |
1783 | temperature = <90000>; | |
1784 | hysteresis = <2000>; | |
1785 | type = "passive"; | |
1786 | }; | |
1787 | ||
1788 | cpu2_alert1: trip-point1 { | |
1789 | temperature = <95000>; | |
1790 | hysteresis = <2000>; | |
1791 | type = "passive"; | |
1792 | }; | |
1793 | ||
1794 | cpu2_crit: cpu_crit { | |
1795 | temperature = <110000>; | |
1796 | hysteresis = <1000>; | |
1797 | type = "critical"; | |
1798 | }; | |
1799 | }; | |
1800 | ||
1801 | cooling-maps { | |
1802 | map0 { | |
1803 | trip = <&cpu2_alert0>; | |
1804 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1805 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1806 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1807 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1808 | }; | |
1809 | map1 { | |
1810 | trip = <&cpu2_alert1>; | |
1811 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1812 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1813 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1814 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1815 | }; | |
1816 | }; | |
1817 | }; | |
1818 | ||
1819 | cpu3-thermal { | |
1820 | polling-delay-passive = <250>; | |
1821 | polling-delay = <1000>; | |
1822 | ||
1823 | thermal-sensors = <&tsens0 4>; | |
1824 | ||
1825 | trips { | |
1826 | cpu3_alert0: trip-point0 { | |
1827 | temperature = <90000>; | |
1828 | hysteresis = <2000>; | |
1829 | type = "passive"; | |
1830 | }; | |
1831 | ||
1832 | cpu3_alert1: trip-point1 { | |
1833 | temperature = <95000>; | |
1834 | hysteresis = <2000>; | |
1835 | type = "passive"; | |
1836 | }; | |
1837 | ||
1838 | cpu3_crit: cpu_crit { | |
1839 | temperature = <110000>; | |
1840 | hysteresis = <1000>; | |
1841 | type = "critical"; | |
1842 | }; | |
1843 | }; | |
1844 | ||
1845 | cooling-maps { | |
1846 | map0 { | |
1847 | trip = <&cpu3_alert0>; | |
1848 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1849 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1850 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1851 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1852 | }; | |
1853 | map1 { | |
1854 | trip = <&cpu3_alert1>; | |
1855 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1856 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1857 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1858 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1859 | }; | |
1860 | }; | |
1861 | }; | |
1862 | ||
1863 | cpu4-top-thermal { | |
1864 | polling-delay-passive = <250>; | |
1865 | polling-delay = <1000>; | |
1866 | ||
1867 | thermal-sensors = <&tsens0 7>; | |
1868 | ||
1869 | trips { | |
1870 | cpu4_top_alert0: trip-point0 { | |
1871 | temperature = <90000>; | |
1872 | hysteresis = <2000>; | |
1873 | type = "passive"; | |
1874 | }; | |
1875 | ||
1876 | cpu4_top_alert1: trip-point1 { | |
1877 | temperature = <95000>; | |
1878 | hysteresis = <2000>; | |
1879 | type = "passive"; | |
1880 | }; | |
1881 | ||
1882 | cpu4_top_crit: cpu_crit { | |
1883 | temperature = <110000>; | |
1884 | hysteresis = <1000>; | |
1885 | type = "critical"; | |
1886 | }; | |
1887 | }; | |
1888 | ||
1889 | cooling-maps { | |
1890 | map0 { | |
1891 | trip = <&cpu4_top_alert0>; | |
1892 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1893 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1894 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1895 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1896 | }; | |
1897 | map1 { | |
1898 | trip = <&cpu4_top_alert1>; | |
1899 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1900 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1901 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1902 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1903 | }; | |
1904 | }; | |
1905 | }; | |
1906 | ||
1907 | cpu5-top-thermal { | |
1908 | polling-delay-passive = <250>; | |
1909 | polling-delay = <1000>; | |
1910 | ||
1911 | thermal-sensors = <&tsens0 8>; | |
1912 | ||
1913 | trips { | |
1914 | cpu5_top_alert0: trip-point0 { | |
1915 | temperature = <90000>; | |
1916 | hysteresis = <2000>; | |
1917 | type = "passive"; | |
1918 | }; | |
1919 | ||
1920 | cpu5_top_alert1: trip-point1 { | |
1921 | temperature = <95000>; | |
1922 | hysteresis = <2000>; | |
1923 | type = "passive"; | |
1924 | }; | |
1925 | ||
1926 | cpu5_top_crit: cpu_crit { | |
1927 | temperature = <110000>; | |
1928 | hysteresis = <1000>; | |
1929 | type = "critical"; | |
1930 | }; | |
1931 | }; | |
1932 | ||
1933 | cooling-maps { | |
1934 | map0 { | |
1935 | trip = <&cpu5_top_alert0>; | |
1936 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1937 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1938 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1939 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1940 | }; | |
1941 | map1 { | |
1942 | trip = <&cpu5_top_alert1>; | |
1943 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1944 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1945 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1946 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1947 | }; | |
1948 | }; | |
1949 | }; | |
1950 | ||
1951 | cpu6-top-thermal { | |
1952 | polling-delay-passive = <250>; | |
1953 | polling-delay = <1000>; | |
1954 | ||
1955 | thermal-sensors = <&tsens0 9>; | |
1956 | ||
1957 | trips { | |
1958 | cpu6_top_alert0: trip-point0 { | |
1959 | temperature = <90000>; | |
1960 | hysteresis = <2000>; | |
1961 | type = "passive"; | |
1962 | }; | |
1963 | ||
1964 | cpu6_top_alert1: trip-point1 { | |
1965 | temperature = <95000>; | |
1966 | hysteresis = <2000>; | |
1967 | type = "passive"; | |
1968 | }; | |
1969 | ||
1970 | cpu6_top_crit: cpu_crit { | |
1971 | temperature = <110000>; | |
1972 | hysteresis = <1000>; | |
1973 | type = "critical"; | |
1974 | }; | |
1975 | }; | |
1976 | ||
1977 | cooling-maps { | |
1978 | map0 { | |
1979 | trip = <&cpu6_top_alert0>; | |
1980 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1981 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1982 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1983 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1984 | }; | |
1985 | map1 { | |
1986 | trip = <&cpu6_top_alert1>; | |
1987 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1988 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1989 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
1990 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
1991 | }; | |
1992 | }; | |
1993 | }; | |
1994 | ||
1995 | cpu7-top-thermal { | |
1996 | polling-delay-passive = <250>; | |
1997 | polling-delay = <1000>; | |
1998 | ||
1999 | thermal-sensors = <&tsens0 10>; | |
2000 | ||
2001 | trips { | |
2002 | cpu7_top_alert0: trip-point0 { | |
2003 | temperature = <90000>; | |
2004 | hysteresis = <2000>; | |
2005 | type = "passive"; | |
2006 | }; | |
2007 | ||
2008 | cpu7_top_alert1: trip-point1 { | |
2009 | temperature = <95000>; | |
2010 | hysteresis = <2000>; | |
2011 | type = "passive"; | |
2012 | }; | |
2013 | ||
2014 | cpu7_top_crit: cpu_crit { | |
2015 | temperature = <110000>; | |
2016 | hysteresis = <1000>; | |
2017 | type = "critical"; | |
2018 | }; | |
2019 | }; | |
2020 | ||
2021 | cooling-maps { | |
2022 | map0 { | |
2023 | trip = <&cpu7_top_alert0>; | |
2024 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2025 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2026 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2027 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2028 | }; | |
2029 | map1 { | |
2030 | trip = <&cpu7_top_alert1>; | |
2031 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2032 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2033 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2034 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2035 | }; | |
2036 | }; | |
2037 | }; | |
2038 | ||
2039 | cpu4-bottom-thermal { | |
2040 | polling-delay-passive = <250>; | |
2041 | polling-delay = <1000>; | |
2042 | ||
2043 | thermal-sensors = <&tsens0 11>; | |
2044 | ||
2045 | trips { | |
2046 | cpu4_bottom_alert0: trip-point0 { | |
2047 | temperature = <90000>; | |
2048 | hysteresis = <2000>; | |
2049 | type = "passive"; | |
2050 | }; | |
2051 | ||
2052 | cpu4_bottom_alert1: trip-point1 { | |
2053 | temperature = <95000>; | |
2054 | hysteresis = <2000>; | |
2055 | type = "passive"; | |
2056 | }; | |
2057 | ||
2058 | cpu4_bottom_crit: cpu_crit { | |
2059 | temperature = <110000>; | |
2060 | hysteresis = <1000>; | |
2061 | type = "critical"; | |
2062 | }; | |
2063 | }; | |
2064 | ||
2065 | cooling-maps { | |
2066 | map0 { | |
2067 | trip = <&cpu4_bottom_alert0>; | |
2068 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2069 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2070 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2071 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2072 | }; | |
2073 | map1 { | |
2074 | trip = <&cpu4_bottom_alert1>; | |
2075 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2076 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2077 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2078 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2079 | }; | |
2080 | }; | |
2081 | }; | |
2082 | ||
2083 | cpu5-bottom-thermal { | |
2084 | polling-delay-passive = <250>; | |
2085 | polling-delay = <1000>; | |
2086 | ||
2087 | thermal-sensors = <&tsens0 12>; | |
2088 | ||
2089 | trips { | |
2090 | cpu5_bottom_alert0: trip-point0 { | |
2091 | temperature = <90000>; | |
2092 | hysteresis = <2000>; | |
2093 | type = "passive"; | |
2094 | }; | |
2095 | ||
2096 | cpu5_bottom_alert1: trip-point1 { | |
2097 | temperature = <95000>; | |
2098 | hysteresis = <2000>; | |
2099 | type = "passive"; | |
2100 | }; | |
2101 | ||
2102 | cpu5_bottom_crit: cpu_crit { | |
2103 | temperature = <110000>; | |
2104 | hysteresis = <1000>; | |
2105 | type = "critical"; | |
2106 | }; | |
2107 | }; | |
2108 | ||
2109 | cooling-maps { | |
2110 | map0 { | |
2111 | trip = <&cpu5_bottom_alert0>; | |
2112 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2113 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2114 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2115 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2116 | }; | |
2117 | map1 { | |
2118 | trip = <&cpu5_bottom_alert1>; | |
2119 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2120 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2121 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2122 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2123 | }; | |
2124 | }; | |
2125 | }; | |
2126 | ||
2127 | cpu6-bottom-thermal { | |
2128 | polling-delay-passive = <250>; | |
2129 | polling-delay = <1000>; | |
2130 | ||
2131 | thermal-sensors = <&tsens0 13>; | |
2132 | ||
2133 | trips { | |
2134 | cpu6_bottom_alert0: trip-point0 { | |
2135 | temperature = <90000>; | |
2136 | hysteresis = <2000>; | |
2137 | type = "passive"; | |
2138 | }; | |
2139 | ||
2140 | cpu6_bottom_alert1: trip-point1 { | |
2141 | temperature = <95000>; | |
2142 | hysteresis = <2000>; | |
2143 | type = "passive"; | |
2144 | }; | |
2145 | ||
2146 | cpu6_bottom_crit: cpu_crit { | |
2147 | temperature = <110000>; | |
2148 | hysteresis = <1000>; | |
2149 | type = "critical"; | |
2150 | }; | |
2151 | }; | |
2152 | ||
2153 | cooling-maps { | |
2154 | map0 { | |
2155 | trip = <&cpu6_bottom_alert0>; | |
2156 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2157 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2158 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2159 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2160 | }; | |
2161 | map1 { | |
2162 | trip = <&cpu6_bottom_alert1>; | |
2163 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2164 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2165 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2166 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2167 | }; | |
2168 | }; | |
2169 | }; | |
2170 | ||
2171 | cpu7-bottom-thermal { | |
2172 | polling-delay-passive = <250>; | |
2173 | polling-delay = <1000>; | |
2174 | ||
2175 | thermal-sensors = <&tsens0 14>; | |
2176 | ||
2177 | trips { | |
2178 | cpu7_bottom_alert0: trip-point0 { | |
2179 | temperature = <90000>; | |
2180 | hysteresis = <2000>; | |
2181 | type = "passive"; | |
2182 | }; | |
2183 | ||
2184 | cpu7_bottom_alert1: trip-point1 { | |
2185 | temperature = <95000>; | |
2186 | hysteresis = <2000>; | |
2187 | type = "passive"; | |
2188 | }; | |
2189 | ||
2190 | cpu7_bottom_crit: cpu_crit { | |
2191 | temperature = <110000>; | |
2192 | hysteresis = <1000>; | |
2193 | type = "critical"; | |
2194 | }; | |
2195 | }; | |
2196 | ||
2197 | cooling-maps { | |
2198 | map0 { | |
2199 | trip = <&cpu7_bottom_alert0>; | |
2200 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2201 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2202 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2203 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2204 | }; | |
2205 | map1 { | |
2206 | trip = <&cpu7_bottom_alert1>; | |
2207 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2208 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2209 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2210 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2211 | }; | |
2212 | }; | |
2213 | }; | |
2214 | ||
2215 | aoss0-thermal { | |
2216 | polling-delay-passive = <250>; | |
2217 | polling-delay = <1000>; | |
2218 | ||
2219 | thermal-sensors = <&tsens0 0>; | |
2220 | ||
2221 | trips { | |
2222 | aoss0_alert0: trip-point0 { | |
2223 | temperature = <90000>; | |
2224 | hysteresis = <2000>; | |
2225 | type = "hot"; | |
2226 | }; | |
2227 | }; | |
2228 | }; | |
2229 | ||
2230 | cluster0-thermal { | |
2231 | polling-delay-passive = <250>; | |
2232 | polling-delay = <1000>; | |
2233 | ||
2234 | thermal-sensors = <&tsens0 5>; | |
2235 | ||
2236 | trips { | |
2237 | cluster0_alert0: trip-point0 { | |
2238 | temperature = <90000>; | |
2239 | hysteresis = <2000>; | |
2240 | type = "hot"; | |
2241 | }; | |
2242 | cluster0_crit: cluster0_crit { | |
2243 | temperature = <110000>; | |
2244 | hysteresis = <2000>; | |
2245 | type = "critical"; | |
2246 | }; | |
2247 | }; | |
2248 | }; | |
2249 | ||
2250 | cluster1-thermal { | |
2251 | polling-delay-passive = <250>; | |
2252 | polling-delay = <1000>; | |
2253 | ||
2254 | thermal-sensors = <&tsens0 6>; | |
2255 | ||
2256 | trips { | |
2257 | cluster1_alert0: trip-point0 { | |
2258 | temperature = <90000>; | |
2259 | hysteresis = <2000>; | |
2260 | type = "hot"; | |
2261 | }; | |
2262 | cluster1_crit: cluster1_crit { | |
2263 | temperature = <110000>; | |
2264 | hysteresis = <2000>; | |
2265 | type = "critical"; | |
2266 | }; | |
2267 | }; | |
2268 | }; | |
2269 | ||
2270 | aoss1-thermal { | |
2271 | polling-delay-passive = <250>; | |
2272 | polling-delay = <1000>; | |
2273 | ||
2274 | thermal-sensors = <&tsens1 0>; | |
2275 | ||
2276 | trips { | |
2277 | aoss1_alert0: trip-point0 { | |
2278 | temperature = <90000>; | |
2279 | hysteresis = <2000>; | |
2280 | type = "hot"; | |
2281 | }; | |
2282 | }; | |
2283 | }; | |
2284 | ||
2285 | gpu-thermal-top { | |
2286 | polling-delay-passive = <250>; | |
2287 | polling-delay = <1000>; | |
2288 | ||
2289 | thermal-sensors = <&tsens1 1>; | |
2290 | ||
2291 | trips { | |
2292 | gpu1_alert0: trip-point0 { | |
2293 | temperature = <90000>; | |
2294 | hysteresis = <1000>; | |
2295 | type = "hot"; | |
2296 | }; | |
2297 | }; | |
2298 | }; | |
2299 | ||
2300 | gpu-thermal-bottom { | |
2301 | polling-delay-passive = <250>; | |
2302 | polling-delay = <1000>; | |
2303 | ||
2304 | thermal-sensors = <&tsens1 2>; | |
2305 | ||
2306 | trips { | |
2307 | gpu2_alert0: trip-point0 { | |
2308 | temperature = <90000>; | |
2309 | hysteresis = <1000>; | |
2310 | type = "hot"; | |
2311 | }; | |
2312 | }; | |
2313 | }; | |
2314 | ||
2315 | nspss1-thermal { | |
2316 | polling-delay-passive = <250>; | |
2317 | polling-delay = <1000>; | |
2318 | ||
2319 | thermal-sensors = <&tsens1 3>; | |
2320 | ||
2321 | trips { | |
2322 | nspss1_alert0: trip-point0 { | |
2323 | temperature = <90000>; | |
2324 | hysteresis = <1000>; | |
2325 | type = "hot"; | |
2326 | }; | |
2327 | }; | |
2328 | }; | |
2329 | ||
2330 | nspss2-thermal { | |
2331 | polling-delay-passive = <250>; | |
2332 | polling-delay = <1000>; | |
2333 | ||
2334 | thermal-sensors = <&tsens1 4>; | |
2335 | ||
2336 | trips { | |
2337 | nspss2_alert0: trip-point0 { | |
2338 | temperature = <90000>; | |
2339 | hysteresis = <1000>; | |
2340 | type = "hot"; | |
2341 | }; | |
2342 | }; | |
2343 | }; | |
2344 | ||
2345 | nspss3-thermal { | |
2346 | polling-delay-passive = <250>; | |
2347 | polling-delay = <1000>; | |
2348 | ||
2349 | thermal-sensors = <&tsens1 5>; | |
2350 | ||
2351 | trips { | |
2352 | nspss3_alert0: trip-point0 { | |
2353 | temperature = <90000>; | |
2354 | hysteresis = <1000>; | |
2355 | type = "hot"; | |
2356 | }; | |
2357 | }; | |
2358 | }; | |
2359 | ||
2360 | video-thermal { | |
2361 | polling-delay-passive = <250>; | |
2362 | polling-delay = <1000>; | |
2363 | ||
2364 | thermal-sensors = <&tsens1 6>; | |
2365 | ||
2366 | trips { | |
2367 | video_alert0: trip-point0 { | |
2368 | temperature = <90000>; | |
2369 | hysteresis = <2000>; | |
2370 | type = "hot"; | |
2371 | }; | |
2372 | }; | |
2373 | }; | |
2374 | ||
2375 | mem-thermal { | |
2376 | polling-delay-passive = <250>; | |
2377 | polling-delay = <1000>; | |
2378 | ||
2379 | thermal-sensors = <&tsens1 7>; | |
2380 | ||
2381 | trips { | |
2382 | mem_alert0: trip-point0 { | |
2383 | temperature = <90000>; | |
2384 | hysteresis = <2000>; | |
2385 | type = "hot"; | |
2386 | }; | |
2387 | }; | |
2388 | }; | |
2389 | ||
2390 | modem1-thermal-top { | |
2391 | polling-delay-passive = <250>; | |
2392 | polling-delay = <1000>; | |
2393 | ||
2394 | thermal-sensors = <&tsens1 8>; | |
2395 | ||
2396 | trips { | |
2397 | modem1_alert0: trip-point0 { | |
2398 | temperature = <90000>; | |
2399 | hysteresis = <2000>; | |
2400 | type = "hot"; | |
2401 | }; | |
2402 | }; | |
2403 | }; | |
2404 | ||
2405 | modem2-thermal-top { | |
2406 | polling-delay-passive = <250>; | |
2407 | polling-delay = <1000>; | |
2408 | ||
2409 | thermal-sensors = <&tsens1 9>; | |
2410 | ||
2411 | trips { | |
2412 | modem2_alert0: trip-point0 { | |
2413 | temperature = <90000>; | |
2414 | hysteresis = <2000>; | |
2415 | type = "hot"; | |
2416 | }; | |
2417 | }; | |
2418 | }; | |
2419 | ||
2420 | modem3-thermal-top { | |
2421 | polling-delay-passive = <250>; | |
2422 | polling-delay = <1000>; | |
2423 | ||
2424 | thermal-sensors = <&tsens1 10>; | |
2425 | ||
2426 | trips { | |
2427 | modem3_alert0: trip-point0 { | |
2428 | temperature = <90000>; | |
2429 | hysteresis = <2000>; | |
2430 | type = "hot"; | |
2431 | }; | |
2432 | }; | |
2433 | }; | |
2434 | ||
2435 | modem4-thermal-top { | |
2436 | polling-delay-passive = <250>; | |
2437 | polling-delay = <1000>; | |
2438 | ||
2439 | thermal-sensors = <&tsens1 11>; | |
2440 | ||
2441 | trips { | |
2442 | modem4_alert0: trip-point0 { | |
2443 | temperature = <90000>; | |
2444 | hysteresis = <2000>; | |
2445 | type = "hot"; | |
2446 | }; | |
2447 | }; | |
2448 | }; | |
2449 | ||
2450 | camera-thermal-top { | |
2451 | polling-delay-passive = <250>; | |
2452 | polling-delay = <1000>; | |
2453 | ||
2454 | thermal-sensors = <&tsens1 12>; | |
2455 | ||
2456 | trips { | |
2457 | camera1_alert0: trip-point0 { | |
2458 | temperature = <90000>; | |
2459 | hysteresis = <2000>; | |
2460 | type = "hot"; | |
2461 | }; | |
2462 | }; | |
2463 | }; | |
2464 | ||
f52dd339 | 2465 | cam-thermal-bottom { |
20f9d94e RF |
2466 | polling-delay-passive = <250>; |
2467 | polling-delay = <1000>; | |
2468 | ||
2469 | thermal-sensors = <&tsens1 13>; | |
2470 | ||
2471 | trips { | |
2472 | camera2_alert0: trip-point0 { | |
2473 | temperature = <90000>; | |
2474 | hysteresis = <2000>; | |
2475 | type = "hot"; | |
2476 | }; | |
2477 | }; | |
2478 | }; | |
2479 | }; | |
2480 | ||
b7e8f433 VK |
2481 | timer { |
2482 | compatible = "arm,armv8-timer"; | |
2483 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
2484 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
2485 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
2486 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
ed9500c1 | 2487 | clock-frequency = <19200000>; |
b7e8f433 VK |
2488 | }; |
2489 | }; |