[people/ms/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig

config ARCH_LS1012A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR_BE
	select SYS_FSL_MMDC
	select SYS_FSL_ERRATUM_A010315
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config ARCH_LS1043A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A008850
	select SYS_FSL_ERRATUM_A009660
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009929
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010315
	select SYS_FSL_ERRATUM_A010539
	select SYS_FSL_HAS_DDR3
	select SYS_FSL_HAS_DDR4
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config ARCH_LS1046A
	bool
	select ARMV8_SET_SMPEN
	select FSL_LSCH2
	select SYS_FSL_DDR
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_ERRATUM_A008336
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A008850
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
	select SYS_FSL_ERRATUM_A010539
	select SYS_FSL_HAS_DDR4
	select SYS_FSL_SRDS_2
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config ARCH_LS2080A
	bool
	select ARMV8_SET_SMPEN
	select ARM_ERRATA_826974
	select ARM_ERRATA_828024
	select ARM_ERRATA_829520
	select ARM_ERRATA_833471
	select FSL_LSCH3
	select SYS_FSL_DDR
	select SYS_FSL_DDR_LE
	select SYS_FSL_DDR_VER_50
	select SYS_FSL_HAS_DP_DDR
	select SYS_FSL_HAS_SEC
	select SYS_FSL_HAS_DDR4
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_LE
	select SYS_FSL_SRDS_2
	select FSL_TZASC_1
	select FSL_TZASC_2
	select SYS_FSL_ERRATUM_A008336
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A008514
	select SYS_FSL_ERRATUM_A008585
	select SYS_FSL_ERRATUM_A009635
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
	select SYS_FSL_ERRATUM_A009203
	select ARCH_EARLY_INIT_R
	select BOARD_EARLY_INIT_F

config FSL_LSCH2
	bool
	select SYS_FSL_HAS_SEC
	select SYS_FSL_SEC_COMPAT_5
	select SYS_FSL_SEC_BE
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

config FSL_LSCH3
	bool
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES

config FSL_MC_ENET
	bool "Management Complex network"
	depends on ARCH_LS2080A
	default y
	select RESV_RAM
	help
	  Enable Management Complex (MC) network

menu "Layerscape architecture"
	depends on FSL_LSCH2 || FSL_LSCH3

config FSL_PCIE_COMPAT
	string "PCIe compatible of Kernel DT"
	depends on PCIE_LAYERSCAPE
	default "fsl,ls1012a-pcie" if ARCH_LS1012A
	default "fsl,ls1043a-pcie" if ARCH_LS1043A
	default "fsl,ls1046a-pcie" if ARCH_LS1046A
	default "fsl,ls2080a-pcie" if ARCH_LS2080A
	help
	  This compatible is used to find pci controller node in Kernel DT
	  to complete fixup.

config HAS_FEATURE_GIC64K_ALIGN
	bool
	default y if ARCH_LS1043A

config HAS_FEATURE_ENHANCED_MSI
	bool
	default y if ARCH_LS1043A

menu "Layerscape PPA"
config FSL_LS_PPA
	bool "FSL Layerscape PPA firmware support"
	depends on !ARMV8_PSCI
	select ARMV8_SEC_FIRMWARE_SUPPORT
	select SEC_FIRMWARE_ARMV8_PSCI
	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
	help
	  The FSL Primary Protected Application (PPA) is a software component
	  which is loaded during boot stage, and then remains resident in RAM
	  and runs in the TrustZone after boot.
	  Say y to enable it.
choice
	prompt "FSL Layerscape PPA firmware loading-media select"
	depends on FSL_LS_PPA
	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
	default SYS_LS_PPA_FW_IN_XIP

config SYS_LS_PPA_FW_IN_XIP
	bool "XIP"
	help
	  Say Y here if the PPA firmware locate at XIP flash, such
	  as NOR or QSPI flash.

config SYS_LS_PPA_FW_IN_MMC
	bool "eMMC or SD Card"
	help
	  Say Y here if the PPA firmware locate at eMMC/SD card.

config SYS_LS_PPA_FW_IN_NAND
	bool "NAND"
	help
	  Say Y here if the PPA firmware locate at NAND flash.

endchoice

config SYS_LS_PPA_FW_ADDR
	hex "Address of PPA firmware loading from"
	depends on FSL_LS_PPA
	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
	default 0x400000 if SYS_LS_PPA_FW_IN_NAND

	help
	  If the PPA firmware locate at XIP flash, such as NOR or
	  QSPI flash, this address is a directly memory-mapped.
	  If it is in a serial accessed flash, such as NAND and SD
	  card, it is a byte offset.

config SYS_LS_PPA_ESBC_ADDR
	hex "hdr address of PPA firmware loading from"
	depends on FSL_LS_PPA && CHAIN_OF_TRUST
	default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
	default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
	default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
	default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
	default 0x700000 if SYS_LS_PPA_FW_IN_MMC
	default 0x700000 if SYS_LS_PPA_FW_IN_NAND
	help
	  If the PPA header firmware locate at XIP flash, such as NOR or
	  QSPI flash, this address is a directly memory-mapped.
	  If it is in a serial accessed flash, such as NAND and SD
	  card, it is a byte offset.

config LS_PPA_ESBC_HDR_SIZE
	hex "Length of PPA ESBC header"
	depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
	default 0x2000
	help
	  Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
	  NAND to memory to validate PPA image.

endmenu

config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"

config SYS_FSL_ERRATUM_A010539
	bool "Workaround for PIN MUX erratum A010539"

config MAX_CPUS
	int "Maximum number of CPUs permitted for Layerscape"
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 16 if ARCH_LS2080A
	default 1
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

config SECURE_BOOT
	bool "Secure Boot"
	help
		Enable Freescale Secure Boot feature

config QSPI_AHB_INIT
	bool "Init the QSPI AHB bus"
	help
	  The default setting for QSPI AHB bus just support 3bytes addressing.
	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
	  bus for those flashes to support the full QSPI flash size.

config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 8 if ARCH_LS2080A

config SYS_FSL_HAS_DP_DDR
	bool

config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

config FSL_TZASC_1
	bool

config FSL_TZASC_2
	bool

endmenu

menu "Layerscape clock tree configuration"
	depends on FSL_LSCH2 || FSL_LSCH3

config SYS_FSL_CLK
	bool "Enable clock tree initialization"
	default y

config CLUSTER_CLK_FREQ
	int "Reference clock of core cluster"
	depends on ARCH_LS1012A
	default 100000000
	help
	  This number is the reference clock frequency of core PLL.
	  For most platforms, the core PLL and Platform PLL have the same
	  reference clock, but for some platforms, LS1012A for instance,
	  they are provided sepatately.

config SYS_FSL_PCLK_DIV
	int "Platform clock divider"
	default 1 if ARCH_LS1043A
	default 1 if ARCH_LS1046A
	default 2
	help
	  This is the divider that is used to derive Platform clock from
	  Platform PLL, in another word:
		Platform_clk = Platform_PLL_freq / this_divider

config SYS_FSL_DSPI_CLK_DIV
	int "DSPI clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive DSPI clock from Platform
	  PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.

config SYS_FSL_DUART_CLK_DIV
	int "DUART clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive DUART clock from Platform
	  clock, in another word DUART_clk = Platform_clk / this_divider.

config SYS_FSL_I2C_CLK_DIV
	int "I2C clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive I2C clock from Platform
	  clock, in another word I2C_clk = Platform_clk / this_divider.

config SYS_FSL_IFC_CLK_DIV
	int "IFC clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive IFC clock from Platform
	  clock, in another word IFC_clk = Platform_clk / this_divider.

config SYS_FSL_LPUART_CLK_DIV
	int "LPUART clock divider"
	default 1 if ARCH_LS1043A
	default 2
	help
	  This is the divider that is used to derive LPUART clock from Platform
	  clock, in another word LPUART_clk = Platform_clk / this_divider.

config SYS_FSL_SDHC_CLK_DIV
	int "SDHC clock divider"
	default 1 if ARCH_LS1043A
	default 1 if ARCH_LS1012A
	default 2
	help
	  This is the divider that is used to derive SDHC clock from Platform
	  clock, in another word SDHC_clk = Platform_clk / this_divider.
endmenu

config RESV_RAM
	bool
	help
	  Reserve memory from the top, tracked by gd->arch.resv_ram. This
	  reserved RAM can be used by special driver that resides in memory
	  after U-Boot exits. It's up to implementation to allocate and allow
	  access to this reserved memory. For example, the reserved RAM can
	  be at the high end of physical memory. The reserve RAM may be
	  excluded from memory bank(s) passed to OS, or marked as reserved.

config SYS_FSL_ERRATUM_A008336
	bool

config SYS_FSL_ERRATUM_A008514
	bool

config SYS_FSL_ERRATUM_A008585
	bool

config SYS_FSL_ERRATUM_A008850
	bool

config SYS_FSL_ERRATUM_A009203
	bool

config SYS_FSL_ERRATUM_A009635
	bool

config SYS_FSL_ERRATUM_A009660
	bool

config SYS_FSL_ERRATUM_A009929
	bool

config SYS_MC_RSV_MEM_ALIGN
	hex "Management Complex reserved memory alignment"
	depends on RESV_RAM
	default 0x20000000
	help
	  Reserved memory needs to be aligned for MC to use. Default value
	  is 512MB.
Commit	Line	Data
9533acf3	1	config ARCH_LS1012A
4a444176	2	bool
ee2a5102	3	select ARMV8_SET_SMPEN
fb2bf8c2	4	select FSL_LSCH2
24aaa094	5	select SYS_FSL_DDR_BE
9533acf3	6	select SYS_FSL_MMDC
0a37cf8f	7	select SYS_FSL_ERRATUM_A010315
a421192f	8	select ARCH_EARLY_INIT_R
a5d67547	9	select BOARD_EARLY_INIT_F
0a37cf8f YS	10
0a37cf8f YS	11	config ARCH_LS1043A
4a444176	12	bool
ee2a5102	13	select ARMV8_SET_SMPEN
fb2bf8c2	14	select FSL_LSCH2
d26e34c4	15	select SYS_FSL_DDR
24aaa094 YS	16	select SYS_FSL_DDR_BE
24aaa094 YS	17	select SYS_FSL_DDR_VER_50
ba1b6fb5 YS	18	select SYS_FSL_ERRATUM_A008850
	19	select SYS_FSL_ERRATUM_A009660
	20	select SYS_FSL_ERRATUM_A009663
	21	select SYS_FSL_ERRATUM_A009929
	22	select SYS_FSL_ERRATUM_A009942
0a37cf8f	23	select SYS_FSL_ERRATUM_A010315
0ea3671d	24	select SYS_FSL_ERRATUM_A010539
d26e34c4 YS	25	select SYS_FSL_HAS_DDR3
d26e34c4 YS	26	select SYS_FSL_HAS_DDR4
a421192f	27	select ARCH_EARLY_INIT_R
a5d67547	28	select BOARD_EARLY_INIT_F
9533acf3	29
da28e58a	30	config ARCH_LS1046A
4a444176	31	bool
ee2a5102	32	select ARMV8_SET_SMPEN
fb2bf8c2	33	select FSL_LSCH2
d26e34c4	34	select SYS_FSL_DDR
24aaa094	35	select SYS_FSL_DDR_BE
24aaa094	36	select SYS_FSL_DDR_VER_50
0ae7050c	37	select SYS_FSL_ERRATUM_A008336
ba1b6fb5	38	select SYS_FSL_ERRATUM_A008511
fb806ad6	39	select SYS_FSL_ERRATUM_A008850
ba1b6fb5 YS	40	select SYS_FSL_ERRATUM_A009801
	41	select SYS_FSL_ERRATUM_A009803
	42	select SYS_FSL_ERRATUM_A009942
	43	select SYS_FSL_ERRATUM_A010165
0ea3671d	44	select SYS_FSL_ERRATUM_A010539
d26e34c4	45	select SYS_FSL_HAS_DDR4
f534b8f5	46	select SYS_FSL_SRDS_2
a421192f	47	select ARCH_EARLY_INIT_R
a5d67547	48	select BOARD_EARLY_INIT_F
9533acf3	49
4a444176 YS	50	config ARCH_LS2080A
4a444176 YS	51	bool
ee2a5102	52	select ARMV8_SET_SMPEN
8dda2e2f TR	53	select ARM_ERRATA_826974
	54	select ARM_ERRATA_828024
	55	select ARM_ERRATA_829520
	56	select ARM_ERRATA_833471
fb2bf8c2	57	select FSL_LSCH3
d26e34c4	58	select SYS_FSL_DDR
24aaa094 YS	59	select SYS_FSL_DDR_LE
24aaa094 YS	60	select SYS_FSL_DDR_VER_50
f534b8f5	61	select SYS_FSL_HAS_DP_DDR
2c2e2c9e	62	select SYS_FSL_HAS_SEC
d26e34c4	63	select SYS_FSL_HAS_DDR4
2c2e2c9e	64	select SYS_FSL_SEC_COMPAT_5
90b80386	65	select SYS_FSL_SEC_LE
f534b8f5	66	select SYS_FSL_SRDS_2
85a9a14e A	67	select FSL_TZASC_1
85a9a14e A	68	select FSL_TZASC_2
ba1b6fb5 YS	69	select SYS_FSL_ERRATUM_A008336
	70	select SYS_FSL_ERRATUM_A008511
	71	select SYS_FSL_ERRATUM_A008514
	72	select SYS_FSL_ERRATUM_A008585
	73	select SYS_FSL_ERRATUM_A009635
	74	select SYS_FSL_ERRATUM_A009663
	75	select SYS_FSL_ERRATUM_A009801
	76	select SYS_FSL_ERRATUM_A009803
	77	select SYS_FSL_ERRATUM_A009942
	78	select SYS_FSL_ERRATUM_A010165
dd48f0bf	79	select SYS_FSL_ERRATUM_A009203
a421192f	80	select ARCH_EARLY_INIT_R
a5d67547	81	select BOARD_EARLY_INIT_F
fb2bf8c2 YS	82
	83	config FSL_LSCH2
	84	bool
2c2e2c9e YS	85	select SYS_FSL_HAS_SEC
2c2e2c9e YS	86	select SYS_FSL_SEC_COMPAT_5
90b80386	87	select SYS_FSL_SEC_BE
f534b8f5 YS	88	select SYS_FSL_SRDS_1
f534b8f5 YS	89	select SYS_HAS_SERDES
fb2bf8c2 YS	90
	91	config FSL_LSCH3
	92	bool
f534b8f5 YS	93	select SYS_FSL_SRDS_1
f534b8f5 YS	94	select SYS_HAS_SERDES
fb2bf8c2	95
e243b6e1 YS	96	config FSL_MC_ENET
	97	bool "Management Complex network"
	98	depends on ARCH_LS2080A
	99	default y
	100	select RESV_RAM
	101	help
	102	Enable Management Complex (MC) network
	103
fb2bf8c2 YS	104	menu "Layerscape architecture"
fb2bf8c2 YS	105	depends on FSL_LSCH2 \|\| FSL_LSCH3
4a444176	106
19538f30 HZ	107	config FSL_PCIE_COMPAT
	108	string "PCIe compatible of Kernel DT"
	109	depends on PCIE_LAYERSCAPE
	110	default "fsl,ls1012a-pcie" if ARCH_LS1012A
	111	default "fsl,ls1043a-pcie" if ARCH_LS1043A
	112	default "fsl,ls1046a-pcie" if ARCH_LS1046A
	113	default "fsl,ls2080a-pcie" if ARCH_LS2080A
	114	help
	115	This compatible is used to find pci controller node in Kernel DT
	116	to complete fixup.
	117
fa18ed76 WS	118	config HAS_FEATURE_GIC64K_ALIGN
	119	bool
	120	default y if ARCH_LS1043A
	121
2ca84bf7 WS	122	config HAS_FEATURE_ENHANCED_MSI
	123	bool
	124	default y if ARCH_LS1043A
fa18ed76	125
2d16a1a6	126	menu "Layerscape PPA"
	127	config FSL_LS_PPA
	128	bool "FSL Layerscape PPA firmware support"
df88cb3b	129	depends on !ARMV8_PSCI
0541527b	130	select ARMV8_SEC_FIRMWARE_SUPPORT
daa92644	131	select SEC_FIRMWARE_ARMV8_PSCI
0541527b	132	select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
2d16a1a6	133	help
	134	The FSL Primary Protected Application (PPA) is a software component
	135	which is loaded during boot stage, and then remains resident in RAM
	136	and runs in the TrustZone after boot.
	137	Say y to enable it.
0541527b HZ	138	choice
	139	prompt "FSL Layerscape PPA firmware loading-media select"
	140	depends on FSL_LS_PPA
77bbe55d HZ	141	default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
77bbe55d HZ	142	default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
0541527b HZ	143	default SYS_LS_PPA_FW_IN_XIP
	144
	145	config SYS_LS_PPA_FW_IN_XIP
	146	bool "XIP"
	147	help
	148	Say Y here if the PPA firmware locate at XIP flash, such
	149	as NOR or QSPI flash.
	150
77bbe55d HZ	151	config SYS_LS_PPA_FW_IN_MMC
	152	bool "eMMC or SD Card"
	153	help
	154	Say Y here if the PPA firmware locate at eMMC/SD card.
	155
	156	config SYS_LS_PPA_FW_IN_NAND
	157	bool "NAND"
	158	help
	159	Say Y here if the PPA firmware locate at NAND flash.
	160
0541527b HZ	161	endchoice
	162
	163	config SYS_LS_PPA_FW_ADDR
	164	hex "Address of PPA firmware loading from"
	165	depends on FSL_LS_PPA
89a168f7	166	default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
a9a5cef3	167	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
f5bf23d8	168	default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
a9a5cef3 AW	169	default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
	170	default 0x400000 if SYS_LS_PPA_FW_IN_MMC
	171	default 0x400000 if SYS_LS_PPA_FW_IN_NAND
77bbe55d	172
0541527b HZ	173	help
	174	If the PPA firmware locate at XIP flash, such as NOR or
	175	QSPI flash, this address is a directly memory-mapped.
	176	If it is in a serial accessed flash, such as NAND and SD
	177	card, it is a byte offset.
d1a795ac VPB	178
	179	config SYS_LS_PPA_ESBC_ADDR
	180	hex "hdr address of PPA firmware loading from"
	181	depends on FSL_LS_PPA && CHAIN_OF_TRUST
	182	default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
b3635f57	183	default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
d2a99502	184	default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
d1a795ac	185	default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
9fa3a542 SG	186	default 0x700000 if SYS_LS_PPA_FW_IN_MMC
9fa3a542 SG	187	default 0x700000 if SYS_LS_PPA_FW_IN_NAND
d1a795ac VPB	188	help
	189	If the PPA header firmware locate at XIP flash, such as NOR or
	190	QSPI flash, this address is a directly memory-mapped.
	191	If it is in a serial accessed flash, such as NAND and SD
	192	card, it is a byte offset.
	193
9fa3a542 SG	194	config LS_PPA_ESBC_HDR_SIZE
	195	hex "Length of PPA ESBC header"
	196	depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
	197	default 0x2000
	198	help
	199	Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
	200	NAND to memory to validate PPA image.
	201
2d16a1a6	202	endmenu
2d16a1a6	203
0a37cf8f YS	204	config SYS_FSL_ERRATUM_A010315
0a37cf8f YS	205	bool "Workaround for PCIe erratum A010315"
0ea3671d HZ	206
	207	config SYS_FSL_ERRATUM_A010539
	208	bool "Workaround for PIN MUX erratum A010539"
fb2bf8c2	209
b4b60d06 YS	210	config MAX_CPUS
	211	int "Maximum number of CPUs permitted for Layerscape"
	212	default 4 if ARCH_LS1043A
	213	default 4 if ARCH_LS1046A
	214	default 16 if ARCH_LS2080A
	215	default 1
	216	help
	217	Set this number to the maximum number of possible CPUs in the SoC.
	218	SoCs may have multiple clusters with each cluster may have multiple
	219	ports. If some ports are reserved but higher ports are used for
	220	cores, count the reserved ports. This will allocate enough memory
	221	in spin table to properly handle all cores.
	222
01f65d97	223	config SECURE_BOOT
9cfab06e	224	bool "Secure Boot"
01f65d97 YS	225	help
	226	Enable Freescale Secure Boot feature
	227
dd2ad2f1 YY	228	config QSPI_AHB_INIT
	229	bool "Init the QSPI AHB bus"
	230	help
	231	The default setting for QSPI AHB bus just support 3bytes addressing.
	232	But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
	233	bus for those flashes to support the full QSPI flash size.
	234
25af7dc1 YS	235	config SYS_FSL_IFC_BANK_COUNT
	236	int "Maximum banks of Integrated flash controller"
	237	depends on ARCH_LS1043A \|\| ARCH_LS1046A \|\| ARCH_LS2080A
	238	default 4 if ARCH_LS1043A
	239	default 4 if ARCH_LS1046A
	240	default 8 if ARCH_LS2080A
	241
fd638102 YS	242	config SYS_FSL_HAS_DP_DDR
	243	bool
	244
f534b8f5 YS	245	config SYS_FSL_SRDS_1
	246	bool
	247
	248	config SYS_FSL_SRDS_2
	249	bool
	250
	251	config SYS_HAS_SERDES
	252	bool
	253
85a9a14e A	254	config FSL_TZASC_1
	255	bool
	256
	257	config FSL_TZASC_2
	258	bool
	259
fb2bf8c2	260	endmenu
ba1b6fb5	261
904110c7 HZ	262	menu "Layerscape clock tree configuration"
	263	depends on FSL_LSCH2 \|\| FSL_LSCH3
	264
	265	config SYS_FSL_CLK
	266	bool "Enable clock tree initialization"
	267	default y
	268
	269	config CLUSTER_CLK_FREQ
	270	int "Reference clock of core cluster"
	271	depends on ARCH_LS1012A
	272	default 100000000
	273	help
	274	This number is the reference clock frequency of core PLL.
	275	For most platforms, the core PLL and Platform PLL have the same
	276	reference clock, but for some platforms, LS1012A for instance,
	277	they are provided sepatately.
	278
	279	config SYS_FSL_PCLK_DIV
	280	int "Platform clock divider"
	281	default 1 if ARCH_LS1043A
	282	default 1 if ARCH_LS1046A
	283	default 2
	284	help
	285	This is the divider that is used to derive Platform clock from
	286	Platform PLL, in another word:
	287	Platform_clk = Platform_PLL_freq / this_divider
	288
	289	config SYS_FSL_DSPI_CLK_DIV
	290	int "DSPI clock divider"
	291	default 1 if ARCH_LS1043A
	292	default 2
	293	help
	294	This is the divider that is used to derive DSPI clock from Platform
	295	PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider.
	296
	297	config SYS_FSL_DUART_CLK_DIV
	298	int "DUART clock divider"
	299	default 1 if ARCH_LS1043A
	300	default 2
	301	help
	302	This is the divider that is used to derive DUART clock from Platform
	303	clock, in another word DUART_clk = Platform_clk / this_divider.
	304
	305	config SYS_FSL_I2C_CLK_DIV
	306	int "I2C clock divider"
	307	default 1 if ARCH_LS1043A
	308	default 2
	309	help
	310	This is the divider that is used to derive I2C clock from Platform
	311	clock, in another word I2C_clk = Platform_clk / this_divider.
	312
	313	config SYS_FSL_IFC_CLK_DIV
	314	int "IFC clock divider"
	315	default 1 if ARCH_LS1043A
	316	default 2
	317	help
	318	This is the divider that is used to derive IFC clock from Platform
	319	clock, in another word IFC_clk = Platform_clk / this_divider.
	320
	321	config SYS_FSL_LPUART_CLK_DIV
	322	int "LPUART clock divider"
	323	default 1 if ARCH_LS1043A
	324	default 2
	325	help
326	This is the divider that is used to derive LPUART clock from Platform
327	clock, in another word LPUART_clk = Platform_clk / this_divider.
328
329	config SYS_FSL_SDHC_CLK_DIV
330	int "SDHC clock divider"
331	default 1 if ARCH_LS1043A
332	default 1 if ARCH_LS1012A
333	default 2
334	help
335	This is the divider that is used to derive SDHC clock from Platform
336	clock, in another word SDHC_clk = Platform_clk / this_divider.
337	endmenu
338
f2ccf7f7 YS	339	config RESV_RAM
	340	bool
	341	help
	342	Reserve memory from the top, tracked by gd->arch.resv_ram. This
	343	reserved RAM can be used by special driver that resides in memory
	344	after U-Boot exits. It's up to implementation to allocate and allow
	345	access to this reserved memory. For example, the reserved RAM can
	346	be at the high end of physical memory. The reserve RAM may be
	347	excluded from memory bank(s) passed to OS, or marked as reserved.
	348
ba1b6fb5 YS	349	config SYS_FSL_ERRATUM_A008336
	350	bool
	351
	352	config SYS_FSL_ERRATUM_A008514
	353	bool
	354
	355	config SYS_FSL_ERRATUM_A008585
	356	bool
	357
	358	config SYS_FSL_ERRATUM_A008850
	359	bool
	360
dd48f0bf A	361	config SYS_FSL_ERRATUM_A009203
	362	bool
	363
ba1b6fb5 YS	364	config SYS_FSL_ERRATUM_A009635
	365	bool
	366
	367	config SYS_FSL_ERRATUM_A009660
	368	bool
	369
	370	config SYS_FSL_ERRATUM_A009929
	371	bool
f692d4ee YS	372
	373	config SYS_MC_RSV_MEM_ALIGN
	374	hex "Management Complex reserved memory alignment"
	375	depends on RESV_RAM
	376	default 0x20000000
	377	help
	378	Reserved memory needs to be aligned for MC to use. Default value
	379	is 512MB.