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Commit | Line | Data |
---|---|---|
9533acf3 | 1 | config ARCH_LS1012A |
4a444176 | 2 | bool |
ee2a5102 | 3 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 4 | select FSL_LSCH2 |
24aaa094 | 5 | select SYS_FSL_DDR_BE |
9533acf3 | 6 | select SYS_FSL_MMDC |
0a37cf8f | 7 | select SYS_FSL_ERRATUM_A010315 |
a421192f | 8 | select ARCH_EARLY_INIT_R |
a5d67547 | 9 | select BOARD_EARLY_INIT_F |
0a37cf8f YS |
10 | |
11 | config ARCH_LS1043A | |
4a444176 | 12 | bool |
ee2a5102 | 13 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 14 | select FSL_LSCH2 |
d26e34c4 | 15 | select SYS_FSL_DDR |
24aaa094 YS |
16 | select SYS_FSL_DDR_BE |
17 | select SYS_FSL_DDR_VER_50 | |
ba1b6fb5 YS |
18 | select SYS_FSL_ERRATUM_A008850 |
19 | select SYS_FSL_ERRATUM_A009660 | |
20 | select SYS_FSL_ERRATUM_A009663 | |
21 | select SYS_FSL_ERRATUM_A009929 | |
22 | select SYS_FSL_ERRATUM_A009942 | |
0a37cf8f | 23 | select SYS_FSL_ERRATUM_A010315 |
0ea3671d | 24 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 YS |
25 | select SYS_FSL_HAS_DDR3 |
26 | select SYS_FSL_HAS_DDR4 | |
a421192f | 27 | select ARCH_EARLY_INIT_R |
a5d67547 | 28 | select BOARD_EARLY_INIT_F |
fedb428c | 29 | imply SCSI |
6500ec7a | 30 | imply CMD_PCI |
9533acf3 | 31 | |
da28e58a | 32 | config ARCH_LS1046A |
4a444176 | 33 | bool |
ee2a5102 | 34 | select ARMV8_SET_SMPEN |
fb2bf8c2 | 35 | select FSL_LSCH2 |
d26e34c4 | 36 | select SYS_FSL_DDR |
24aaa094 | 37 | select SYS_FSL_DDR_BE |
24aaa094 | 38 | select SYS_FSL_DDR_VER_50 |
0ae7050c | 39 | select SYS_FSL_ERRATUM_A008336 |
ba1b6fb5 | 40 | select SYS_FSL_ERRATUM_A008511 |
fb806ad6 | 41 | select SYS_FSL_ERRATUM_A008850 |
ba1b6fb5 YS |
42 | select SYS_FSL_ERRATUM_A009801 |
43 | select SYS_FSL_ERRATUM_A009803 | |
44 | select SYS_FSL_ERRATUM_A009942 | |
45 | select SYS_FSL_ERRATUM_A010165 | |
0ea3671d | 46 | select SYS_FSL_ERRATUM_A010539 |
d26e34c4 | 47 | select SYS_FSL_HAS_DDR4 |
f534b8f5 | 48 | select SYS_FSL_SRDS_2 |
a421192f | 49 | select ARCH_EARLY_INIT_R |
a5d67547 | 50 | select BOARD_EARLY_INIT_F |
fedb428c | 51 | imply SCSI |
9533acf3 | 52 | |
4a444176 YS |
53 | config ARCH_LS2080A |
54 | bool | |
ee2a5102 | 55 | select ARMV8_SET_SMPEN |
8dda2e2f TR |
56 | select ARM_ERRATA_826974 |
57 | select ARM_ERRATA_828024 | |
58 | select ARM_ERRATA_829520 | |
59 | select ARM_ERRATA_833471 | |
fb2bf8c2 | 60 | select FSL_LSCH3 |
d26e34c4 | 61 | select SYS_FSL_DDR |
24aaa094 YS |
62 | select SYS_FSL_DDR_LE |
63 | select SYS_FSL_DDR_VER_50 | |
c055cee1 | 64 | select SYS_FSL_HAS_CCN504 |
f534b8f5 | 65 | select SYS_FSL_HAS_DP_DDR |
2c2e2c9e | 66 | select SYS_FSL_HAS_SEC |
d26e34c4 | 67 | select SYS_FSL_HAS_DDR4 |
2c2e2c9e | 68 | select SYS_FSL_SEC_COMPAT_5 |
90b80386 | 69 | select SYS_FSL_SEC_LE |
f534b8f5 | 70 | select SYS_FSL_SRDS_2 |
85a9a14e A |
71 | select FSL_TZASC_1 |
72 | select FSL_TZASC_2 | |
ba1b6fb5 YS |
73 | select SYS_FSL_ERRATUM_A008336 |
74 | select SYS_FSL_ERRATUM_A008511 | |
75 | select SYS_FSL_ERRATUM_A008514 | |
76 | select SYS_FSL_ERRATUM_A008585 | |
77 | select SYS_FSL_ERRATUM_A009635 | |
78 | select SYS_FSL_ERRATUM_A009663 | |
79 | select SYS_FSL_ERRATUM_A009801 | |
80 | select SYS_FSL_ERRATUM_A009803 | |
81 | select SYS_FSL_ERRATUM_A009942 | |
82 | select SYS_FSL_ERRATUM_A010165 | |
dd48f0bf | 83 | select SYS_FSL_ERRATUM_A009203 |
a421192f | 84 | select ARCH_EARLY_INIT_R |
a5d67547 | 85 | select BOARD_EARLY_INIT_F |
fb2bf8c2 YS |
86 | |
87 | config FSL_LSCH2 | |
88 | bool | |
63b2316c | 89 | select SYS_FSL_HAS_CCI400 |
2c2e2c9e YS |
90 | select SYS_FSL_HAS_SEC |
91 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 92 | select SYS_FSL_SEC_BE |
f534b8f5 YS |
93 | select SYS_FSL_SRDS_1 |
94 | select SYS_HAS_SERDES | |
fb2bf8c2 YS |
95 | |
96 | config FSL_LSCH3 | |
97 | bool | |
f534b8f5 YS |
98 | select SYS_FSL_SRDS_1 |
99 | select SYS_HAS_SERDES | |
fb2bf8c2 | 100 | |
e243b6e1 YS |
101 | config FSL_MC_ENET |
102 | bool "Management Complex network" | |
103 | depends on ARCH_LS2080A | |
104 | default y | |
105 | select RESV_RAM | |
106 | help | |
107 | Enable Management Complex (MC) network | |
108 | ||
fb2bf8c2 YS |
109 | menu "Layerscape architecture" |
110 | depends on FSL_LSCH2 || FSL_LSCH3 | |
4a444176 | 111 | |
19538f30 HZ |
112 | config FSL_PCIE_COMPAT |
113 | string "PCIe compatible of Kernel DT" | |
114 | depends on PCIE_LAYERSCAPE | |
115 | default "fsl,ls1012a-pcie" if ARCH_LS1012A | |
116 | default "fsl,ls1043a-pcie" if ARCH_LS1043A | |
117 | default "fsl,ls1046a-pcie" if ARCH_LS1046A | |
118 | default "fsl,ls2080a-pcie" if ARCH_LS2080A | |
119 | help | |
120 | This compatible is used to find pci controller node in Kernel DT | |
121 | to complete fixup. | |
122 | ||
fa18ed76 WS |
123 | config HAS_FEATURE_GIC64K_ALIGN |
124 | bool | |
125 | default y if ARCH_LS1043A | |
126 | ||
2ca84bf7 WS |
127 | config HAS_FEATURE_ENHANCED_MSI |
128 | bool | |
129 | default y if ARCH_LS1043A | |
fa18ed76 | 130 | |
2d16a1a6 | 131 | menu "Layerscape PPA" |
132 | config FSL_LS_PPA | |
133 | bool "FSL Layerscape PPA firmware support" | |
df88cb3b | 134 | depends on !ARMV8_PSCI |
0541527b | 135 | select ARMV8_SEC_FIRMWARE_SUPPORT |
daa92644 | 136 | select SEC_FIRMWARE_ARMV8_PSCI |
0541527b | 137 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
2d16a1a6 | 138 | help |
139 | The FSL Primary Protected Application (PPA) is a software component | |
140 | which is loaded during boot stage, and then remains resident in RAM | |
141 | and runs in the TrustZone after boot. | |
142 | Say y to enable it. | |
8e59778b YS |
143 | |
144 | config SPL_FSL_LS_PPA | |
145 | bool "FSL Layerscape PPA firmware support for SPL build" | |
146 | depends on !ARMV8_PSCI | |
147 | select SPL_ARMV8_SEC_FIRMWARE_SUPPORT | |
148 | select SEC_FIRMWARE_ARMV8_PSCI | |
149 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 | |
150 | help | |
151 | The FSL Primary Protected Application (PPA) is a software component | |
152 | which is loaded during boot stage, and then remains resident in RAM | |
153 | and runs in the TrustZone after boot. This is to load PPA during SPL | |
154 | stage instead of the RAM version of U-Boot. Once PPA is initialized, | |
155 | the rest of U-Boot (including RAM version) runs at EL2. | |
0541527b HZ |
156 | choice |
157 | prompt "FSL Layerscape PPA firmware loading-media select" | |
158 | depends on FSL_LS_PPA | |
77bbe55d HZ |
159 | default SYS_LS_PPA_FW_IN_MMC if SD_BOOT |
160 | default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT | |
0541527b HZ |
161 | default SYS_LS_PPA_FW_IN_XIP |
162 | ||
163 | config SYS_LS_PPA_FW_IN_XIP | |
164 | bool "XIP" | |
165 | help | |
166 | Say Y here if the PPA firmware locate at XIP flash, such | |
167 | as NOR or QSPI flash. | |
168 | ||
77bbe55d HZ |
169 | config SYS_LS_PPA_FW_IN_MMC |
170 | bool "eMMC or SD Card" | |
171 | help | |
172 | Say Y here if the PPA firmware locate at eMMC/SD card. | |
173 | ||
174 | config SYS_LS_PPA_FW_IN_NAND | |
175 | bool "NAND" | |
176 | help | |
177 | Say Y here if the PPA firmware locate at NAND flash. | |
178 | ||
0541527b HZ |
179 | endchoice |
180 | ||
181 | config SYS_LS_PPA_FW_ADDR | |
182 | hex "Address of PPA firmware loading from" | |
183 | depends on FSL_LS_PPA | |
89a168f7 | 184 | default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
a9a5cef3 | 185 | default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT |
f5bf23d8 | 186 | default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A |
a9a5cef3 AW |
187 | default 0x60400000 if SYS_LS_PPA_FW_IN_XIP |
188 | default 0x400000 if SYS_LS_PPA_FW_IN_MMC | |
189 | default 0x400000 if SYS_LS_PPA_FW_IN_NAND | |
77bbe55d | 190 | |
0541527b HZ |
191 | help |
192 | If the PPA firmware locate at XIP flash, such as NOR or | |
193 | QSPI flash, this address is a directly memory-mapped. | |
194 | If it is in a serial accessed flash, such as NAND and SD | |
195 | card, it is a byte offset. | |
d1a795ac VPB |
196 | |
197 | config SYS_LS_PPA_ESBC_ADDR | |
198 | hex "hdr address of PPA firmware loading from" | |
199 | depends on FSL_LS_PPA && CHAIN_OF_TRUST | |
06fb06f6 SG |
200 | default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A |
201 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A | |
202 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A | |
15e7c681 UA |
203 | default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
204 | default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A | |
06fb06f6 SG |
205 | default 0x680000 if SYS_LS_PPA_FW_IN_MMC |
206 | default 0x680000 if SYS_LS_PPA_FW_IN_NAND | |
d1a795ac VPB |
207 | help |
208 | If the PPA header firmware locate at XIP flash, such as NOR or | |
209 | QSPI flash, this address is a directly memory-mapped. | |
210 | If it is in a serial accessed flash, such as NAND and SD | |
211 | card, it is a byte offset. | |
212 | ||
9fa3a542 SG |
213 | config LS_PPA_ESBC_HDR_SIZE |
214 | hex "Length of PPA ESBC header" | |
215 | depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP | |
216 | default 0x2000 | |
217 | help | |
218 | Length (in bytes) of PPA ESBC header to be copied from MMC/SD or | |
219 | NAND to memory to validate PPA image. | |
220 | ||
2d16a1a6 | 221 | endmenu |
222 | ||
0a37cf8f YS |
223 | config SYS_FSL_ERRATUM_A010315 |
224 | bool "Workaround for PCIe erratum A010315" | |
0ea3671d HZ |
225 | |
226 | config SYS_FSL_ERRATUM_A010539 | |
227 | bool "Workaround for PIN MUX erratum A010539" | |
fb2bf8c2 | 228 | |
b4b60d06 YS |
229 | config MAX_CPUS |
230 | int "Maximum number of CPUs permitted for Layerscape" | |
231 | default 4 if ARCH_LS1043A | |
232 | default 4 if ARCH_LS1046A | |
233 | default 16 if ARCH_LS2080A | |
234 | default 1 | |
235 | help | |
236 | Set this number to the maximum number of possible CPUs in the SoC. | |
237 | SoCs may have multiple clusters with each cluster may have multiple | |
238 | ports. If some ports are reserved but higher ports are used for | |
239 | cores, count the reserved ports. This will allocate enough memory | |
240 | in spin table to properly handle all cores. | |
241 | ||
01f65d97 | 242 | config SECURE_BOOT |
9cfab06e | 243 | bool "Secure Boot" |
01f65d97 YS |
244 | help |
245 | Enable Freescale Secure Boot feature | |
246 | ||
dd2ad2f1 YY |
247 | config QSPI_AHB_INIT |
248 | bool "Init the QSPI AHB bus" | |
249 | help | |
250 | The default setting for QSPI AHB bus just support 3bytes addressing. | |
251 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB | |
252 | bus for those flashes to support the full QSPI flash size. | |
253 | ||
63b2316c AK |
254 | config SYS_CCI400_OFFSET |
255 | hex "Offset for CCI400 base" | |
256 | depends on SYS_FSL_HAS_CCI400 | |
257 | default 0x3090000 if ARCH_LS1088A | |
258 | default 0x180000 if FSL_LSCH2 | |
259 | help | |
260 | Offset for CCI400 base | |
261 | CCI400 base addr = CCSRBAR + CCI400_OFFSET | |
262 | ||
25af7dc1 YS |
263 | config SYS_FSL_IFC_BANK_COUNT |
264 | int "Maximum banks of Integrated flash controller" | |
265 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A | |
266 | default 4 if ARCH_LS1043A | |
267 | default 4 if ARCH_LS1046A | |
268 | default 8 if ARCH_LS2080A | |
269 | ||
63b2316c AK |
270 | config SYS_FSL_HAS_CCI400 |
271 | bool | |
272 | ||
c055cee1 AK |
273 | config SYS_FSL_HAS_CCN504 |
274 | bool | |
275 | ||
fd638102 YS |
276 | config SYS_FSL_HAS_DP_DDR |
277 | bool | |
278 | ||
f534b8f5 YS |
279 | config SYS_FSL_SRDS_1 |
280 | bool | |
281 | ||
282 | config SYS_FSL_SRDS_2 | |
283 | bool | |
284 | ||
285 | config SYS_HAS_SERDES | |
286 | bool | |
287 | ||
85a9a14e A |
288 | config FSL_TZASC_1 |
289 | bool | |
290 | ||
291 | config FSL_TZASC_2 | |
292 | bool | |
293 | ||
fb2bf8c2 | 294 | endmenu |
ba1b6fb5 | 295 | |
904110c7 HZ |
296 | menu "Layerscape clock tree configuration" |
297 | depends on FSL_LSCH2 || FSL_LSCH3 | |
298 | ||
299 | config SYS_FSL_CLK | |
300 | bool "Enable clock tree initialization" | |
301 | default y | |
302 | ||
303 | config CLUSTER_CLK_FREQ | |
304 | int "Reference clock of core cluster" | |
305 | depends on ARCH_LS1012A | |
306 | default 100000000 | |
307 | help | |
308 | This number is the reference clock frequency of core PLL. | |
309 | For most platforms, the core PLL and Platform PLL have the same | |
310 | reference clock, but for some platforms, LS1012A for instance, | |
311 | they are provided sepatately. | |
312 | ||
313 | config SYS_FSL_PCLK_DIV | |
314 | int "Platform clock divider" | |
315 | default 1 if ARCH_LS1043A | |
316 | default 1 if ARCH_LS1046A | |
317 | default 2 | |
318 | help | |
319 | This is the divider that is used to derive Platform clock from | |
320 | Platform PLL, in another word: | |
321 | Platform_clk = Platform_PLL_freq / this_divider | |
322 | ||
323 | config SYS_FSL_DSPI_CLK_DIV | |
324 | int "DSPI clock divider" | |
325 | default 1 if ARCH_LS1043A | |
326 | default 2 | |
327 | help | |
328 | This is the divider that is used to derive DSPI clock from Platform | |
bf7aecce | 329 | clock, in another word DSPI_clk = Platform_clk / this_divider. |
904110c7 HZ |
330 | |
331 | config SYS_FSL_DUART_CLK_DIV | |
332 | int "DUART clock divider" | |
333 | default 1 if ARCH_LS1043A | |
334 | default 2 | |
335 | help | |
336 | This is the divider that is used to derive DUART clock from Platform | |
337 | clock, in another word DUART_clk = Platform_clk / this_divider. | |
338 | ||
339 | config SYS_FSL_I2C_CLK_DIV | |
340 | int "I2C clock divider" | |
341 | default 1 if ARCH_LS1043A | |
342 | default 2 | |
343 | help | |
344 | This is the divider that is used to derive I2C clock from Platform | |
345 | clock, in another word I2C_clk = Platform_clk / this_divider. | |
346 | ||
347 | config SYS_FSL_IFC_CLK_DIV | |
348 | int "IFC clock divider" | |
349 | default 1 if ARCH_LS1043A | |
350 | default 2 | |
351 | help | |
352 | This is the divider that is used to derive IFC clock from Platform | |
353 | clock, in another word IFC_clk = Platform_clk / this_divider. | |
354 | ||
355 | config SYS_FSL_LPUART_CLK_DIV | |
356 | int "LPUART clock divider" | |
357 | default 1 if ARCH_LS1043A | |
358 | default 2 | |
359 | help | |
360 | This is the divider that is used to derive LPUART clock from Platform | |
361 | clock, in another word LPUART_clk = Platform_clk / this_divider. | |
362 | ||
363 | config SYS_FSL_SDHC_CLK_DIV | |
364 | int "SDHC clock divider" | |
365 | default 1 if ARCH_LS1043A | |
366 | default 1 if ARCH_LS1012A | |
367 | default 2 | |
368 | help | |
369 | This is the divider that is used to derive SDHC clock from Platform | |
370 | clock, in another word SDHC_clk = Platform_clk / this_divider. | |
371 | endmenu | |
372 | ||
f2ccf7f7 YS |
373 | config RESV_RAM |
374 | bool | |
375 | help | |
376 | Reserve memory from the top, tracked by gd->arch.resv_ram. This | |
377 | reserved RAM can be used by special driver that resides in memory | |
378 | after U-Boot exits. It's up to implementation to allocate and allow | |
379 | access to this reserved memory. For example, the reserved RAM can | |
380 | be at the high end of physical memory. The reserve RAM may be | |
381 | excluded from memory bank(s) passed to OS, or marked as reserved. | |
382 | ||
ba1b6fb5 YS |
383 | config SYS_FSL_ERRATUM_A008336 |
384 | bool | |
385 | ||
386 | config SYS_FSL_ERRATUM_A008514 | |
387 | bool | |
388 | ||
389 | config SYS_FSL_ERRATUM_A008585 | |
390 | bool | |
391 | ||
392 | config SYS_FSL_ERRATUM_A008850 | |
393 | bool | |
394 | ||
dd48f0bf A |
395 | config SYS_FSL_ERRATUM_A009203 |
396 | bool | |
397 | ||
ba1b6fb5 YS |
398 | config SYS_FSL_ERRATUM_A009635 |
399 | bool | |
400 | ||
401 | config SYS_FSL_ERRATUM_A009660 | |
402 | bool | |
403 | ||
404 | config SYS_FSL_ERRATUM_A009929 | |
405 | bool | |
f692d4ee YS |
406 | |
407 | config SYS_MC_RSV_MEM_ALIGN | |
408 | hex "Management Complex reserved memory alignment" | |
409 | depends on RESV_RAM | |
410 | default 0x20000000 | |
411 | help | |
412 | Reserved memory needs to be aligned for MC to use. Default value | |
413 | is 512MB. | |
b529993e PT |
414 | |
415 | config SPL_LDSCRIPT | |
416 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |