[people/ms/u-boot.git] / arch / arm / dts / imx6qdl-icore-rqs.dtsi

/*
 * Copyright (C) 2015 Amarula Solutions B.V.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>

/ {
	memory {
		reg = <0x10000000 0x80000000>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-handle = <&eth_phy>;
	phy-mode = "rgmii";
	status = "okay";

	mdio {
		eth_phy: ethernet-phy {
			rxc-skew-ps = <1140>;
			txc-skew-ps = <1140>;
			txen-skew-ps = <600>;
			rxdv-skew-ps = <240>;
			rxd0-skew-ps = <420>;
			rxd1-skew-ps = <600>;
			rxd2-skew-ps = <420>;
			rxd3-skew-ps = <240>;
			txd0-skew-ps = <60>;
			txd1-skew-ps = <60>;
			txd2-skew-ps = <60>;
			txd3-skew-ps = <240>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	no-1-8-v;
	status = "okay";
};

&iomuxc {
	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
			MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
			MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
		>;
	};

	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
		>;
	};
};
Commit	Line	Data
871ec6da JT	1	/*
	2	* Copyright (C) 2015 Amarula Solutions B.V.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This file is distributed in the hope that it will be useful
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* Or, alternatively
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	#include <dt-bindings/gpio/gpio.h>
	43	#include <dt-bindings/clock/imx6qdl-clock.h>
	44
	45	/ {
	46	memory {
	47	reg = <0x10000000 0x80000000>;
	48	};
	49	};
	50
fcf77483 JT	51	&fec {
	52	pinctrl-names = "default";
	53	pinctrl-0 = <&pinctrl_enet>;
	54	phy-handle = <&eth_phy>;
	55	phy-mode = "rgmii";
	56	status = "okay";
	57
	58	mdio {
	59	eth_phy: ethernet-phy {
	60	rxc-skew-ps = <1140>;
	61	txc-skew-ps = <1140>;
	62	txen-skew-ps = <600>;
	63	rxdv-skew-ps = <240>;
	64	rxd0-skew-ps = <420>;
	65	rxd1-skew-ps = <600>;
	66	rxd2-skew-ps = <420>;
	67	rxd3-skew-ps = <240>;
	68	txd0-skew-ps = <60>;
	69	txd1-skew-ps = <60>;
	70	txd2-skew-ps = <60>;
	71	txd3-skew-ps = <240>;
	72	};
	73	};
	74	};
	75
5fdea9ff JT	76	&i2c1 {
	77	clock-frequency = <100000>;
	78	pinctrl-names = "default";
	79	pinctrl-0 = <&pinctrl_i2c1>;
	80	status = "okay";
	81	};
	82
	83	&i2c2 {
	84	clock-frequency = <100000>;
	85	pinctrl-names = "default";
	86	pinctrl-0 = <&pinctrl_i2c2>;
	87	status = "okay";
	88	};
	89
	90	&i2c3 {
	91	pinctrl-names = "default";
	92	pinctrl-0 = <&pinctrl_i2c3>;
	93	status = "okay";
	94	};
	95
871ec6da JT	96	&uart4 {
	97	pinctrl-names = "default";
	98	pinctrl-0 = <&pinctrl_uart4>;
	99	status = "okay";
	100	};
	101
	102	&usdhc3 {
	103	pinctrl-names = "default";
	104	pinctrl-0 = <&pinctrl_usdhc3>;
	105	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	106	no-1-8-v;
	107	status = "okay";
	108	};
	109
baa0920d JT	110	&usdhc4 {
	111	pinctrl-names = "default";
	112	pinctrl-0 = <&pinctrl_usdhc4>;
	113	no-1-8-v;
	114	status = "okay";
	115	};
	116
871ec6da	117	&iomuxc {
fcf77483 JT	118	pinctrl_enet: enetgrp {
	119	fsl,pins = <
	120	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	121	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	122	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	123	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	124	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	125	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	126	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	127	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
	128	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	129	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	130	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	131	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	132	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	133	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	134	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
	135	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	136	>;
	137	};
	138
5fdea9ff JT	139	pinctrl_i2c1: i2c1grp {
	140	fsl,pins = <
	141	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	142	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	143	>;
	144	};
	145
	146	pinctrl_i2c2: i2c2grp {
	147	fsl,pins = <
	148	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	149	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	150	>;
	151	};
	152
	153	pinctrl_i2c3: i2c3grp {
	154	fsl,pins = <
	155	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	156	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	157	>;
	158	};
	159
871ec6da JT	160	pinctrl_uart4: uart4grp {
	161	fsl,pins = <
	162	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	163	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	164	>;
	165	};
	166
	167	pinctrl_usdhc3: usdhc3grp {
	168	fsl,pins = <
	169	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
	170	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
	171	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
	172	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
	173	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
	174	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
	175	>;
	176	};
baa0920d JT	177
	178	pinctrl_usdhc4: usdhc4grp {
	179	fsl,pins = <
	180	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
	181	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
	182	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
	183	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
	184	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
	185	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
	186	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
	187	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
	188	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
	189	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
	190	>;
	191	};
871ec6da	192	};