[people/ms/u-boot.git] / arch / arm / include / asm / arch-at91 / at91_pmc.h

/*
 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
 *
 * Power Management Controller (PMC) - System peripherals registers.
 * Based on AT91RM9200 datasheet revision E.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef AT91_PMC_H
#define AT91_PMC_H

#define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
#define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
#define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
#define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
#define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)

#ifndef __ASSEMBLY__

#include <asm/types.h>

typedef struct at91_pmc {
	u32	scer;		/* 0x00 System Clock Enable Register */
	u32	scdr;		/* 0x04 System Clock Disable Register */
	u32	scsr;		/* 0x08 System Clock Status Register */
	u32	reserved0;
	u32	pcer;		/* 0x10 Peripheral Clock Enable Register */
	u32	pcdr;		/* 0x14 Peripheral Clock Disable Register */
	u32	pcsr;		/* 0x18 Peripheral Clock Status Register */
	u32	uckr;		/* 0x1C UTMI Clock Register */
	u32	mor;		/* 0x20 Main Oscilator Register */
	u32	mcfr;		/* 0x24 Main Clock Frequency Register */
	u32	pllar;		/* 0x28 PLL A Register */
	u32	pllbr;		/* 0x2C PLL B Register */
	u32	mckr;		/* 0x30 Master Clock Register */
	u32	reserved1;
	u32	usb;		/* 0x38 USB Clock Register */
	u32	reserved2;
	u32	pck[4];		/* 0x40 Programmable Clock Register 0 - 3 */
	u32	reserved3[4];
	u32	ier;		/* 0x60 Interrupt Enable Register */
	u32	idr;		/* 0x64 Interrupt Disable Register */
	u32	sr;		/* 0x68 Status Register */
	u32	imr;		/* 0x6C Interrupt Mask Register */
	u32	reserved4[4];
	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
	u32	reserved5[21];
	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
#ifdef CONFIG_SAMA5D3
	u32	reserved6[8];
	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
	u32	pcr;		/* 0x10c Periperial Control Register */
	u32	ocr;		/* 0x110 Oscillator Calibration Register */
#else
	u32	reserved8[5];
#endif
} at91_pmc_t;

#endif	/* end not assembly */

#define AT91_PMC_MOR_MOSCEN		0x01
#define AT91_PMC_MOR_OSCBYPASS		0x02
#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)

#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
#define AT91_PMC_PLLAR_29		0x20000000
#define AT91_PMC_PLLBR_USBDIV_1		0x00000000
#define AT91_PMC_PLLBR_USBDIV_2		0x10000000
#define AT91_PMC_PLLBR_USBDIV_4		0x20000000

#define AT91_PMC_MCFR_MAINRDY		0x00010000
#define AT91_PMC_MCFR_MAINF_MASK	0x0000FFFF

#define AT91_PMC_MCKR_CSS_SLOW		0x00000000
#define AT91_PMC_MCKR_CSS_MAIN		0x00000001
#define AT91_PMC_MCKR_CSS_PLLA		0x00000002
#define AT91_PMC_MCKR_CSS_PLLB		0x00000003
#define AT91_PMC_MCKR_CSS_MASK		0x00000003

#ifdef CONFIG_SAMA5D3
#define AT91_PMC_MCKR_PRES_1		0x00000000
#define AT91_PMC_MCKR_PRES_2		0x00000010
#define AT91_PMC_MCKR_PRES_4		0x00000020
#define AT91_PMC_MCKR_PRES_8		0x00000030
#define AT91_PMC_MCKR_PRES_16		0x00000040
#define AT91_PMC_MCKR_PRES_32		0x00000050
#define AT91_PMC_MCKR_PRES_64		0x00000060
#define AT91_PMC_MCKR_PRES_MASK		0x00000070
#else
#define AT91_PMC_MCKR_PRES_1		0x00000000
#define AT91_PMC_MCKR_PRES_2		0x00000004
#define AT91_PMC_MCKR_PRES_4		0x00000008
#define AT91_PMC_MCKR_PRES_8		0x0000000C
#define AT91_PMC_MCKR_PRES_16		0x00000010
#define AT91_PMC_MCKR_PRES_32		0x00000014
#define AT91_PMC_MCKR_PRES_64		0x00000018
#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
#endif

#ifdef CONFIG_AT91RM9200
#define AT91_PMC_MCKR_MDIV_1		0x00000000
#define AT91_PMC_MCKR_MDIV_2		0x00000100
#define AT91_PMC_MCKR_MDIV_3		0x00000200
#define AT91_PMC_MCKR_MDIV_4		0x00000300
#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
#else
#define AT91_PMC_MCKR_MDIV_1		0x00000000
#define AT91_PMC_MCKR_MDIV_2		0x00000100
#ifdef CONFIG_SAMA5D3
#define AT91_PMC_MCKR_MDIV_3		0x00000300
#endif
#define AT91_PMC_MCKR_MDIV_4		0x00000200
#define AT91_PMC_MCKR_MDIV_MASK		0x00000300
#endif

#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
#define AT91_PMC_MCKR_PLLADIV_2		0x00002000

#define AT91_PMC_IXR_MOSCS		0x00000001
#define AT91_PMC_IXR_LOCKA		0x00000002
#define AT91_PMC_IXR_LOCKB		0x00000004
#define AT91_PMC_IXR_MCKRDY		0x00000008
#define AT91_PMC_IXR_LOCKU		0x00000040
#define AT91_PMC_IXR_PCKRDY0		0x00000100
#define AT91_PMC_IXR_PCKRDY1		0x00000200
#define AT91_PMC_IXR_PCKRDY2		0x00000400
#define AT91_PMC_IXR_PCKRDY3		0x00000800

#ifdef CONFIG_AT91_LEGACY
#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */

#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
#endif

#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [AT91CAP9 revC only] */
#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */

#ifdef CONFIG_AT91_LEGACY
#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */

#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
#endif

#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */

#ifdef CONFIG_AT91_LEGACY
#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
#endif
#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
#ifdef CONFIG_AT91_LEGACY
#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
#endif
#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
#ifdef CONFIG_AT91_LEGACY
#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
#endif
#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
#define			AT91_PMC_USBDIV_1		(0 << 28)
#define			AT91_PMC_USBDIV_2		(1 << 28)
#define			AT91_PMC_USBDIV_4		(2 << 28)
#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
#define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */

#ifdef CONFIG_AT91_LEGACY
#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
#endif
#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
#define			AT91_PMC_CSS_SLOW		(0 << 0)
#define			AT91_PMC_CSS_MAIN		(1 << 0)
#define			AT91_PMC_CSS_PLLA		(2 << 0)
#define			AT91_PMC_CSS_PLLB		(3 << 0)
#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
#define			AT91_PMC_PRES_1			(0 << 2)
#define			AT91_PMC_PRES_2			(1 << 2)
#define			AT91_PMC_PRES_4			(2 << 2)
#define			AT91_PMC_PRES_8			(3 << 2)
#define			AT91_PMC_PRES_16		(4 << 2)
#define			AT91_PMC_PRES_32		(5 << 2)
#define			AT91_PMC_PRES_64		(6 << 2)
#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
#define			AT91SAM9_PMC_MDIV_6		(3 << 8)
#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
#define			AT91_PMC_PDIV_1			(0 << 12)
#define			AT91_PMC_PDIV_2			(1 << 12)

#ifdef CONFIG_AT91_LEGACY
#define		AT91_PMC_USB			(AT91_PMC + 0x38)	/* USB Clock Register */
#endif
#define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
#define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
#define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
#define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */

#ifdef CONFIG_AT91_LEGACY
#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */

#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
#endif
#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [AT91CAP9 only] */
#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
#ifdef CONFIG_AT91_LEGACY
#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */

#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
#endif
#define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
#endif /* CONFIG_AT91_LEGACY */
#endif
Commit	Line	Data
6d1dbbbf	1	/*
dc39ae95	2	* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
6d1dbbbf SP	3	*
	4	* Copyright (C) 2005 Ivan Kokshaysky
	5	* Copyright (C) SAN People
5d8e359c	6	* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6d1dbbbf SP	7	*
	8	* Power Management Controller (PMC) - System peripherals registers.
	9	* Based on AT91RM9200 datasheet revision E.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
6d1dbbbf SP	12	*/
	13
	14	#ifndef AT91_PMC_H
	15	#define AT91_PMC_H
	16
80733994 JS	17	#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
	18	#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
	19	#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
	20	#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
	21	#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
5d8e359c JS	22
	23	#ifndef __ASSEMBLY__
	24
	25	#include <asm/types.h>
	26
	27	typedef struct at91_pmc {
	28	u32 scer; /* 0x00 System Clock Enable Register */
	29	u32 scdr; /* 0x04 System Clock Disable Register */
	30	u32 scsr; /* 0x08 System Clock Status Register */
	31	u32 reserved0;
	32	u32 pcer; /* 0x10 Peripheral Clock Enable Register */
	33	u32 pcdr; /* 0x14 Peripheral Clock Disable Register */
	34	u32 pcsr; /* 0x18 Peripheral Clock Status Register */
64203c7b	35	u32 uckr; /* 0x1C UTMI Clock Register */
5d8e359c JS	36	u32 mor; /* 0x20 Main Oscilator Register */
	37	u32 mcfr; /* 0x24 Main Clock Frequency Register */
	38	u32 pllar; /* 0x28 PLL A Register */
	39	u32 pllbr; /* 0x2C PLL B Register */
	40	u32 mckr; /* 0x30 Master Clock Register */
64203c7b SM	41	u32 reserved1;
	42	u32 usb; /* 0x38 USB Clock Register */
	43	u32 reserved2;
5d8e359c JS	44	u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
	45	u32 reserved3[4];
	46	u32 ier; /* 0x60 Interrupt Enable Register */
	47	u32 idr; /* 0x64 Interrupt Disable Register */
	48	u32 sr; /* 0x68 Status Register */
	49	u32 imr; /* 0x6C Interrupt Mask Register */
	50	u32 reserved4[4];
	51	u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */
	52	u32 reserved5[21];
	53	u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
	54	u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
284403aa BS	55	#ifdef CONFIG_SAMA5D3
	56	u32 reserved6[8];
	57	u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
	58	u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
	59	u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
	60	u32 pcr; /* 0x10c Periperial Control Register */
	61	u32 ocr; /* 0x110 Oscillator Calibration Register */
	62	#else
5d8e359c	63	u32 reserved8[5];
284403aa	64	#endif
5d8e359c JS	65	} at91_pmc_t;
	66
	67	#endif /* end not assembly */
	68
	69	#define AT91_PMC_MOR_MOSCEN 0x01
	70	#define AT91_PMC_MOR_OSCBYPASS 0x02
	71	#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8)
	72
	73	#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
	74	#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
	75	#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
	76	#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
	77	#define AT91_PMC_PLLAR_29 0x20000000
	78	#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
	79	#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
	80	#define AT91_PMC_PLLBR_USBDIV_4 0x20000000
	81
7cedb298 JS	82	#define AT91_PMC_MCFR_MAINRDY 0x00010000
	83	#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF
	84
5d8e359c JS	85	#define AT91_PMC_MCKR_CSS_SLOW 0x00000000
	86	#define AT91_PMC_MCKR_CSS_MAIN 0x00000001
	87	#define AT91_PMC_MCKR_CSS_PLLA 0x00000002
	88	#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
	89	#define AT91_PMC_MCKR_CSS_MASK 0x00000003
	90
284403aa BS	91	#ifdef CONFIG_SAMA5D3
	92	#define AT91_PMC_MCKR_PRES_1 0x00000000
	93	#define AT91_PMC_MCKR_PRES_2 0x00000010
	94	#define AT91_PMC_MCKR_PRES_4 0x00000020
	95	#define AT91_PMC_MCKR_PRES_8 0x00000030
	96	#define AT91_PMC_MCKR_PRES_16 0x00000040
	97	#define AT91_PMC_MCKR_PRES_32 0x00000050
	98	#define AT91_PMC_MCKR_PRES_64 0x00000060
	99	#define AT91_PMC_MCKR_PRES_MASK 0x00000070
	100	#else
5d8e359c JS	101	#define AT91_PMC_MCKR_PRES_1 0x00000000
	102	#define AT91_PMC_MCKR_PRES_2 0x00000004
	103	#define AT91_PMC_MCKR_PRES_4 0x00000008
	104	#define AT91_PMC_MCKR_PRES_8 0x0000000C
	105	#define AT91_PMC_MCKR_PRES_16 0x00000010
	106	#define AT91_PMC_MCKR_PRES_32 0x00000014
	107	#define AT91_PMC_MCKR_PRES_64 0x00000018
	108	#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
284403aa	109	#endif
5d8e359c	110
a138d96a	111	#ifdef CONFIG_AT91RM9200
	112	#define AT91_PMC_MCKR_MDIV_1 0x00000000
	113	#define AT91_PMC_MCKR_MDIV_2 0x00000100
	114	#define AT91_PMC_MCKR_MDIV_3 0x00000200
	115	#define AT91_PMC_MCKR_MDIV_4 0x00000300
	116	#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
	117	#else
5d8e359c JS	118	#define AT91_PMC_MCKR_MDIV_1 0x00000000
5d8e359c JS	119	#define AT91_PMC_MCKR_MDIV_2 0x00000100
284403aa BS	120	#ifdef CONFIG_SAMA5D3
	121	#define AT91_PMC_MCKR_MDIV_3 0x00000300
	122	#endif
5d8e359c JS	123	#define AT91_PMC_MCKR_MDIV_4 0x00000200
5d8e359c JS	124	#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
a138d96a	125	#endif
5d8e359c JS	126
	127	#define AT91_PMC_MCKR_PLLADIV_1 0x00001000
	128	#define AT91_PMC_MCKR_PLLADIV_2 0x00002000
	129
	130	#define AT91_PMC_IXR_MOSCS 0x00000001
	131	#define AT91_PMC_IXR_LOCKA 0x00000002
	132	#define AT91_PMC_IXR_LOCKB 0x00000004
	133	#define AT91_PMC_IXR_MCKRDY 0x00000008
	134	#define AT91_PMC_IXR_LOCKU 0x00000040
	135	#define AT91_PMC_IXR_PCKRDY0 0x00000100
	136	#define AT91_PMC_IXR_PCKRDY1 0x00000200
	137	#define AT91_PMC_IXR_PCKRDY2 0x00000400
	138	#define AT91_PMC_IXR_PCKRDY3 0x00000800
	139
	140	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf SP	141	#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
	142	#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
	143
	144	#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
0701f730 MF	145	#endif
0701f730 MF	146
6d1dbbbf SP	147	#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
	148	#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
	149	#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
dc39ae95	150	#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
6d1dbbbf SP	151	#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
	152	#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
	153	#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
	154	#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
	155	#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
	156	#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
	157	#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
	158	#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
	159	#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
	160	#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
	161
0701f730	162	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf SP	163	#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
	164	#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
	165	#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
	166
	167	#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
0701f730 MF	168	#endif
0701f730 MF	169
dc39ae95 JCPV	170	#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
	171	#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
	172	#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
	173	#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
6d1dbbbf	174
0701f730	175	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf	176	#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
0701f730	177	#endif
6d1dbbbf	178	#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
dc39ae95	179	#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
6d1dbbbf	180	#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
0701f730	181	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf	182	#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
0701f730	183	#endif
6d1dbbbf SP	184	#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
6d1dbbbf SP	185	#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
0701f730	186	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf SP	187	#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
6d1dbbbf SP	188	#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
0701f730	189	#endif
6d1dbbbf SP	190	#define AT91_PMC_DIV (0xff << 0) /* Divider */
	191	#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
	192	#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
	193	#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
	194	#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
	195	#define AT91_PMC_USBDIV_1 (0 << 28)
	196	#define AT91_PMC_USBDIV_2 (1 << 28)
	197	#define AT91_PMC_USBDIV_4 (2 << 28)
	198	#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
01550a2b	199	#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
6d1dbbbf	200
0701f730	201	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf	202	#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
0701f730	203	#endif
6d1dbbbf SP	204	#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
	205	#define AT91_PMC_CSS_SLOW (0 << 0)
	206	#define AT91_PMC_CSS_MAIN (1 << 0)
	207	#define AT91_PMC_CSS_PLLA (2 << 0)
	208	#define AT91_PMC_CSS_PLLB (3 << 0)
	209	#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
	210	#define AT91_PMC_PRES_1 (0 << 2)
	211	#define AT91_PMC_PRES_2 (1 << 2)
	212	#define AT91_PMC_PRES_4 (2 << 2)
	213	#define AT91_PMC_PRES_8 (3 << 2)
	214	#define AT91_PMC_PRES_16 (4 << 2)
	215	#define AT91_PMC_PRES_32 (5 << 2)
	216	#define AT91_PMC_PRES_64 (6 << 2)
	217	#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
dc39ae95 JCPV	218	#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
	219	#define AT91RM9200_PMC_MDIV_2 (1 << 8)
	220	#define AT91RM9200_PMC_MDIV_3 (2 << 8)
	221	#define AT91RM9200_PMC_MDIV_4 (3 << 8)
	222	#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
	223	#define AT91SAM9_PMC_MDIV_2 (1 << 8)
	224	#define AT91SAM9_PMC_MDIV_4 (2 << 8)
22ee6473	225	#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
dc39ae95 JCPV	226	#define AT91SAM9_PMC_MDIV_6 (3 << 8)
	227	#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
	228	#define AT91_PMC_PDIV_1 (0 << 12)
	229	#define AT91_PMC_PDIV_2 (1 << 12)
6d1dbbbf	230
64203c7b SM	231	#ifdef CONFIG_AT91_LEGACY
	232	#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */
	233	#endif
	234	#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
	235	#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
	236	#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
	237	#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
	238
0701f730	239	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf SP	240	#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
	241
	242	#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
	243	#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
	244	#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
0701f730	245	#endif
6d1dbbbf SP	246	#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
	247	#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
	248	#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
	249	#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
dc39ae95 JCPV	250	#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
dc39ae95 JCPV	251	#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
6d1dbbbf SP	252	#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
	253	#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
	254	#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
	255	#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
0701f730	256	#ifdef CONFIG_AT91_LEGACY
6d1dbbbf SP	257	#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
6d1dbbbf SP	258
19883aed	259	#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
0701f730	260	#endif
dc39ae95	261	#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
0701f730	262	#ifdef CONFIG_AT91_LEGACY
dc39ae95	263	#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
5d8e359c	264	#endif /* CONFIG_AT91_LEGACY */
6d1dbbbf	265	#endif