[people/ms/u-boot.git] / arch / arm / include / asm / arch-kirkwood / cpu.h

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _KWCPU_H
#define _KWCPU_H

#include <asm/system.h>

#ifndef __ASSEMBLY__

#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))

#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)

#define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
#define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
#define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
#define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
#define SYSRST_CNT_1SEC_VAL		(25*1000000)
#define KW_REG_MPP_OUT_DRV_REG		(KW_MPP_BASE + 0xE0)

enum memory_bank {
	BANK0,
	BANK1,
	BANK2,
	BANK3
};

enum kwcpu_winen {
	KWCPU_WIN_DISABLE,
	KWCPU_WIN_ENABLE
};

enum kwcpu_target {
	KWCPU_TARGET_RESERVED,
	KWCPU_TARGET_MEMORY,
	KWCPU_TARGET_1RESERVED,
	KWCPU_TARGET_SASRAM,
	KWCPU_TARGET_PCIE
};

enum kwcpu_attrib {
	KWCPU_ATTR_SASRAM = 0x01,
	KWCPU_ATTR_DRAM_CS0 = 0x0e,
	KWCPU_ATTR_DRAM_CS1 = 0x0d,
	KWCPU_ATTR_DRAM_CS2 = 0x0b,
	KWCPU_ATTR_DRAM_CS3 = 0x07,
	KWCPU_ATTR_NANDFLASH = 0x2f,
	KWCPU_ATTR_SPIFLASH = 0x1e,
	KWCPU_ATTR_BOOTROM = 0x1d,
	KWCPU_ATTR_PCIE_IO = 0xe0,
	KWCPU_ATTR_PCIE_MEM = 0xe8
};

/*
 * Default Device Address MAP BAR values
 */
#define KW_DEFADR_PCI_MEM	0x90000000
#define KW_DEFADR_PCI_IO	0xC0000000
#define KW_DEFADR_PCI_IO_REMAP	0xC0000000
#define KW_DEFADR_SASRAM	0xC8010000
#define KW_DEFADR_NANDF		0xD8000000
#define KW_DEFADR_SPIF		0xE8000000
#define KW_DEFADR_BOOTROM	0xF8000000

/*
 * read feroceon/sheeva core extra feature register
 * using co-proc instruction
 */
static inline unsigned int readfr_extra_feature_reg(void)
{
	unsigned int val;
	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
			(val)::"cc");
	return val;
}

/*
 * write feroceon/sheeva core extra feature register
 * using co-proc instruction
 */
static inline void writefr_extra_feature_reg(unsigned int val)
{
	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
			(val):"cc");
	isb();
}

/*
 * MBus-L to Mbus Bridge Registers
 * Ref: Datasheet sec:A.3
 */
struct kwwin_registers {
	u32 ctrl;
	u32 base;
	u32 remap_lo;
	u32 remap_hi;
};

/*
 * CPU control and status Registers
 * Ref: Datasheet sec:A.3.2
 */
struct kwcpu_registers {
	u32 config;	/*0x20100 */
	u32 ctrl_stat;	/*0x20104 */
	u32 rstoutn_mask; /* 0x20108 */
	u32 sys_soft_rst; /* 0x2010C */
	u32 ahb_mbus_cause_irq; /* 0x20110 */
	u32 ahb_mbus_mask_irq; /* 0x20114 */
	u32 pad1[2];
	u32 ftdll_config; /* 0x20120 */
	u32 pad2;
	u32 l2_cfg;	/* 0x20128 */
};

/*
 * GPIO Registers
 * Ref: Datasheet sec:A.19
 */
struct kwgpio_registers {
	u32 dout;
	u32 oe;
	u32 blink_en;
	u32 din_pol;
	u32 din;
	u32 irq_cause;
	u32 irq_mask;
	u32 irq_level;
};

/*
 * functions
 */
unsigned char get_random_hex(void);
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
		unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
		unsigned int mpp16_23, unsigned int mpp24_31,
		unsigned int mpp32_39, unsigned int mpp40_47,
		unsigned int mpp48_55);
unsigned int kw_winctrl_calcsize(unsigned int sizeval);
#endif /* __ASSEMBLY__ */
#endif /* _KWCPU_H */
Commit	Line	Data
4efb77d4 PW	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4efb77d4 PW	7	*/
	8
	9	#ifndef _KWCPU_H
	10	#define _KWCPU_H
	11
	12	#include <asm/system.h>
	13
	14	#ifndef __ASSEMBLY__
	15
78eabb90 PW	16	#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en \| (target << 4) \
	17	\| (attr << 8) \| (kw_winctrl_calcsize(size) << 16))
	18
4efb77d4	19	#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
3e75e696	20	((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
4efb77d4	21
c0cd0207 PW	22	#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
c0cd0207 PW	23	#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
4efb77d4	24	#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
49d2cb4d PW	25	#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
49d2cb4d PW	26	#define SYSRST_CNT_1SEC_VAL (25*1000000)
4efb77d4 PW	27	#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
	28
	29	enum memory_bank {
	30	BANK0,
	31	BANK1,
	32	BANK2,
	33	BANK3
	34	};
	35
	36	enum kwcpu_winen {
	37	KWCPU_WIN_DISABLE,
	38	KWCPU_WIN_ENABLE
	39	};
	40
	41	enum kwcpu_target {
	42	KWCPU_TARGET_RESERVED,
	43	KWCPU_TARGET_MEMORY,
	44	KWCPU_TARGET_1RESERVED,
	45	KWCPU_TARGET_SASRAM,
	46	KWCPU_TARGET_PCIE
	47	};
	48
	49	enum kwcpu_attrib {
	50	KWCPU_ATTR_SASRAM = 0x01,
78eabb90 PW	51	KWCPU_ATTR_DRAM_CS0 = 0x0e,
	52	KWCPU_ATTR_DRAM_CS1 = 0x0d,
	53	KWCPU_ATTR_DRAM_CS2 = 0x0b,
	54	KWCPU_ATTR_DRAM_CS3 = 0x07,
4efb77d4 PW	55	KWCPU_ATTR_NANDFLASH = 0x2f,
	56	KWCPU_ATTR_SPIFLASH = 0x1e,
	57	KWCPU_ATTR_BOOTROM = 0x1d,
	58	KWCPU_ATTR_PCIE_IO = 0xe0,
	59	KWCPU_ATTR_PCIE_MEM = 0xe8
	60	};
	61
	62	/*
	63	* Default Device Address MAP BAR values
	64	*/
	65	#define KW_DEFADR_PCI_MEM 0x90000000
	66	#define KW_DEFADR_PCI_IO 0xC0000000
	67	#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
	68	#define KW_DEFADR_SASRAM 0xC8010000
	69	#define KW_DEFADR_NANDF 0xD8000000
	70	#define KW_DEFADR_SPIF 0xE8000000
	71	#define KW_DEFADR_BOOTROM 0xF8000000
	72
	73	/*
	74	* read feroceon/sheeva core extra feature register
	75	* using co-proc instruction
	76	*/
	77	static inline unsigned int readfr_extra_feature_reg(void)
	78	{
	79	unsigned int val;
	80	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
	81	(val)::"cc");
	82	return val;
	83	}
	84
	85	/*
	86	* write feroceon/sheeva core extra feature register
	87	* using co-proc instruction
	88	*/
	89	static inline void writefr_extra_feature_reg(unsigned int val)
	90	{
	91	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
	92	(val):"cc");
	93	isb();
	94	}
	95
	96	/*
	97	* MBus-L to Mbus Bridge Registers
	98	* Ref: Datasheet sec:A.3
	99	*/
	100	struct kwwin_registers {
	101	u32 ctrl;
	102	u32 base;
	103	u32 remap_lo;
	104	u32 remap_hi;
	105	};
	106
	107	/*
	108	* CPU control and status Registers
	109	* Ref: Datasheet sec:A.3.2
	110	*/
	111	struct kwcpu_registers {
	112	u32 config; /0x20100 /
	113	u32 ctrl_stat; /0x20104 /
	114	u32 rstoutn_mask; /* 0x20108 */
	115	u32 sys_soft_rst; /* 0x2010C */
	116	u32 ahb_mbus_cause_irq; /* 0x20110 */
	117	u32 ahb_mbus_mask_irq; /* 0x20114 */
	118	u32 pad1[2];
119	u32 ftdll_config; /* 0x20120 */
120	u32 pad2;
121	u32 l2_cfg; /* 0x20128 */
122	};
123
124	/*
125	* GPIO Registers
126	* Ref: Datasheet sec:A.19
127	*/
128	struct kwgpio_registers {
129	u32 dout;
130	u32 oe;
131	u32 blink_en;
132	u32 din_pol;
133	u32 din;
134	u32 irq_cause;
135	u32 irq_mask;
136	u32 irq_level;
137	};
138
139	/*
140	* functions
141	*/
4efb77d4	142	unsigned char get_random_hex(void);
96c5f081 SR	143	unsigned int mvebu_sdram_bar(enum memory_bank bank);
	144	unsigned int mvebu_sdram_bs(enum memory_bank bank);
	145	void mvebu_sdram_size_adjust(enum memory_bank bank);
4efb77d4	146	int kw_config_adr_windows(void);
d5c5132f	147	void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
4efb77d4 PW	148	unsigned int gpp0_oe, unsigned int gpp1_oe);
	149	int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
	150	unsigned int mpp16_23, unsigned int mpp24_31,
	151	unsigned int mpp32_39, unsigned int mpp40_47,
	152	unsigned int mpp48_55);
78eabb90	153	unsigned int kw_winctrl_calcsize(unsigned int sizeval);
4efb77d4 PW	154	#endif /* __ASSEMBLY__ */
4efb77d4 PW	155	#endif /* _KWCPU_H */