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rockchip: rk3288: Add TPL_LDSCRIPT
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CommitLineData
2444dae5
SG
1if ARCH_ROCKCHIP
2
041cdb5f
HS
3config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
5 select CPU_V7
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KY
6 select SUPPORT_SPL
7 select SPL
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EC
8 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
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HS
10 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
daeed1db
KY
16config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
18 select CPU_V7
19 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
0a2be69f
HS
25config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
27 select CPU_V7
0680f1b1 28 select SPL_BOARD_INIT if SPL
0a2be69f 29 select SUPPORT_SPL
0a2be69f 30 select SPL
4bbb05bc
PT
31 select SPL_CLK
32 select SPL_PINCTRL
33 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
4d9253fb 37 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
008a610b 38 select BOARD_LATE_INIT
0a2be69f
HS
39 select ROCKCHIP_BROM_HELPER
40 help
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43 video interfaces, several memory options and video codec support.
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45 UART, SPI, I2C and PWMs.
168eef7a
KY
46
47config ROCKCHIP_RK322X
48 bool "Support Rockchip RK3228/RK3229"
49 select CPU_V7
50 select SUPPORT_SPL
51 select SPL
52 select ROCKCHIP_BROM_HELPER
53 select DEBUG_UART_BOARD_INIT
54 help
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
57 and video codec support. Peripherals include Gigabit Ethernet,
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
0a2be69f 59
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SG
60config ROCKCHIP_RK3288
61 bool "Support Rockchip RK3288"
e0f5dbcb 62 select CPU_V7
0680f1b1 63 select SPL_BOARD_INIT if SPL
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KY
64 select SUPPORT_SPL
65 select SPL
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EC
66 imply USB_FUNCTION_ROCKUSB
67 imply CMD_ROCKUSB
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SG
68 help
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71 video interfaces supporting HDMI and eDP, several DDR3 options
72 and video codec support. Peripherals include Gigabit Ethernet,
ef904bf2 73 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
2444dae5 74
849f672b
JT
75if ROCKCHIP_RK3288
76
77config TPL_LDSCRIPT
78 default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
79
80endif
81
85a3cfb8
KY
82config ROCKCHIP_RK3328
83 bool "Support Rockchip RK3328"
84 select ARM64
85 help
86 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
87 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
88 video interfaces supporting HDMI and eDP, several DDR3 options
89 and video codec support. Peripherals include Gigabit Ethernet,
90 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
91
37a0c600
AF
92config ROCKCHIP_RK3368
93 bool "Support Rockchip RK3368"
94 select ARM64
5071457e
PT
95 select SUPPORT_SPL
96 select SUPPORT_TPL
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PT
97 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
98 select TPL_NEEDS_SEPARATE_STACK if TPL
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PT
99 imply SPL_SEPARATE_BSS
100 imply SPL_SERIAL_SUPPORT
101 imply TPL_SERIAL_SUPPORT
5071457e 102 select DEBUG_UART_BOARD_INIT
37a0c600
AF
103 select SYS_NS16550
104 help
9a8f009f
PT
105 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
106 into a big and little cluster with 4 cores each) Cortex-A53 including
107 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
108 (for the little cluster), PowerVR G6110 based graphics, one video
109 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
110 video codec support.
111
112 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
113 I2S, UARTs, SPI, I2C and PWMs.
37a0c600 114
d9d1242b
PT
115if ROCKCHIP_RK3368
116
117config TPL_LDSCRIPT
118 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
119
5aa49af3
PT
120config TPL_TEXT_BASE
121 default 0xff8c1000
122
123config TPL_MAX_SIZE
124 default 28672
125
126config TPL_STACK
127 default 0xff8cffff
128
d9d1242b
PT
129endif
130
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KY
131config ROCKCHIP_RK3399
132 bool "Support Rockchip RK3399"
133 select ARM64
66e87cc8
KY
134 select SUPPORT_SPL
135 select SPL
136 select SPL_SEPARATE_BSS
c0508e42
PT
137 select SPL_SERIAL_SUPPORT
138 select SPL_DRIVERS_MISC_SUPPORT
7ee16de5 139 select DEBUG_UART_BOARD_INIT
e3067793 140 select BOARD_LATE_INIT
b4d23f76 141 select ROCKCHIP_BROM_HELPER
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KY
142 help
143 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
144 and quad-core Cortex-A53.
145 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
146 video interfaces supporting HDMI and eDP, several DDR3 options
147 and video codec support. Peripherals include Gigabit Ethernet,
148 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
149
2c1e11dd
AY
150config ROCKCHIP_RV1108
151 bool "Support Rockchip RV1108"
152 select CPU_V7
153 help
154 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
155 and a DSP.
156
ee14d29d 157config SPL_ROCKCHIP_BACK_TO_BROM
b47ea792
XZ
158 bool "SPL returns to bootrom"
159 default y if ROCKCHIP_RK3036
1d845947 160 select ROCKCHIP_BROM_HELPER
ee14d29d
PT
161 depends on SPL
162 help
163 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
164 SPL will return to the boot rom, which will then load the U-Boot
165 binary to keep going on.
166
167config TPL_ROCKCHIP_BACK_TO_BROM
168 bool "TPL returns to bootrom"
169 default y if ROCKCHIP_RK3368
170 select ROCKCHIP_BROM_HELPER
171 depends on TPL
b47ea792
XZ
172 help
173 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
174 SPL will return to the boot rom, which will then load the U-Boot
175 binary to keep going on.
176
e3067793
AY
177config ROCKCHIP_BOOT_MODE_REG
178 hex "Rockchip boot mode flag register address"
179 default 0x200081c8 if ROCKCHIP_RK3036
180 default 0x20004040 if ROCKCHIP_RK3188
181 default 0x110005c8 if ROCKCHIP_RK322X
182 default 0xff730094 if ROCKCHIP_RK3288
183 default 0xff738200 if ROCKCHIP_RK3368
184 default 0xff320300 if ROCKCHIP_RK3399
185 default 0x10300580 if ROCKCHIP_RV1108
186 default 0
187 help
188 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
189 according to the value from this register.
190
fa1392a2
KY
191config ROCKCHIP_SPL_RESERVE_IRAM
192 hex "Size of IRAM reserved in SPL"
8a8106f0 193 default 0
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KY
194 help
195 SPL may need reserve memory for firmware loaded by SPL, whose load
196 address is in IRAM and may overlay with SPL text area if not
197 reserved.
198
1d845947
HS
199config ROCKCHIP_BROM_HELPER
200 bool
201
b377d222
PT
202config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
203 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
204 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
205 help
206 Some Rockchip BROM variants (e.g. on the RK3188) load the
207 first stage in segments and enter multiple times. E.g. on
208 the RK3188, the first 1KB of the first stage are loaded
209 first and entered; after returning to the BROM, the
210 remainder of the first stage is loaded, but the BROM
211 re-enters at the same address/to the same code as previously.
212
213 This enables support code in the BOOT0 hook for the SPL stage
214 to allow multiple entries.
215
216config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
217 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
218 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
219 help
220 Some Rockchip BROM variants (e.g. on the RK3188) load the
221 first stage in segments and enter multiple times. E.g. on
222 the RK3188, the first 1KB of the first stage are loaded
223 first and entered; after returning to the BROM, the
224 remainder of the first stage is loaded, but the BROM
225 re-enters at the same address/to the same code as previously.
226
227 This enables support code in the BOOT0 hook for the TPL stage
228 to allow multiple entries.
229
230e0e09 230config SPL_MMC_SUPPORT
ee14d29d 231 default y if !SPL_ROCKCHIP_BACK_TO_BROM
230e0e09 232
be1d5e03 233source "arch/arm/mach-rockchip/rk3036/Kconfig"
daeed1db 234source "arch/arm/mach-rockchip/rk3128/Kconfig"
0a2be69f 235source "arch/arm/mach-rockchip/rk3188/Kconfig"
b24a8ec1 236source "arch/arm/mach-rockchip/rk322x/Kconfig"
041cdb5f 237source "arch/arm/mach-rockchip/rk3288/Kconfig"
85a3cfb8 238source "arch/arm/mach-rockchip/rk3328/Kconfig"
37a0c600 239source "arch/arm/mach-rockchip/rk3368/Kconfig"
a381bcf5 240source "arch/arm/mach-rockchip/rk3399/Kconfig"
2c1e11dd 241source "arch/arm/mach-rockchip/rv1108/Kconfig"
2444dae5 242endif