[people/ms/u-boot.git] / arch / m68k / include / asm / immap_5227x.h

/*
 * MCF5227x Internal Memory Map
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __IMMAP_5227X__
#define __IMMAP_5227X__

/* Module Base Addresses */
#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x00020000)
#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x0003C000)
#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040010)
#define MMAP_SCM3	(CONFIG_SYS_MBAR + 0x00040070)
#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
#define MMAP_IACK	(CONFIG_SYS_MBAR + 0x00054000)
#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x00090000)
#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00094000)
#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
#define MMAP_ADC	(CONFIG_SYS_MBAR + 0x000A8000)
#define MMAP_LCD	(CONFIG_SYS_MBAR + 0x000AC000)
#define MMAP_LCD_BGLUT	(CONFIG_SYS_MBAR + 0x000AC800)
#define MMAP_LCD_GWLUT	(CONFIG_SYS_MBAR + 0x000ACC00)
#define MMAP_USBHW	(CONFIG_SYS_MBAR + 0x000B0000)
#define MMAP_USBCAPS	(CONFIG_SYS_MBAR + 0x000B0100)
#define MMAP_USBEHCI	(CONFIG_SYS_MBAR + 0x000B0140)
#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B01A0)
#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)

#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>

/* Reset Controller Module (RCM) */
typedef struct rcm {
	u8 rcr;
	u8 rsr;
} rcm_t;

/* Chip Configuration Module (CCM) */
typedef struct ccm {
	u16 ccr;		/* Chip Configuration (Rd-only) */
	u16 resv1;
	u16 rcon;		/* Reset Configuration (Rd-only) */
	u16 cir;		/* Chip Identification (Rd-only) */
	u32 resv2;
	u16 misccr;		/* Miscellaneous Control */
	u16 cdr;		/* Clock Divider */
	u16 uocsr;		/* USB On-the-Go Controller Status */
	u16 resv4;
	u16 sbfsr;		/* Serial Boot Status */
	u16 sbfcr;		/* Serial Boot Control */
} ccm_t;

typedef struct canex_ctrl {
	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
	u32 res0[0x700];	/* 0x100 */
	can_msg_t rxim[16];	/* 0x800 Rx Individual Mask 0-15 */
} canex_t;

/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
	/* Port Output Data Registers */
	u8 podr_be;		/* 0x00 */
	u8 podr_cs;		/* 0x01 */
	u8 podr_fbctl;		/* 0x02 */
	u8 podr_i2c;		/* 0x03 */
	u8 rsvd1;		/* 0x04 */
	u8 podr_uart;		/* 0x05 */
	u8 podr_dspi;		/* 0x06 */
	u8 podr_timer;		/* 0x07 */
	u8 podr_lcdctl;		/* 0x08 */
	u8 podr_lcddatah;	/* 0x09 */
	u8 podr_lcddatam;	/* 0x0A */
	u8 podr_lcddatal;	/* 0x0B */

	/* Port Data Direction Registers */
	u8 pddr_be;		/* 0x0C */
	u8 pddr_cs;		/* 0x0D */
	u8 pddr_fbctl;		/* 0x0E */
	u8 pddr_i2c;		/* 0x0F */
	u8 rsvd2;		/* 0x10 */
	u8 pddr_uart;		/* 0x11 */
	u8 pddr_dspi;		/* 0x12 */
	u8 pddr_timer;		/* 0x13 */
	u8 pddr_lcdctl;		/* 0x14 */
	u8 pddr_lcddatah;	/* 0x15 */
	u8 pddr_lcddatam;	/* 0x16 */
	u8 pddr_lcddatal;	/* 0x17 */

	/* Port Pin Data/Set Data Registers */
	u8 ppdsdr_be;		/* 0x18 */
	u8 ppdsdr_cs;		/* 0x19 */
	u8 ppdsdr_fbctl;	/* 0x1A */
	u8 ppdsdr_i2c;		/* 0x1B */
	u8 rsvd3;		/* 0x1C */
	u8 ppdsdr_uart;		/* 0x1D */
	u8 ppdsdr_dspi;		/* 0x1E */
	u8 ppdsdr_timer;	/* 0x1F */
	u8 ppdsdr_lcdctl;	/* 0x20 */
	u8 ppdsdr_lcddatah;	/* 0x21 */
	u8 ppdsdr_lcddatam;	/* 0x22 */
	u8 ppdsdr_lcddatal;	/* 0x23 */

	/* Port Clear Output Data Registers */
	u8 pclrr_be;		/* 0x24 */
	u8 pclrr_cs;		/* 0x25 */
	u8 pclrr_fbctl;		/* 0x26 */
	u8 pclrr_i2c;		/* 0x27 */
	u8 rsvd4;		/* 0x28 */
	u8 pclrr_uart;		/* 0x29 */
	u8 pclrr_dspi;		/* 0x2A */
	u8 pclrr_timer;		/* 0x2B */
	u8 pclrr_lcdctl;	/* 0x2C */
	u8 pclrr_lcddatah;	/* 0x2D */
	u8 pclrr_lcddatam;	/* 0x2E */
	u8 pclrr_lcddatal;	/* 0x2F */

	/* Pin Assignment Registers */
	u8 par_be;		/* 0x30 */
	u8 par_cs;		/* 0x31 */
	u8 par_fbctl;		/* 0x32 */
	u8 par_i2c;		/* 0x33 */
	u16 par_uart;		/* 0x34 */
	u8 par_dspi;		/* 0x36 */
	u8 par_timer;		/* 0x37 */
	u8 par_lcdctl;		/* 0x38 */
	u8 par_irq;		/* 0x39 */
	u16 rsvd6;		/* 0x3A - 0x3B */
	u32 par_lcdh;		/* 0x3C */
	u32 par_lcdl;		/* 0x40 */

	/* Mode select control registers */
	u8 mscr_fb;		/* 0x44 */
	u8 mscr_sdram;		/* 0x45 */

	u16 rsvd7;		/* 0x46 - 0x47 */
	u8 dscr_dspi;		/* 0x48 */
	u8 dscr_timer;		/* 0x49 */
	u8 dscr_i2c;		/* 0x4A */
	u8 dscr_lcd;		/* 0x4B */
	u8 dscr_debug;		/* 0x4C */
	u8 dscr_clkrst;		/* 0x4D */
	u8 dscr_irq;		/* 0x4E */
	u8 dscr_uart;		/* 0x4F */
} gpio_t;

/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
	u32 sdmr;		/* Mode/Extended Mode */
	u32 sdcr;		/* Control */
	u32 sdcfg1;		/* Configuration 1 */
	u32 sdcfg2;		/* Chip Select */
	u8 resv0[0x100];
	u32 sdcs0;		/* Mode/Extended Mode */
	u32 sdcs1;		/* Mode/Extended Mode */
} sdramc_t;

/* Phase Locked Loop (PLL) */
typedef struct pll {
	u32 pcr;		/* PLL Control */
	u32 psr;		/* PLL Status */
} pll_t;

/* System Control Module register  */
typedef struct scm1 {
	u32 mpr;		/* 0x00 Master Privilege */
	u32 rsvd1[7];
	u32 pacra;		/* 0x20 */
	u32 pacrb;		/* 0x24 */
	u32 pacrc;		/* 0x28 */
	u32 pacrd;		/* 0x2C */
	u32 rsvd2[4];
	u32 pacre;		/* 0x40 */
	u32 pacrf;		/* 0x44 */
	u32 pacrg;		/* 0x48 */
	u32 rsvd3;
	u32 pacri;		/* 0x50 */
} scm1_t;

typedef struct scm2_ctrl {
	u8 res1[3];		/* 0x00 - 0x02 */
	u8 wcr;			/* 0x03 wakeup control */
	u16 res2;		/* 0x04 - 0x05 */
	u16 cwcr;		/* 0x06 Core Watchdog Control */
	u8 res3[3];		/* 0x08 - 0x0A */
	u8 cwsr;		/* 0x0B Core Watchdog Service */
	u8 res4[2];		/* 0x0C - 0x0D */
	u8 scmisr;		/* 0x0F Interrupt Status */
	u32 res5;		/* 0x20 */
	u32 bcr;		/* 0x24 Burst Configuration */
} scm2_t;

typedef struct scm3_ctrl {
	u32 cfadr;		/* 0x00 Core Fault Address */
	u8 res7;		/* 0x04 */
	u8 cfier;		/* 0x05 Core Fault Interrupt Enable */
	u8 cfloc;		/* 0x06 Core Fault Location */
	u8 cfatr;		/* 0x07 Core Fault Attributes */
	u32 cfdtr;		/* 0x08 Core Fault Data */
} scm3_t;

typedef struct rtcex {
	u32 rsvd1[3];
	u32 gocu;
	u32 gocl;
} rtcex_t;
#endif				/* __IMMAP_5227X__ */
Commit	Line	Data
c8758102 TL	1	/*
	2	* MCF5227x Internal Memory Map
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c8758102 TL	8	*/
	9
	10	#ifndef __IMMAP_5227X__
	11	#define __IMMAP_5227X__
	12
	13	/* Module Base Addresses */
6d0f6bcf JCPV	14	#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
	15	#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
	16	#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
	17	#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
	18	#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
	19	#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
	20	#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
	21	#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
	22	#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
	23	#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
	24	#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000)
	25	#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
	26	#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
	27	#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
	28	#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
	29	#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
	30	#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
	31	#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
	32	#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
	33	#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
	34	#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
	35	#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
	36	#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000)
	37	#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000)
	38	#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
	39	#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
	40	#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
	41	#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000)
	42	#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000)
	43	#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800)
	44	#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00)
	45	#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000)
	46	#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100)
	47	#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140)
	48	#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0)
	49	#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
	50	#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
	51	#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
c8758102 TL	52
	53	#include <asm/coldfire/crossbar.h>
	54	#include <asm/coldfire/dspi.h>
	55	#include <asm/coldfire/edma.h>
012522fe	56	#include <asm/coldfire/eport.h>
c8758102	57	#include <asm/coldfire/flexbus.h>
012522fe TL	58	#include <asm/coldfire/flexcan.h>
012522fe TL	59	#include <asm/coldfire/intctrl.h>
c8758102	60	#include <asm/coldfire/lcd.h>
012522fe	61	#include <asm/coldfire/pwm.h>
c8758102 TL	62	#include <asm/coldfire/ssi.h>
c8758102 TL	63
c8758102 TL	64	/* Reset Controller Module (RCM) */
	65	typedef struct rcm {
	66	u8 rcr;
	67	u8 rsr;
	68	} rcm_t;
	69
	70	/* Chip Configuration Module (CCM) */
	71	typedef struct ccm {
	72	u16 ccr; /* Chip Configuration (Rd-only) */
	73	u16 resv1;
	74	u16 rcon; /* Reset Configuration (Rd-only) */
	75	u16 cir; /* Chip Identification (Rd-only) */
	76	u32 resv2;
	77	u16 misccr; /* Miscellaneous Control */
	78	u16 cdr; /* Clock Divider */
	79	u16 uocsr; /* USB On-the-Go Controller Status */
	80	u16 resv4;
	81	u16 sbfsr; /* Serial Boot Status */
	82	u16 sbfcr; /* Serial Boot Control */
	83	} ccm_t;
	84
012522fe TL	85	typedef struct canex_ctrl {
	86	can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
	87	u32 res0[0x700]; /* 0x100 */
	88	can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
	89	} canex_t;
	90
c8758102 TL	91	/* General Purpose I/O Module (GPIO) */
	92	typedef struct gpio {
	93	/* Port Output Data Registers */
	94	u8 podr_be; /* 0x00 */
	95	u8 podr_cs; /* 0x01 */
	96	u8 podr_fbctl; /* 0x02 */
	97	u8 podr_i2c; /* 0x03 */
	98	u8 rsvd1; /* 0x04 */
	99	u8 podr_uart; /* 0x05 */
	100	u8 podr_dspi; /* 0x06 */
	101	u8 podr_timer; /* 0x07 */
	102	u8 podr_lcdctl; /* 0x08 */
	103	u8 podr_lcddatah; /* 0x09 */
	104	u8 podr_lcddatam; /* 0x0A */
	105	u8 podr_lcddatal; /* 0x0B */
	106
	107	/* Port Data Direction Registers */
	108	u8 pddr_be; /* 0x0C */
	109	u8 pddr_cs; /* 0x0D */
	110	u8 pddr_fbctl; /* 0x0E */
	111	u8 pddr_i2c; /* 0x0F */
	112	u8 rsvd2; /* 0x10 */
	113	u8 pddr_uart; /* 0x11 */
	114	u8 pddr_dspi; /* 0x12 */
	115	u8 pddr_timer; /* 0x13 */
	116	u8 pddr_lcdctl; /* 0x14 */
	117	u8 pddr_lcddatah; /* 0x15 */
	118	u8 pddr_lcddatam; /* 0x16 */
	119	u8 pddr_lcddatal; /* 0x17 */
	120
	121	/* Port Pin Data/Set Data Registers */
	122	u8 ppdsdr_be; /* 0x18 */
	123	u8 ppdsdr_cs; /* 0x19 */
	124	u8 ppdsdr_fbctl; /* 0x1A */
	125	u8 ppdsdr_i2c; /* 0x1B */
	126	u8 rsvd3; /* 0x1C */
	127	u8 ppdsdr_uart; /* 0x1D */
	128	u8 ppdsdr_dspi; /* 0x1E */
	129	u8 ppdsdr_timer; /* 0x1F */
	130	u8 ppdsdr_lcdctl; /* 0x20 */
	131	u8 ppdsdr_lcddatah; /* 0x21 */
	132	u8 ppdsdr_lcddatam; /* 0x22 */
	133	u8 ppdsdr_lcddatal; /* 0x23 */
	134
	135	/* Port Clear Output Data Registers */
	136	u8 pclrr_be; /* 0x24 */
	137	u8 pclrr_cs; /* 0x25 */
	138	u8 pclrr_fbctl; /* 0x26 */
	139	u8 pclrr_i2c; /* 0x27 */
	140	u8 rsvd4; /* 0x28 */
	141	u8 pclrr_uart; /* 0x29 */
	142	u8 pclrr_dspi; /* 0x2A */
	143	u8 pclrr_timer; /* 0x2B */
	144	u8 pclrr_lcdctl; /* 0x2C */
	145	u8 pclrr_lcddatah; /* 0x2D */
	146	u8 pclrr_lcddatam; /* 0x2E */
	147	u8 pclrr_lcddatal; /* 0x2F */
	148
	149	/* Pin Assignment Registers */
	150	u8 par_be; /* 0x30 */
	151	u8 par_cs; /* 0x31 */
	152	u8 par_fbctl; /* 0x32 */
	153	u8 par_i2c; /* 0x33 */
	154	u16 par_uart; /* 0x34 */
155	u8 par_dspi; /* 0x36 */
156	u8 par_timer; /* 0x37 */
157	u8 par_lcdctl; /* 0x38 */
158	u8 par_irq; /* 0x39 */
159	u16 rsvd6; /* 0x3A - 0x3B */
160	u32 par_lcdh; /* 0x3C */
161	u32 par_lcdl; /* 0x40 */
162
163	/* Mode select control registers */
164	u8 mscr_fb; /* 0x44 */
165	u8 mscr_sdram; /* 0x45 */
166
167	u16 rsvd7; /* 0x46 - 0x47 */
168	u8 dscr_dspi; /* 0x48 */
169	u8 dscr_timer; /* 0x49 */
170	u8 dscr_i2c; /* 0x4A */
171	u8 dscr_lcd; /* 0x4B */
172	u8 dscr_debug; /* 0x4C */
173	u8 dscr_clkrst; /* 0x4D */
174	u8 dscr_irq; /* 0x4E */
175	u8 dscr_uart; /* 0x4F */
176	} gpio_t;
177
178	/* SDRAM Controller (SDRAMC) */
179	typedef struct sdramc {
180	u32 sdmr; /* Mode/Extended Mode */
181	u32 sdcr; /* Control */
182	u32 sdcfg1; /* Configuration 1 */
183	u32 sdcfg2; /* Chip Select */
184	u8 resv0[0x100];
185	u32 sdcs0; /* Mode/Extended Mode */
186	u32 sdcs1; /* Mode/Extended Mode */
187	} sdramc_t;
188
189	/* Phase Locked Loop (PLL) */
190	typedef struct pll {
191	u32 pcr; /* PLL Control */
192	u32 psr; /* PLL Status */
193	} pll_t;
194
195	/* System Control Module register */
196	typedef struct scm1 {
197	u32 mpr; /* 0x00 Master Privilege */
198	u32 rsvd1[7];
199	u32 pacra; /* 0x20 */
200	u32 pacrb; /* 0x24 */
201	u32 pacrc; /* 0x28 */
202	u32 pacrd; /* 0x2C */
203	u32 rsvd2[4];
204	u32 pacre; /* 0x40 */
205	u32 pacrf; /* 0x44 */
206	u32 pacrg; /* 0x48 */
207	u32 rsvd3;
208	u32 pacri; /* 0x50 */
209	} scm1_t;
210
211	typedef struct scm2_ctrl {
212	u8 res1[3]; /* 0x00 - 0x02 */
213	u8 wcr; /* 0x03 wakeup control */
214	u16 res2; /* 0x04 - 0x05 */
215	u16 cwcr; /* 0x06 Core Watchdog Control */
216	u8 res3[3]; /* 0x08 - 0x0A */
217	u8 cwsr; /* 0x0B Core Watchdog Service */
218	u8 res4[2]; /* 0x0C - 0x0D */
219	u8 scmisr; /* 0x0F Interrupt Status */
220	u32 res5; /* 0x20 */
221	u32 bcr; /* 0x24 Burst Configuration */
222	} scm2_t;
223
224	typedef struct scm3_ctrl {
225	u32 cfadr; /* 0x00 Core Fault Address */
226	u8 res7; /* 0x04 */
227	u8 cfier; /* 0x05 Core Fault Interrupt Enable */
228	u8 cfloc; /* 0x06 Core Fault Location */
229	u8 cfatr; /* 0x07 Core Fault Attributes */
230	u32 cfdtr; /* 0x08 Core Fault Data */
231	} scm3_t;
232
233	typedef struct rtcex {
234	u32 rsvd1[3];
235	u32 gocu;
236	u32 gocl;
237	} rtcex_t;
238	#endif /* __IMMAP_5227X__ */