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efee1709 WD |
1 | /* |
2 | * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
efee1709 WD |
5 | */ |
6 | ||
7 | #include <config.h> | |
8 | #include <command.h> | |
9 | #include <mpc8xx.h> | |
10 | #include <version.h> | |
11 | ||
12 | #define CONFIG_8xx 1 /* needed for Linux kernel header files */ | |
13 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
14 | ||
15 | #include <ppc_asm.tmpl> | |
16 | #include <ppc_defs.h> | |
17 | ||
18 | #include <asm/cache.h> | |
19 | #include <asm/mmu.h> | |
20 | ||
4431283c | 21 | #if defined(CONFIG_CMD_KGDB) |
efee1709 WD |
22 | |
23 | /* | |
24 | * cache flushing routines for kgdb | |
25 | */ | |
26 | ||
27 | .globl kgdb_flush_cache_all | |
28 | kgdb_flush_cache_all: | |
29 | lis r3, IDC_INVALL@h | |
30 | mtspr DC_CST, r3 | |
31 | sync | |
32 | lis r3, IDC_INVALL@h | |
33 | mtspr IC_CST, r3 | |
34 | SYNC | |
35 | blr | |
36 | ||
37 | .globl kgdb_flush_cache_range | |
38 | kgdb_flush_cache_range: | |
6d0f6bcf | 39 | li r5,CONFIG_SYS_CACHELINE_SIZE-1 |
efee1709 WD |
40 | andc r3,r3,r5 |
41 | subf r4,r3,r4 | |
42 | add r4,r4,r5 | |
6d0f6bcf | 43 | srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT |
efee1709 WD |
44 | beqlr |
45 | mtctr r4 | |
46 | mr r6,r3 | |
47 | 1: dcbst 0,r3 | |
6d0f6bcf | 48 | addi r3,r3,CONFIG_SYS_CACHELINE_SIZE |
efee1709 WD |
49 | bdnz 1b |
50 | sync /* wait for dcbst's to get to ram */ | |
51 | mtctr r4 | |
52 | 2: icbi 0,r6 | |
6d0f6bcf | 53 | addi r6,r6,CONFIG_SYS_CACHELINE_SIZE |
efee1709 WD |
54 | bdnz 2b |
55 | SYNC | |
56 | blr | |
57 | ||
068b60a0 | 58 | #endif |