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0442ed86 WD |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> | |
3cb86f3e | 5 | * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering |
c821b5f1 GE |
6 | * Copyright (c) 2008 Nuovation System Designs, LLC |
7 | * Grant Erickson <gerickson@nuovations.com> | |
0442ed86 WD |
8 | * |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
83b4cfa3 | 27 | /*------------------------------------------------------------------------------+ |
31773496 JB |
28 | * This source code is dual-licensed. You may use it under the terms of the |
29 | * GNU General Public License version 2, or under the license below. | |
83b4cfa3 WD |
30 | * |
31 | * This source code has been made available to you by IBM on an AS-IS | |
32 | * basis. Anyone receiving this source is licensed under IBM | |
33 | * copyrights to use it in any way he or she deems fit, including | |
34 | * copying it, modifying it, compiling it, and redistributing it either | |
35 | * with or without modifications. No license under IBM patents or | |
36 | * patent applications is to be implied by the copyright license. | |
37 | * | |
38 | * Any user of this software should understand that IBM cannot provide | |
39 | * technical support for this software and will not be responsible for | |
40 | * any consequences resulting from the use of this software. | |
41 | * | |
42 | * Any person who transfers this source code or any derivative work | |
43 | * must include the IBM copyright notice, this paragraph, and the | |
44 | * preceding two paragraphs in the transferred software. | |
45 | * | |
46 | * COPYRIGHT I B M CORPORATION 1995 | |
47 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
48 | *------------------------------------------------------------------------------- | |
49 | */ | |
0442ed86 | 50 | |
f7b548ad SR |
51 | /* |
52 | * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards | |
0442ed86 | 53 | * |
f7b548ad SR |
54 | * The following description only applies to the NOR flash style booting. |
55 | * NAND booting is different. For more details about NAND booting on 4xx | |
56 | * take a look at doc/README.nand-boot-ppc440. | |
0442ed86 | 57 | * |
f7b548ad SR |
58 | * The CPU starts at address 0xfffffffc (last word in the address space). |
59 | * The U-Boot image therefore has to be located in the "upper" area of the | |
60 | * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for | |
61 | * the boot chip-select (CS0) is quite big and covers this area. On the | |
62 | * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will | |
63 | * reconfigure this CS0 (and other chip-selects as well when configured | |
64 | * this way) in the boot process to the "correct" values matching the | |
65 | * board layout. | |
0442ed86 | 66 | */ |
f7b548ad | 67 | |
25ddd1fb | 68 | #include <asm-offsets.h> |
0442ed86 | 69 | #include <config.h> |
b36df561 | 70 | #include <asm/ppc4xx.h> |
561858ee | 71 | #include <timestamp.h> |
0442ed86 WD |
72 | #include <version.h> |
73 | ||
74 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
75 | ||
76 | #include <ppc_asm.tmpl> | |
77 | #include <ppc_defs.h> | |
78 | ||
79 | #include <asm/cache.h> | |
80 | #include <asm/mmu.h> | |
b14ca4b6 | 81 | #include <asm/ppc4xx-isram.h> |
0442ed86 WD |
82 | |
83 | #ifndef CONFIG_IDENT_STRING | |
84 | #define CONFIG_IDENT_STRING "" | |
85 | #endif | |
86 | ||
6d0f6bcf JCPV |
87 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
88 | # if (CONFIG_SYS_INIT_DCACHE_CS == 0) | |
d1c3b275 SR |
89 | # define PBxAP PB1AP |
90 | # define PBxCR PB0CR | |
6d0f6bcf JCPV |
91 | # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
92 | # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP | |
93 | # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR | |
c821b5f1 | 94 | # endif |
0442ed86 | 95 | # endif |
6d0f6bcf | 96 | # if (CONFIG_SYS_INIT_DCACHE_CS == 1) |
d1c3b275 SR |
97 | # define PBxAP PB1AP |
98 | # define PBxCR PB1CR | |
6d0f6bcf JCPV |
99 | # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) |
100 | # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP | |
101 | # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR | |
c821b5f1 | 102 | # endif |
0442ed86 | 103 | # endif |
6d0f6bcf | 104 | # if (CONFIG_SYS_INIT_DCACHE_CS == 2) |
d1c3b275 SR |
105 | # define PBxAP PB2AP |
106 | # define PBxCR PB2CR | |
6d0f6bcf JCPV |
107 | # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) |
108 | # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP | |
109 | # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR | |
c821b5f1 | 110 | # endif |
0442ed86 | 111 | # endif |
6d0f6bcf | 112 | # if (CONFIG_SYS_INIT_DCACHE_CS == 3) |
d1c3b275 SR |
113 | # define PBxAP PB3AP |
114 | # define PBxCR PB3CR | |
6d0f6bcf JCPV |
115 | # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) |
116 | # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP | |
117 | # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR | |
c821b5f1 | 118 | # endif |
0442ed86 | 119 | # endif |
6d0f6bcf | 120 | # if (CONFIG_SYS_INIT_DCACHE_CS == 4) |
d1c3b275 SR |
121 | # define PBxAP PB4AP |
122 | # define PBxCR PB4CR | |
6d0f6bcf JCPV |
123 | # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) |
124 | # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP | |
125 | # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR | |
c821b5f1 | 126 | # endif |
0442ed86 | 127 | # endif |
6d0f6bcf | 128 | # if (CONFIG_SYS_INIT_DCACHE_CS == 5) |
d1c3b275 SR |
129 | # define PBxAP PB5AP |
130 | # define PBxCR PB5CR | |
6d0f6bcf JCPV |
131 | # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) |
132 | # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP | |
133 | # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR | |
c821b5f1 | 134 | # endif |
0442ed86 | 135 | # endif |
6d0f6bcf | 136 | # if (CONFIG_SYS_INIT_DCACHE_CS == 6) |
d1c3b275 SR |
137 | # define PBxAP PB6AP |
138 | # define PBxCR PB6CR | |
6d0f6bcf JCPV |
139 | # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) |
140 | # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP | |
141 | # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR | |
c821b5f1 | 142 | # endif |
0442ed86 | 143 | # endif |
6d0f6bcf | 144 | # if (CONFIG_SYS_INIT_DCACHE_CS == 7) |
d1c3b275 SR |
145 | # define PBxAP PB7AP |
146 | # define PBxCR PB7CR | |
6d0f6bcf JCPV |
147 | # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) |
148 | # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP | |
149 | # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR | |
c821b5f1 GE |
150 | # endif |
151 | # endif | |
152 | # ifndef PBxAP_VAL | |
153 | # define PBxAP_VAL 0 | |
154 | # endif | |
155 | # ifndef PBxCR_VAL | |
156 | # define PBxCR_VAL 0 | |
157 | # endif | |
158 | /* | |
6d0f6bcf | 159 | * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB |
c821b5f1 GE |
160 | * used as temporary stack pointer for the primordial stack |
161 | */ | |
6d0f6bcf JCPV |
162 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR |
163 | # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ | |
c821b5f1 GE |
164 | EBC_BXAP_TWT_ENCODE(7) | \ |
165 | EBC_BXAP_BCE_DISABLE | \ | |
166 | EBC_BXAP_BCT_2TRANS | \ | |
167 | EBC_BXAP_CSN_ENCODE(0) | \ | |
168 | EBC_BXAP_OEN_ENCODE(0) | \ | |
169 | EBC_BXAP_WBN_ENCODE(0) | \ | |
170 | EBC_BXAP_WBF_ENCODE(0) | \ | |
171 | EBC_BXAP_TH_ENCODE(2) | \ | |
172 | EBC_BXAP_RE_DISABLED | \ | |
173 | EBC_BXAP_SOR_NONDELAYED | \ | |
174 | EBC_BXAP_BEM_WRITEONLY | \ | |
175 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf JCPV |
176 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ |
177 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR | |
178 | # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ | |
c821b5f1 GE |
179 | EBC_BXCR_BS_64MB | \ |
180 | EBC_BXCR_BU_RW | \ | |
181 | EBC_BXCR_BW_16BIT) | |
6d0f6bcf JCPV |
182 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ |
183 | # ifndef CONFIG_SYS_INIT_RAM_PATTERN | |
184 | # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD | |
0442ed86 | 185 | # endif |
6d0f6bcf | 186 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 187 | |
553f0982 WD |
188 | #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10))) |
189 | #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE! | |
28d77d96 SR |
190 | #endif |
191 | ||
c821b5f1 GE |
192 | /* |
193 | * Unless otherwise overriden, enable two 128MB cachable instruction regions | |
6d0f6bcf JCPV |
194 | * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering |
195 | * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. | |
c821b5f1 | 196 | */ |
6d0f6bcf | 197 | #if !defined(CONFIG_SYS_FLASH_BASE) |
64852d09 | 198 | /* If not already defined, set it to the "last" 128MByte region */ |
6d0f6bcf | 199 | # define CONFIG_SYS_FLASH_BASE 0xf8000000 |
64852d09 | 200 | #endif |
6d0f6bcf JCPV |
201 | #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) |
202 | # define CONFIG_SYS_ICACHE_SACR_VALUE \ | |
203 | (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ | |
204 | PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ | |
205 | PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) | |
206 | #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ | |
207 | ||
208 | #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) | |
209 | # define CONFIG_SYS_DCACHE_SACR_VALUE \ | |
c821b5f1 | 210 | (0x00000000) |
6d0f6bcf | 211 | #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ |
c821b5f1 | 212 | |
4978e605 SR |
213 | #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH) |
214 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */ | |
215 | #endif | |
216 | ||
83b4cfa3 | 217 | #define function_prolog(func_name) .text; \ |
cf959c7d SR |
218 | .align 2; \ |
219 | .globl func_name; \ | |
220 | func_name: | |
83b4cfa3 | 221 | #define function_epilog(func_name) .type func_name,@function; \ |
cf959c7d SR |
222 | .size func_name,.-func_name |
223 | ||
0442ed86 WD |
224 | /* We don't want the MMU yet. |
225 | */ | |
226 | #undef MSR_KERNEL | |
227 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ | |
228 | ||
229 | ||
230 | .extern ext_bus_cntlr_init | |
887e2ec9 SR |
231 | #ifdef CONFIG_NAND_U_BOOT |
232 | .extern reconfig_tlb0 | |
233 | #endif | |
0442ed86 WD |
234 | |
235 | /* | |
236 | * Set up GOT: Global Offset Table | |
237 | * | |
0f8aa159 | 238 | * Use r12 to access the GOT |
0442ed86 | 239 | */ |
887e2ec9 | 240 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 WD |
241 | START_GOT |
242 | GOT_ENTRY(_GOT2_TABLE_) | |
243 | GOT_ENTRY(_FIXUP_TABLE_) | |
244 | ||
245 | GOT_ENTRY(_start) | |
246 | GOT_ENTRY(_start_of_vectors) | |
247 | GOT_ENTRY(_end_of_vectors) | |
248 | GOT_ENTRY(transfer_to_handler) | |
249 | ||
3b57fe0a | 250 | GOT_ENTRY(__init_end) |
44c6e659 | 251 | GOT_ENTRY(__bss_end__) |
5d232d0e | 252 | GOT_ENTRY(__bss_start) |
0442ed86 | 253 | END_GOT |
887e2ec9 SR |
254 | #endif /* CONFIG_NAND_SPL */ |
255 | ||
256 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
257 | /* | |
258 | * NAND U-Boot image is started from offset 0 | |
259 | */ | |
260 | .text | |
c440bfe6 | 261 | #if defined(CONFIG_440) |
887e2ec9 | 262 | bl reconfig_tlb0 |
c440bfe6 | 263 | #endif |
887e2ec9 | 264 | GET_GOT |
39768f77 JT |
265 | #if defined(__pic__) && __pic__ == 1 |
266 | /* Needed for upcoming -msingle-pic-base */ | |
267 | bl _GLOBAL_OFFSET_TABLE_@local-4 | |
268 | mflr r30 | |
269 | #endif | |
887e2ec9 SR |
270 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
271 | bl board_init_f | |
52ebd9c1 | 272 | /* NOTREACHED - board_init_f() does not return */ |
887e2ec9 | 273 | #endif |
0442ed86 | 274 | |
d20b9991 | 275 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) |
d873133f SR |
276 | /* |
277 | * 4xx RAM-booting U-Boot image is started from offset 0 | |
278 | */ | |
279 | .text | |
280 | bl _start_440 | |
281 | #endif | |
282 | ||
0442ed86 WD |
283 | /* |
284 | * 440 Startup -- on reset only the top 4k of the effective | |
285 | * address space is mapped in by an entry in the instruction | |
286 | * and data shadow TLB. The .bootpg section is located in the | |
287 | * top 4k & does only what's necessary to map in the the rest | |
288 | * of the boot rom. Once the boot rom is mapped in we can | |
289 | * proceed with normal startup. | |
290 | * | |
291 | * NOTE: CS0 only covers the top 2MB of the effective address | |
292 | * space after reset. | |
293 | */ | |
294 | ||
295 | #if defined(CONFIG_440) | |
887e2ec9 | 296 | #if !defined(CONFIG_NAND_SPL) |
0442ed86 | 297 | .section .bootpg,"ax" |
887e2ec9 | 298 | #endif |
0442ed86 WD |
299 | .globl _start_440 |
300 | ||
301 | /**************************************************************************/ | |
302 | _start_440: | |
511d0c72 WD |
303 | /*--------------------------------------------------------------------+ |
304 | | 440EPX BUP Change - Hardware team request | |
305 | +--------------------------------------------------------------------*/ | |
887e2ec9 SR |
306 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
307 | sync | |
308 | nop | |
309 | nop | |
310 | #endif | |
6c5879f3 MB |
311 | /*----------------------------------------------------------------+ |
312 | | Core bug fix. Clear the esr | |
313 | +-----------------------------------------------------------------*/ | |
edd6cf20 | 314 | li r0,0 |
58ea142f | 315 | mtspr SPRN_ESR,r0 |
0442ed86 WD |
316 | /*----------------------------------------------------------------*/ |
317 | /* Clear and set up some registers. */ | |
318 | /*----------------------------------------------------------------*/ | |
f901a83b WD |
319 | iccci r0,r0 /* NOTE: operands not used for 440 */ |
320 | dccci r0,r0 /* NOTE: operands not used for 440 */ | |
0442ed86 WD |
321 | sync |
322 | li r0,0 | |
58ea142f MF |
323 | mtspr SPRN_SRR0,r0 |
324 | mtspr SPRN_SRR1,r0 | |
325 | mtspr SPRN_CSRR0,r0 | |
326 | mtspr SPRN_CSRR1,r0 | |
887e2ec9 SR |
327 | /* NOTE: 440GX adds machine check status regs */ |
328 | #if defined(CONFIG_440) && !defined(CONFIG_440GP) | |
58ea142f MF |
329 | mtspr SPRN_MCSRR0,r0 |
330 | mtspr SPRN_MCSRR1,r0 | |
331 | mfspr r1,SPRN_MCSR | |
332 | mtspr SPRN_MCSR,r1 | |
ba56f625 | 333 | #endif |
20532833 SR |
334 | |
335 | /*----------------------------------------------------------------*/ | |
336 | /* CCR0 init */ | |
337 | /*----------------------------------------------------------------*/ | |
338 | /* Disable store gathering & broadcast, guarantee inst/data | |
339 | * cache block touch, force load/store alignment | |
340 | * (see errata 1.12: 440_33) | |
341 | */ | |
342 | lis r1,0x0030 /* store gathering & broadcast disable */ | |
343 | ori r1,r1,0x6000 /* cache touch */ | |
58ea142f | 344 | mtspr SPRN_CCR0,r1 |
20532833 | 345 | |
0442ed86 WD |
346 | /*----------------------------------------------------------------*/ |
347 | /* Initialize debug */ | |
348 | /*----------------------------------------------------------------*/ | |
58ea142f | 349 | mfspr r1,SPRN_DBCR0 |
887e2ec9 SR |
350 | andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ |
351 | bne skip_debug_init /* if set, don't clear debug register */ | |
ad876fff VG |
352 | mfspr r1,SPRN_CCR0 |
353 | ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ | |
354 | mtspr SPRN_CCR0,r1 | |
58ea142f MF |
355 | mtspr SPRN_DBCR0,r0 |
356 | mtspr SPRN_DBCR1,r0 | |
357 | mtspr SPRN_DBCR2,r0 | |
358 | mtspr SPRN_IAC1,r0 | |
359 | mtspr SPRN_IAC2,r0 | |
360 | mtspr SPRN_IAC3,r0 | |
361 | mtspr SPRN_DAC1,r0 | |
362 | mtspr SPRN_DAC2,r0 | |
363 | mtspr SPRN_DVC1,r0 | |
364 | mtspr SPRN_DVC2,r0 | |
365 | ||
366 | mfspr r1,SPRN_DBSR | |
367 | mtspr SPRN_DBSR,r1 /* Clear all valid bits */ | |
887e2ec9 | 368 | skip_debug_init: |
0442ed86 | 369 | |
6c5879f3 MB |
370 | #if defined (CONFIG_440SPE) |
371 | /*----------------------------------------------------------------+ | |
372 | | Initialize Core Configuration Reg1. | |
373 | | a. ICDPEI: Record even parity. Normal operation. | |
374 | | b. ICTPEI: Record even parity. Normal operation. | |
375 | | c. DCTPEI: Record even parity. Normal operation. | |
376 | | d. DCDPEI: Record even parity. Normal operation. | |
377 | | e. DCUPEI: Record even parity. Normal operation. | |
378 | | f. DCMPEI: Record even parity. Normal operation. | |
379 | | g. FCOM: Normal operation | |
380 | | h. MMUPEI: Record even parity. Normal operation. | |
381 | | i. FFF: Flush only as much data as necessary. | |
edd6cf20 | 382 | | j. TCS: Timebase increments from CPU clock. |
6c5879f3 | 383 | +-----------------------------------------------------------------*/ |
edd6cf20 | 384 | li r0,0 |
58ea142f | 385 | mtspr SPRN_CCR1, r0 |
6c5879f3 MB |
386 | |
387 | /*----------------------------------------------------------------+ | |
388 | | Reset the timebase. | |
389 | | The previous write to CCR1 sets the timebase source. | |
390 | +-----------------------------------------------------------------*/ | |
58ea142f MF |
391 | mtspr SPRN_TBWL, r0 |
392 | mtspr SPRN_TBWU, r0 | |
6c5879f3 MB |
393 | #endif |
394 | ||
0442ed86 WD |
395 | /*----------------------------------------------------------------*/ |
396 | /* Setup interrupt vectors */ | |
397 | /*----------------------------------------------------------------*/ | |
58ea142f | 398 | mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ |
f901a83b | 399 | li r1,0x0100 |
58ea142f | 400 | mtspr SPRN_IVOR0,r1 /* Critical input */ |
f901a83b | 401 | li r1,0x0200 |
58ea142f | 402 | mtspr SPRN_IVOR1,r1 /* Machine check */ |
f901a83b | 403 | li r1,0x0300 |
58ea142f | 404 | mtspr SPRN_IVOR2,r1 /* Data storage */ |
f901a83b | 405 | li r1,0x0400 |
58ea142f | 406 | mtspr SPRN_IVOR3,r1 /* Instruction storage */ |
0442ed86 | 407 | li r1,0x0500 |
58ea142f | 408 | mtspr SPRN_IVOR4,r1 /* External interrupt */ |
0442ed86 | 409 | li r1,0x0600 |
58ea142f | 410 | mtspr SPRN_IVOR5,r1 /* Alignment */ |
0442ed86 | 411 | li r1,0x0700 |
58ea142f | 412 | mtspr SPRN_IVOR6,r1 /* Program check */ |
0442ed86 | 413 | li r1,0x0800 |
58ea142f | 414 | mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ |
0442ed86 | 415 | li r1,0x0c00 |
58ea142f | 416 | mtspr SPRN_IVOR8,r1 /* System call */ |
efa35cf1 | 417 | li r1,0x0a00 |
58ea142f | 418 | mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ |
efa35cf1 | 419 | li r1,0x0900 |
58ea142f | 420 | mtspr SPRN_IVOR10,r1 /* Decrementer */ |
0442ed86 | 421 | li r1,0x1300 |
58ea142f | 422 | mtspr SPRN_IVOR13,r1 /* Data TLB error */ |
efa35cf1 | 423 | li r1,0x1400 |
58ea142f | 424 | mtspr SPRN_IVOR14,r1 /* Instr TLB error */ |
0442ed86 | 425 | li r1,0x2000 |
58ea142f | 426 | mtspr SPRN_IVOR15,r1 /* Debug */ |
0442ed86 WD |
427 | |
428 | /*----------------------------------------------------------------*/ | |
429 | /* Configure cache regions */ | |
430 | /*----------------------------------------------------------------*/ | |
58ea142f MF |
431 | mtspr SPRN_INV0,r0 |
432 | mtspr SPRN_INV1,r0 | |
433 | mtspr SPRN_INV2,r0 | |
434 | mtspr SPRN_INV3,r0 | |
435 | mtspr SPRN_DNV0,r0 | |
436 | mtspr SPRN_DNV1,r0 | |
437 | mtspr SPRN_DNV2,r0 | |
438 | mtspr SPRN_DNV3,r0 | |
439 | mtspr SPRN_ITV0,r0 | |
440 | mtspr SPRN_ITV1,r0 | |
441 | mtspr SPRN_ITV2,r0 | |
442 | mtspr SPRN_ITV3,r0 | |
443 | mtspr SPRN_DTV0,r0 | |
444 | mtspr SPRN_DTV1,r0 | |
445 | mtspr SPRN_DTV2,r0 | |
446 | mtspr SPRN_DTV3,r0 | |
0442ed86 WD |
447 | |
448 | /*----------------------------------------------------------------*/ | |
449 | /* Cache victim limits */ | |
450 | /*----------------------------------------------------------------*/ | |
451 | /* floors 0, ceiling max to use the entire cache -- nothing locked | |
452 | */ | |
453 | lis r1,0x0001 | |
454 | ori r1,r1,0xf800 | |
58ea142f MF |
455 | mtspr SPRN_IVLIM,r1 |
456 | mtspr SPRN_DVLIM,r1 | |
0442ed86 | 457 | |
6c5879f3 MB |
458 | /*----------------------------------------------------------------+ |
459 | |Initialize MMUCR[STID] = 0. | |
460 | +-----------------------------------------------------------------*/ | |
58ea142f | 461 | mfspr r0,SPRN_MMUCR |
6c5879f3 MB |
462 | addis r1,0,0xFFFF |
463 | ori r1,r1,0xFF00 | |
464 | and r0,r0,r1 | |
58ea142f | 465 | mtspr SPRN_MMUCR,r0 |
6c5879f3 | 466 | |
0442ed86 WD |
467 | /*----------------------------------------------------------------*/ |
468 | /* Clear all TLB entries -- TID = 0, TS = 0 */ | |
469 | /*----------------------------------------------------------------*/ | |
6c5879f3 | 470 | addis r0,0,0x0000 |
0a371ca0 | 471 | #ifdef CONFIG_SYS_RAMBOOT |
d873133f | 472 | li r4,0 /* Start with TLB #0 */ |
0a371ca0 SR |
473 | #else |
474 | li r4,1 /* Start with TLB #1 */ | |
475 | #endif | |
476 | li r1,64 /* 64 TLB entries */ | |
477 | sub r1,r1,r4 /* calculate last TLB # */ | |
478 | mtctr r1 | |
d873133f SR |
479 | rsttlb: |
480 | #ifdef CONFIG_SYS_RAMBOOT | |
481 | tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ | |
482 | rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ | |
483 | beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ | |
484 | #endif | |
485 | tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ | |
486 | tlbwe r0,r4,1 | |
487 | tlbwe r0,r4,2 | |
488 | tlbnxt: addi r4,r4,1 /* Next TLB */ | |
6c5879f3 | 489 | bdnz rsttlb |
0442ed86 WD |
490 | |
491 | /*----------------------------------------------------------------*/ | |
492 | /* TLB entry setup -- step thru tlbtab */ | |
493 | /*----------------------------------------------------------------*/ | |
2a72e9ed | 494 | #if defined(CONFIG_440SPE_REVA) |
692519b1 RJ |
495 | /*----------------------------------------------------------------*/ |
496 | /* We have different TLB tables for revA and rev B of 440SPe */ | |
497 | /*----------------------------------------------------------------*/ | |
498 | mfspr r1, PVR | |
499 | lis r0,0x5342 | |
500 | ori r0,r0,0x1891 | |
501 | cmpw r7,r1,r0 | |
502 | bne r7,..revA | |
503 | bl tlbtabB | |
504 | b ..goon | |
505 | ..revA: | |
506 | bl tlbtabA | |
507 | ..goon: | |
508 | #else | |
0442ed86 | 509 | bl tlbtab /* Get tlbtab pointer */ |
692519b1 | 510 | #endif |
0442ed86 WD |
511 | mr r5,r0 |
512 | li r1,0x003f /* 64 TLB entries max */ | |
513 | mtctr r1 | |
514 | li r4,0 /* TLB # */ | |
515 | ||
516 | addi r5,r5,-4 | |
d873133f SR |
517 | 1: |
518 | #ifdef CONFIG_SYS_RAMBOOT | |
519 | tlbre r3,r4,0 /* Read contents from TLB word #0 */ | |
520 | rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ | |
521 | bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ | |
522 | #endif | |
523 | lwzu r0,4(r5) | |
0442ed86 WD |
524 | cmpwi r0,0 |
525 | beq 2f /* 0 marks end */ | |
526 | lwzu r1,4(r5) | |
527 | lwzu r2,4(r5) | |
528 | tlbwe r0,r4,0 /* TLB Word 0 */ | |
529 | tlbwe r1,r4,1 /* TLB Word 1 */ | |
530 | tlbwe r2,r4,2 /* TLB Word 2 */ | |
d873133f | 531 | tlbnx2: addi r4,r4,1 /* Next TLB */ |
0442ed86 WD |
532 | bdnz 1b |
533 | ||
534 | /*----------------------------------------------------------------*/ | |
535 | /* Continue from 'normal' start */ | |
536 | /*----------------------------------------------------------------*/ | |
887e2ec9 | 537 | 2: |
887e2ec9 | 538 | bl 3f |
0442ed86 WD |
539 | b _start |
540 | ||
541 | 3: li r0,0 | |
58ea142f | 542 | mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ |
0442ed86 | 543 | mflr r1 |
58ea142f | 544 | mtspr SPRN_SRR0,r1 |
0442ed86 | 545 | rfi |
b867d705 | 546 | #endif /* CONFIG_440 */ |
0442ed86 WD |
547 | |
548 | /* | |
549 | * r3 - 1st arg to board_init(): IMMP pointer | |
550 | * r4 - 2nd arg to board_init(): boot flag | |
551 | */ | |
887e2ec9 | 552 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
553 | .text |
554 | .long 0x27051956 /* U-Boot Magic Number */ | |
555 | .globl version_string | |
556 | version_string: | |
557 | .ascii U_BOOT_VERSION | |
561858ee | 558 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
0442ed86 WD |
559 | .ascii CONFIG_IDENT_STRING, "\0" |
560 | ||
0442ed86 | 561 | . = EXC_OFF_SYS_RESET |
efa35cf1 GB |
562 | .globl _start_of_vectors |
563 | _start_of_vectors: | |
564 | ||
565 | /* Critical input. */ | |
566 | CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) | |
567 | ||
568 | #ifdef CONFIG_440 | |
569 | /* Machine check */ | |
83b4cfa3 | 570 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 | 571 | #else |
83b4cfa3 | 572 | CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 GB |
573 | #endif /* CONFIG_440 */ |
574 | ||
575 | /* Data Storage exception. */ | |
576 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
577 | ||
578 | /* Instruction Storage exception. */ | |
579 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
580 | ||
581 | /* External Interrupt exception. */ | |
582 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
583 | ||
584 | /* Alignment exception. */ | |
585 | . = 0x600 | |
586 | Alignment: | |
587 | EXCEPTION_PROLOG(SRR0, SRR1) | |
588 | mfspr r4,DAR | |
589 | stw r4,_DAR(r21) | |
590 | mfspr r5,DSISR | |
591 | stw r5,_DSISR(r21) | |
592 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 | 593 | EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) |
efa35cf1 GB |
594 | |
595 | /* Program check exception */ | |
596 | . = 0x700 | |
597 | ProgramCheck: | |
598 | EXCEPTION_PROLOG(SRR0, SRR1) | |
599 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 JT |
600 | EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, |
601 | MSR_KERNEL, COPY_EE) | |
efa35cf1 GB |
602 | |
603 | #ifdef CONFIG_440 | |
604 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
605 | STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) | |
606 | STD_EXCEPTION(0xa00, APU, UnknownException) | |
df8a24cd | 607 | #endif |
efa35cf1 GB |
608 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) |
609 | ||
610 | #ifdef CONFIG_440 | |
611 | STD_EXCEPTION(0x1300, DataTLBError, UnknownException) | |
612 | STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) | |
613 | #else | |
614 | STD_EXCEPTION(0x1000, PIT, DecrementerPITException) | |
615 | STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) | |
616 | STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) | |
617 | #endif | |
618 | CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) | |
619 | ||
620 | .globl _end_of_vectors | |
621 | _end_of_vectors: | |
622 | . = _START_OFFSET | |
887e2ec9 | 623 | #endif |
0442ed86 WD |
624 | .globl _start |
625 | _start: | |
626 | ||
627 | /*****************************************************************************/ | |
628 | #if defined(CONFIG_440) | |
629 | ||
630 | /*----------------------------------------------------------------*/ | |
631 | /* Clear and set up some registers. */ | |
632 | /*----------------------------------------------------------------*/ | |
633 | li r0,0x0000 | |
634 | lis r1,0xffff | |
58ea142f MF |
635 | mtspr SPRN_DEC,r0 /* prevent dec exceptions */ |
636 | mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ | |
637 | mtspr SPRN_TBWU,r0 | |
638 | mtspr SPRN_TSR,r1 /* clear all timer exception status */ | |
639 | mtspr SPRN_TCR,r0 /* disable all */ | |
640 | mtspr SPRN_ESR,r0 /* clear exception syndrome register */ | |
0442ed86 | 641 | mtxer r0 /* clear integer exception register */ |
0442ed86 WD |
642 | |
643 | /*----------------------------------------------------------------*/ | |
644 | /* Debug setup -- some (not very good) ice's need an event*/ | |
6d0f6bcf | 645 | /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ |
0442ed86 WD |
646 | /* value you need in this case 0x8cff 0000 should do the trick */ |
647 | /*----------------------------------------------------------------*/ | |
6d0f6bcf | 648 | #if defined(CONFIG_SYS_INIT_DBCR) |
0442ed86 WD |
649 | lis r1,0xffff |
650 | ori r1,r1,0xffff | |
58ea142f | 651 | mtspr SPRN_DBSR,r1 /* Clear all status bits */ |
6d0f6bcf JCPV |
652 | lis r0,CONFIG_SYS_INIT_DBCR@h |
653 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
58ea142f | 654 | mtspr SPRN_DBCR0,r0 |
0442ed86 WD |
655 | isync |
656 | #endif | |
657 | ||
658 | /*----------------------------------------------------------------*/ | |
659 | /* Setup the internal SRAM */ | |
660 | /*----------------------------------------------------------------*/ | |
661 | li r0,0 | |
887e2ec9 | 662 | |
6d0f6bcf | 663 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
c157d8e2 | 664 | /* Clear Dcache to use as RAM */ |
6d0f6bcf JCPV |
665 | addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
666 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
553f0982 WD |
667 | addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h |
668 | ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l | |
c157d8e2 | 669 | rlwinm. r5,r4,0,27,31 |
f901a83b WD |
670 | rlwinm r5,r4,27,5,31 |
671 | beq ..d_ran | |
672 | addi r5,r5,0x0001 | |
c157d8e2 | 673 | ..d_ran: |
f901a83b | 674 | mtctr r5 |
c157d8e2 | 675 | ..d_ag: |
f901a83b WD |
676 | dcbz r0,r3 |
677 | addi r3,r3,32 | |
678 | bdnz ..d_ag | |
e02c521d SR |
679 | |
680 | /* | |
681 | * Lock the init-ram/stack in d-cache, so that other regions | |
682 | * may use d-cache as well | |
683 | * Note, that this current implementation locks exactly 4k | |
684 | * of d-cache, so please make sure that you don't define a | |
685 | * bigger init-ram area. Take a look at the lwmon5 440EPx | |
686 | * implementation as a reference. | |
687 | */ | |
688 | msync | |
689 | isync | |
690 | /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ | |
691 | lis r1,0x0201 | |
692 | ori r1,r1,0xf808 | |
58ea142f | 693 | mtspr SPRN_DVLIM,r1 |
e02c521d SR |
694 | lis r1,0x0808 |
695 | ori r1,r1,0x0808 | |
58ea142f MF |
696 | mtspr SPRN_DNV0,r1 |
697 | mtspr SPRN_DNV1,r1 | |
698 | mtspr SPRN_DNV2,r1 | |
699 | mtspr SPRN_DNV3,r1 | |
700 | mtspr SPRN_DTV0,r1 | |
701 | mtspr SPRN_DTV1,r1 | |
702 | mtspr SPRN_DTV2,r1 | |
703 | mtspr SPRN_DTV3,r1 | |
e02c521d SR |
704 | msync |
705 | isync | |
6d0f6bcf | 706 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
887e2ec9 SR |
707 | |
708 | /* 440EP & 440GR are only 440er PPC's without internal SRAM */ | |
709 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) | |
710 | /* not all PPC's have internal SRAM usable as L2-cache */ | |
2801b2d2 SR |
711 | #if defined(CONFIG_440GX) || \ |
712 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
7d307936 | 713 | defined(CONFIG_460SX) |
b14ca4b6 | 714 | mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ |
1b8fec13 TM |
715 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
716 | defined(CONFIG_APM821XX) | |
ddf45cc7 DM |
717 | lis r1, 0x0000 |
718 | ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ | |
719 | mtdcr L2_CACHE_CFG,r1 | |
ba56f625 | 720 | #endif |
0442ed86 | 721 | |
887e2ec9 | 722 | lis r2,0x7fff |
0442ed86 | 723 | ori r2,r2,0xffff |
b14ca4b6 | 724 | mfdcr r1,ISRAM0_DPC |
0442ed86 | 725 | and r1,r1,r2 /* Disable parity check */ |
b14ca4b6 DM |
726 | mtdcr ISRAM0_DPC,r1 |
727 | mfdcr r1,ISRAM0_PMEG | |
887e2ec9 | 728 | and r1,r1,r2 /* Disable pwr mgmt */ |
b14ca4b6 | 729 | mtdcr ISRAM0_PMEG,r1 |
0442ed86 WD |
730 | |
731 | lis r1,0x8000 /* BAS = 8000_0000 */ | |
6e7fb6ea | 732 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
ba56f625 | 733 | ori r1,r1,0x0980 /* first 64k */ |
b14ca4b6 | 734 | mtdcr ISRAM0_SB0CR,r1 |
ba56f625 WD |
735 | lis r1,0x8001 |
736 | ori r1,r1,0x0980 /* second 64k */ | |
b14ca4b6 | 737 | mtdcr ISRAM0_SB1CR,r1 |
ba56f625 WD |
738 | lis r1, 0x8002 |
739 | ori r1,r1, 0x0980 /* third 64k */ | |
b14ca4b6 | 740 | mtdcr ISRAM0_SB2CR,r1 |
ba56f625 WD |
741 | lis r1, 0x8003 |
742 | ori r1,r1, 0x0980 /* fourth 64k */ | |
b14ca4b6 | 743 | mtdcr ISRAM0_SB3CR,r1 |
1b8fec13 TM |
744 | #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ |
745 | defined(CONFIG_460GT) || defined(CONFIG_APM821XX) | |
ddf45cc7 | 746 | lis r1,0x0000 /* BAS = X_0000_0000 */ |
6c5879f3 | 747 | ori r1,r1,0x0984 /* first 64k */ |
b14ca4b6 | 748 | mtdcr ISRAM0_SB0CR,r1 |
6c5879f3 MB |
749 | lis r1,0x0001 |
750 | ori r1,r1,0x0984 /* second 64k */ | |
b14ca4b6 | 751 | mtdcr ISRAM0_SB1CR,r1 |
6c5879f3 MB |
752 | lis r1, 0x0002 |
753 | ori r1,r1, 0x0984 /* third 64k */ | |
b14ca4b6 | 754 | mtdcr ISRAM0_SB2CR,r1 |
6c5879f3 MB |
755 | lis r1, 0x0003 |
756 | ori r1,r1, 0x0984 /* fourth 64k */ | |
b14ca4b6 | 757 | mtdcr ISRAM0_SB3CR,r1 |
1b8fec13 TM |
758 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
759 | defined(CONFIG_APM821XX) | |
ddf45cc7 DM |
760 | lis r2,0x7fff |
761 | ori r2,r2,0xffff | |
762 | mfdcr r1,ISRAM1_DPC | |
763 | and r1,r1,r2 /* Disable parity check */ | |
455ae7e8 | 764 | mtdcr ISRAM1_DPC,r1 |
ddf45cc7 DM |
765 | mfdcr r1,ISRAM1_PMEG |
766 | and r1,r1,r2 /* Disable pwr mgmt */ | |
767 | mtdcr ISRAM1_PMEG,r1 | |
768 | ||
769 | lis r1,0x0004 /* BAS = 4_0004_0000 */ | |
1b8fec13 | 770 | ori r1,r1,ISRAM1_SIZE /* ocm size */ |
ddf45cc7 DM |
771 | mtdcr ISRAM1_SB0CR,r1 |
772 | #endif | |
7d307936 FK |
773 | #elif defined(CONFIG_460SX) |
774 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
775 | ori r1,r1,0x0B84 /* first 128k */ | |
b14ca4b6 | 776 | mtdcr ISRAM0_SB0CR,r1 |
7d307936 FK |
777 | lis r1,0x0001 |
778 | ori r1,r1,0x0B84 /* second 128k */ | |
b14ca4b6 | 779 | mtdcr ISRAM0_SB1CR,r1 |
7d307936 FK |
780 | lis r1, 0x0002 |
781 | ori r1,r1, 0x0B84 /* third 128k */ | |
b14ca4b6 | 782 | mtdcr ISRAM0_SB2CR,r1 |
7d307936 FK |
783 | lis r1, 0x0003 |
784 | ori r1,r1, 0x0B84 /* fourth 128k */ | |
b14ca4b6 | 785 | mtdcr ISRAM0_SB3CR,r1 |
887e2ec9 | 786 | #elif defined(CONFIG_440GP) |
0442ed86 | 787 | ori r1,r1,0x0380 /* 8k rw */ |
b14ca4b6 DM |
788 | mtdcr ISRAM0_SB0CR,r1 |
789 | mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ | |
c157d8e2 | 790 | #endif |
887e2ec9 | 791 | #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |
0442ed86 WD |
792 | |
793 | /*----------------------------------------------------------------*/ | |
794 | /* Setup the stack in internal SRAM */ | |
795 | /*----------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
796 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
797 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
0442ed86 WD |
798 | li r0,0 |
799 | stwu r0,-4(r1) | |
800 | stwu r0,-4(r1) /* Terminate call chain */ | |
801 | ||
802 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
803 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
804 | ori r0,r0, RESET_VECTOR@l | |
805 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
806 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
39768f77 JT |
807 | #if defined(__pic__) && __pic__ == 1 |
808 | /* Needed for upcoming -msingle-pic-base */ | |
809 | bl _GLOBAL_OFFSET_TABLE_@local-4 | |
810 | mflr r30 | |
811 | #endif | |
887e2ec9 | 812 | #ifdef CONFIG_NAND_SPL |
64852d09 | 813 | bl nand_boot_common /* will not return */ |
887e2ec9 | 814 | #else |
0442ed86 | 815 | GET_GOT |
5568e613 SR |
816 | |
817 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
0442ed86 | 818 | bl board_init_f |
52ebd9c1 | 819 | /* NOTREACHED - board_init_f() does not return */ |
887e2ec9 | 820 | #endif |
0442ed86 WD |
821 | |
822 | #endif /* CONFIG_440 */ | |
823 | ||
824 | /*****************************************************************************/ | |
825 | #ifdef CONFIG_IOP480 | |
826 | /*----------------------------------------------------------------------- */ | |
827 | /* Set up some machine state registers. */ | |
828 | /*----------------------------------------------------------------------- */ | |
829 | addi r0,r0,0x0000 /* initialize r0 to zero */ | |
58ea142f | 830 | mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ |
0442ed86 WD |
831 | mttcr r0 /* timer control register */ |
832 | mtexier r0 /* disable all interrupts */ | |
0442ed86 WD |
833 | addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ |
834 | ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ | |
835 | mtdbsr r4 /* clear/reset the dbsr */ | |
836 | mtexisr r4 /* clear all pending interrupts */ | |
837 | addis r4,r0,0x8000 | |
838 | mtexier r4 /* enable critical exceptions */ | |
839 | addis r4,r0,0x0000 /* assume 403GCX - enable core clk */ | |
840 | ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */ | |
841 | mtiocr r4 /* since bit not used) & DRC to latch */ | |
842 | /* data bus on rising edge of CAS */ | |
843 | /*----------------------------------------------------------------------- */ | |
844 | /* Clear XER. */ | |
845 | /*----------------------------------------------------------------------- */ | |
846 | mtxer r0 | |
847 | /*----------------------------------------------------------------------- */ | |
848 | /* Invalidate i-cache and d-cache TAG arrays. */ | |
849 | /*----------------------------------------------------------------------- */ | |
850 | addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */ | |
851 | addi r4,0,1024 /* 1/4 of I-cache */ | |
852 | ..cloop: | |
853 | iccci 0,r3 | |
854 | iccci r4,r3 | |
855 | dccci 0,r3 | |
856 | addic. r3,r3,-16 /* move back one cache line */ | |
857 | bne ..cloop /* loop back to do rest until r3 = 0 */ | |
858 | ||
859 | /* */ | |
860 | /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */ | |
861 | /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */ | |
862 | /* */ | |
863 | ||
864 | /* first copy IOP480 register base address into r3 */ | |
865 | addis r3,0,0x5000 /* IOP480 register base address hi */ | |
866 | /* ori r3,r3,0x0000 / IOP480 register base address lo */ | |
867 | ||
868 | #ifdef CONFIG_ADCIOP | |
869 | /* use r4 as the working variable */ | |
870 | /* turn on CS3 (LOCCTL.7) */ | |
871 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
872 | andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */ | |
873 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
874 | #endif | |
875 | ||
876 | #ifdef CONFIG_DASA_SIM | |
877 | /* use r4 as the working variable */ | |
878 | /* turn on MA17 (LOCCTL.7) */ | |
879 | lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
880 | ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */ | |
881 | stw r4,0x84(r3) /* LOCTL is at offset 0x84 */ | |
882 | #endif | |
883 | ||
884 | /* turn on MA16..13 (LCS0BRD.12 = 0) */ | |
885 | lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
886 | andi. r4,r4,0xefff /* make bit 12 = 0 */ | |
887 | stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */ | |
888 | ||
889 | /* make sure above stores all comlete before going on */ | |
890 | sync | |
891 | ||
892 | /* last thing, set local init status done bit (DEVINIT.31) */ | |
893 | lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
894 | oris r4,r4,0x8000 /* make bit 31 = 1 */ | |
895 | stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */ | |
896 | ||
897 | /* clear all pending interrupts and disable all interrupts */ | |
898 | li r4,-1 /* set p1 to 0xffffffff */ | |
899 | stw r4,0x1b0(r3) /* clear all pending interrupts */ | |
900 | stw r4,0x1b8(r3) /* clear all pending interrupts */ | |
901 | li r4,0 /* set r4 to 0 */ | |
902 | stw r4,0x1b4(r3) /* disable all interrupts */ | |
903 | stw r4,0x1bc(r3) /* disable all interrupts */ | |
904 | ||
905 | /* make sure above stores all comlete before going on */ | |
906 | sync | |
907 | ||
c821b5f1 | 908 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
909 | lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h |
910 | ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 GE |
911 | mticcr r1 |
912 | isync | |
0442ed86 | 913 | |
c821b5f1 | 914 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
915 | lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h |
916 | ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 917 | mtdccr r1 |
0442ed86 | 918 | |
6d0f6bcf JCPV |
919 | addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
920 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */ | |
0442ed86 WD |
921 | li r0, 0 /* Make room for stack frame header and */ |
922 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
923 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
924 | ||
925 | GET_GOT /* initialize GOT access */ | |
39768f77 JT |
926 | #if defined(__pic__) && __pic__ == 1 |
927 | /* Needed for upcoming -msingle-pic-base */ | |
928 | bl _GLOBAL_OFFSET_TABLE_@local-4 | |
929 | mflr r30 | |
930 | #endif | |
0442ed86 | 931 | bl board_init_f /* run first part of init code (from Flash) */ |
52ebd9c1 | 932 | /* NOTREACHED - board_init_f() does not return */ |
0442ed86 WD |
933 | |
934 | #endif /* CONFIG_IOP480 */ | |
935 | ||
936 | /*****************************************************************************/ | |
e01bd218 SR |
937 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
938 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ | |
dbbd1257 | 939 | defined(CONFIG_405EX) || defined(CONFIG_405) |
0442ed86 WD |
940 | /*----------------------------------------------------------------------- */ |
941 | /* Clear and set up some registers. */ | |
942 | /*----------------------------------------------------------------------- */ | |
943 | addi r4,r0,0x0000 | |
dbbd1257 | 944 | #if !defined(CONFIG_405EX) |
58ea142f | 945 | mtspr SPRN_SGR,r4 |
dbbd1257 SR |
946 | #else |
947 | /* | |
948 | * On 405EX, completely clearing the SGR leads to PPC hangup | |
949 | * upon PCIe configuration access. The PCIe memory regions | |
950 | * need to be guarded! | |
951 | */ | |
952 | lis r3,0x0000 | |
953 | ori r3,r3,0x7FFC | |
58ea142f | 954 | mtspr SPRN_SGR,r3 |
dbbd1257 | 955 | #endif |
58ea142f | 956 | mtspr SPRN_DCWR,r4 |
0442ed86 WD |
957 | mtesr r4 /* clear Exception Syndrome Reg */ |
958 | mttcr r4 /* clear Timer Control Reg */ | |
959 | mtxer r4 /* clear Fixed-Point Exception Reg */ | |
960 | mtevpr r4 /* clear Exception Vector Prefix Reg */ | |
0442ed86 WD |
961 | addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ |
962 | /* dbsr is cleared by setting bits to 1) */ | |
963 | mtdbsr r4 /* clear/reset the dbsr */ | |
964 | ||
c821b5f1 | 965 | /* Invalidate the i- and d-caches. */ |
0442ed86 WD |
966 | bl invalidate_icache |
967 | bl invalidate_dcache | |
968 | ||
c821b5f1 | 969 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
970 | lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h |
971 | ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 | 972 | mticcr r4 |
0442ed86 WD |
973 | isync |
974 | ||
c821b5f1 | 975 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
976 | lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h |
977 | ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 978 | mtdccr r4 |
0442ed86 | 979 | |
1f4d5326 RR |
980 | #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ |
981 | && !defined (CONFIG_XILINX_405) | |
0442ed86 WD |
982 | /*----------------------------------------------------------------------- */ |
983 | /* Tune the speed and size for flash CS0 */ | |
984 | /*----------------------------------------------------------------------- */ | |
985 | bl ext_bus_cntlr_init | |
986 | #endif | |
64852d09 | 987 | |
6d0f6bcf | 988 | #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) |
dbbd1257 | 989 | /* |
c821b5f1 GE |
990 | * For boards that don't have OCM and can't use the data cache |
991 | * for their primordial stack, setup stack here directly after the | |
992 | * SDRAM is initialized in ext_bus_cntlr_init. | |
dbbd1257 | 993 | */ |
6d0f6bcf JCPV |
994 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
995 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ | |
dbbd1257 SR |
996 | |
997 | li r0, 0 /* Make room for stack frame header and */ | |
998 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
999 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
1000 | /* | |
1001 | * Set up a dummy frame to store reset vector as return address. | |
1002 | * this causes stack underflow to reset board. | |
1003 | */ | |
1004 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1005 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1006 | ori r0, r0, RESET_VECTOR@l | |
1007 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1008 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1009 | #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ |
0442ed86 | 1010 | |
b867d705 SR |
1011 | #if defined(CONFIG_405EP) |
1012 | /*----------------------------------------------------------------------- */ | |
1013 | /* DMA Status, clear to come up clean */ | |
1014 | /*----------------------------------------------------------------------- */ | |
53677ef1 | 1015 | addis r3,r0, 0xFFFF /* Clear all existing DMA status */ |
f901a83b | 1016 | ori r3,r3, 0xFFFF |
d1c3b275 | 1017 | mtdcr DMASR, r3 |
b867d705 | 1018 | |
53677ef1 | 1019 | bl ppc405ep_init /* do ppc405ep specific init */ |
b867d705 SR |
1020 | #endif /* CONFIG_405EP */ |
1021 | ||
6d0f6bcf | 1022 | #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) |
e01bd218 SR |
1023 | #if defined(CONFIG_405EZ) |
1024 | /******************************************************************** | |
1025 | * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 | |
1026 | *******************************************************************/ | |
1027 | /* | |
1028 | * We can map the OCM on the PLB3, so map it at | |
6d0f6bcf | 1029 | * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 |
e01bd218 | 1030 | */ |
6d0f6bcf JCPV |
1031 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1032 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
df8a24cd | 1033 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 | 1034 | mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ |
e01bd218 | 1035 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 | 1036 | mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ |
e01bd218 SR |
1037 | isync |
1038 | ||
6d0f6bcf JCPV |
1039 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1040 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
83b4cfa3 | 1041 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 SR |
1042 | mtdcr OCM0_DSRC1, r3 /* Set Data Side */ |
1043 | mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ | |
e01bd218 | 1044 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 SR |
1045 | mtdcr OCM0_DSRC2, r3 /* Set Data Side */ |
1046 | mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ | |
83b4cfa3 | 1047 | addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ |
d1c3b275 | 1048 | mtdcr OCM0_DISDPC,r3 |
e01bd218 SR |
1049 | |
1050 | isync | |
3cb86f3e | 1051 | #else /* CONFIG_405EZ */ |
0442ed86 WD |
1052 | /******************************************************************** |
1053 | * Setup OCM - On Chip Memory | |
1054 | *******************************************************************/ | |
1055 | /* Setup OCM */ | |
8bde7f77 WD |
1056 | lis r0, 0x7FFF |
1057 | ori r0, r0, 0xFFFF | |
d1c3b275 SR |
1058 | mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ |
1059 | mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ | |
3cb86f3e SR |
1060 | and r3, r3, r0 /* disable data-side IRAM */ |
1061 | and r4, r4, r0 /* disable data-side IRAM */ | |
d1c3b275 SR |
1062 | mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ |
1063 | mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ | |
8bde7f77 | 1064 | isync |
0442ed86 | 1065 | |
6d0f6bcf JCPV |
1066 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
1067 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
d1c3b275 | 1068 | mtdcr OCM0_DSARC, r3 |
0442ed86 | 1069 | addis r4, 0, 0xC000 /* OCM data area enabled */ |
d1c3b275 | 1070 | mtdcr OCM0_DSCNTL, r4 |
8bde7f77 | 1071 | isync |
e01bd218 | 1072 | #endif /* CONFIG_405EZ */ |
0442ed86 WD |
1073 | #endif |
1074 | ||
1075 | /*----------------------------------------------------------------------- */ | |
1076 | /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ | |
1077 | /*----------------------------------------------------------------------- */ | |
6d0f6bcf | 1078 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
c821b5f1 | 1079 | li r4, PBxAP |
d1c3b275 | 1080 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
1081 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h |
1082 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l | |
d1c3b275 | 1083 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
1084 | |
1085 | addi r4, 0, PBxCR | |
d1c3b275 | 1086 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
1087 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h |
1088 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l | |
d1c3b275 | 1089 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
1090 | |
1091 | /* | |
1092 | * Enable the data cache for the 128MB storage access control region | |
6d0f6bcf | 1093 | * at CONFIG_SYS_INIT_RAM_ADDR. |
c821b5f1 GE |
1094 | */ |
1095 | mfdccr r4 | |
6d0f6bcf JCPV |
1096 | oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1097 | ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
0442ed86 WD |
1098 | mtdccr r4 |
1099 | ||
c821b5f1 GE |
1100 | /* |
1101 | * Preallocate data cache lines to be used to avoid a subsequent | |
1102 | * cache miss and an ensuing machine check exception when exceptions | |
1103 | * are enabled. | |
1104 | */ | |
1105 | li r0, 0 | |
0442ed86 | 1106 | |
6d0f6bcf JCPV |
1107 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1108 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
0442ed86 | 1109 | |
553f0982 WD |
1110 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
1111 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
1112 | |
1113 | /* | |
1114 | * Convert the size, in bytes, to the number of cache lines/blocks | |
1115 | * to preallocate. | |
1116 | */ | |
1117 | clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) | |
1118 | srwi r5, r4, L1_CACHE_SHIFT | |
1119 | beq ..load_counter | |
1120 | addi r5, r5, 0x0001 | |
1121 | ..load_counter: | |
1122 | mtctr r5 | |
1123 | ||
1124 | /* Preallocate the computed number of cache blocks. */ | |
1125 | ..alloc_dcache_block: | |
1126 | dcba r0, r3 | |
1127 | addi r3, r3, L1_CACHE_BYTES | |
1128 | bdnz ..alloc_dcache_block | |
1129 | sync | |
1130 | ||
1131 | /* | |
1132 | * Load the initial stack pointer and data area and convert the size, | |
1133 | * in bytes, to the number of words to initialize to a known value. | |
1134 | */ | |
6d0f6bcf JCPV |
1135 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
1136 | ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l | |
c821b5f1 | 1137 | |
553f0982 WD |
1138 | lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h |
1139 | ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l | |
0442ed86 WD |
1140 | mtctr r4 |
1141 | ||
6d0f6bcf | 1142 | lis r2, CONFIG_SYS_INIT_RAM_ADDR@h |
553f0982 | 1143 | ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l |
0442ed86 | 1144 | |
6d0f6bcf JCPV |
1145 | lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h |
1146 | ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l | |
0442ed86 WD |
1147 | |
1148 | ..stackloop: | |
c821b5f1 | 1149 | stwu r4, -4(r2) |
0442ed86 WD |
1150 | bdnz ..stackloop |
1151 | ||
c821b5f1 GE |
1152 | /* |
1153 | * Make room for stack frame header and clear final stack frame so | |
1154 | * that stack backtraces terminate cleanly. | |
1155 | */ | |
1156 | stwu r0, -4(r1) | |
1157 | stwu r0, -4(r1) | |
1158 | ||
0442ed86 WD |
1159 | /* |
1160 | * Set up a dummy frame to store reset vector as return address. | |
1161 | * this causes stack underflow to reset board. | |
1162 | */ | |
1163 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1164 | addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ | |
1165 | ori r0, r0, RESET_VECTOR@l | |
1166 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1167 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
1168 | ||
6d0f6bcf JCPV |
1169 | #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ |
1170 | (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) | |
0442ed86 WD |
1171 | /* |
1172 | * Stack in OCM. | |
1173 | */ | |
1174 | ||
1175 | /* Set up Stack at top of OCM */ | |
6d0f6bcf JCPV |
1176 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h |
1177 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l | |
0442ed86 WD |
1178 | |
1179 | /* Set up a zeroized stack frame so that backtrace works right */ | |
1180 | li r0, 0 | |
1181 | stwu r0, -4(r1) | |
1182 | stwu r0, -4(r1) | |
1183 | ||
1184 | /* | |
1185 | * Set up a dummy frame to store reset vector as return address. | |
1186 | * this causes stack underflow to reset board. | |
1187 | */ | |
1188 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1189 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1190 | ori r0, r0, RESET_VECTOR@l | |
1191 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1192 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1193 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 1194 | |
39768f77 JT |
1195 | #if defined(__pic__) && __pic__ == 1 |
1196 | /* Needed for upcoming -msingle-pic-base */ | |
1197 | bl _GLOBAL_OFFSET_TABLE_@local-4 | |
1198 | mflr r30 | |
1199 | #endif | |
c440bfe6 | 1200 | #ifdef CONFIG_NAND_SPL |
64852d09 | 1201 | bl nand_boot_common /* will not return */ |
c440bfe6 | 1202 | #else |
0442ed86 WD |
1203 | GET_GOT /* initialize GOT access */ |
1204 | ||
f901a83b | 1205 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
0442ed86 | 1206 | |
0442ed86 | 1207 | bl board_init_f /* run first part of init code (from Flash) */ |
52ebd9c1 PT |
1208 | /* NOTREACHED - board_init_f() does not return */ |
1209 | ||
c440bfe6 | 1210 | #endif /* CONFIG_NAND_SPL */ |
0442ed86 | 1211 | |
12f34241 WD |
1212 | #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ |
1213 | /*----------------------------------------------------------------------- */ | |
0442ed86 WD |
1214 | |
1215 | ||
887e2ec9 | 1216 | #ifndef CONFIG_NAND_SPL |
0442ed86 WD |
1217 | /* |
1218 | * This code finishes saving the registers to the exception frame | |
1219 | * and jumps to the appropriate handler for the exception. | |
1220 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
1221 | */ | |
1222 | .globl transfer_to_handler | |
1223 | transfer_to_handler: | |
1224 | stw r22,_NIP(r21) | |
1225 | lis r22,MSR_POW@h | |
1226 | andc r23,r23,r22 | |
1227 | stw r23,_MSR(r21) | |
1228 | SAVE_GPR(7, r21) | |
1229 | SAVE_4GPRS(8, r21) | |
1230 | SAVE_8GPRS(12, r21) | |
1231 | SAVE_8GPRS(24, r21) | |
0442ed86 WD |
1232 | mflr r23 |
1233 | andi. r24,r23,0x3f00 /* get vector offset */ | |
1234 | stw r24,TRAP(r21) | |
1235 | li r22,0 | |
1236 | stw r22,RESULT(r21) | |
1237 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
0442ed86 WD |
1238 | lwz r24,0(r23) /* virtual address of handler */ |
1239 | lwz r23,4(r23) /* where to go when done */ | |
1240 | mtspr SRR0,r24 | |
1241 | mtspr SRR1,r20 | |
1242 | mtlr r23 | |
1243 | SYNC | |
1244 | rfi /* jump to handler, enable MMU */ | |
1245 | ||
1246 | int_return: | |
1247 | mfmsr r28 /* Disable interrupts */ | |
1248 | li r4,0 | |
1249 | ori r4,r4,MSR_EE | |
1250 | andc r28,r28,r4 | |
1251 | SYNC /* Some chip revs need this... */ | |
1252 | mtmsr r28 | |
1253 | SYNC | |
1254 | lwz r2,_CTR(r1) | |
1255 | lwz r0,_LINK(r1) | |
1256 | mtctr r2 | |
1257 | mtlr r0 | |
1258 | lwz r2,_XER(r1) | |
1259 | lwz r0,_CCR(r1) | |
1260 | mtspr XER,r2 | |
1261 | mtcrf 0xFF,r0 | |
1262 | REST_10GPRS(3, r1) | |
1263 | REST_10GPRS(13, r1) | |
1264 | REST_8GPRS(23, r1) | |
1265 | REST_GPR(31, r1) | |
1266 | lwz r2,_NIP(r1) /* Restore environment */ | |
1267 | lwz r0,_MSR(r1) | |
1268 | mtspr SRR0,r2 | |
1269 | mtspr SRR1,r0 | |
1270 | lwz r0,GPR0(r1) | |
1271 | lwz r2,GPR2(r1) | |
1272 | lwz r1,GPR1(r1) | |
1273 | SYNC | |
1274 | rfi | |
1275 | ||
1276 | crit_return: | |
1277 | mfmsr r28 /* Disable interrupts */ | |
1278 | li r4,0 | |
1279 | ori r4,r4,MSR_EE | |
1280 | andc r28,r28,r4 | |
1281 | SYNC /* Some chip revs need this... */ | |
1282 | mtmsr r28 | |
1283 | SYNC | |
1284 | lwz r2,_CTR(r1) | |
1285 | lwz r0,_LINK(r1) | |
1286 | mtctr r2 | |
1287 | mtlr r0 | |
1288 | lwz r2,_XER(r1) | |
1289 | lwz r0,_CCR(r1) | |
1290 | mtspr XER,r2 | |
1291 | mtcrf 0xFF,r0 | |
1292 | REST_10GPRS(3, r1) | |
1293 | REST_10GPRS(13, r1) | |
1294 | REST_8GPRS(23, r1) | |
1295 | REST_GPR(31, r1) | |
1296 | lwz r2,_NIP(r1) /* Restore environment */ | |
1297 | lwz r0,_MSR(r1) | |
58ea142f MF |
1298 | mtspr SPRN_CSRR0,r2 |
1299 | mtspr SPRN_CSRR1,r0 | |
0442ed86 WD |
1300 | lwz r0,GPR0(r1) |
1301 | lwz r2,GPR2(r1) | |
1302 | lwz r1,GPR1(r1) | |
1303 | SYNC | |
1304 | rfci | |
1305 | ||
efa35cf1 GB |
1306 | #ifdef CONFIG_440 |
1307 | mck_return: | |
83b4cfa3 WD |
1308 | mfmsr r28 /* Disable interrupts */ |
1309 | li r4,0 | |
1310 | ori r4,r4,MSR_EE | |
1311 | andc r28,r28,r4 | |
1312 | SYNC /* Some chip revs need this... */ | |
1313 | mtmsr r28 | |
1314 | SYNC | |
1315 | lwz r2,_CTR(r1) | |
1316 | lwz r0,_LINK(r1) | |
1317 | mtctr r2 | |
1318 | mtlr r0 | |
1319 | lwz r2,_XER(r1) | |
1320 | lwz r0,_CCR(r1) | |
1321 | mtspr XER,r2 | |
1322 | mtcrf 0xFF,r0 | |
1323 | REST_10GPRS(3, r1) | |
1324 | REST_10GPRS(13, r1) | |
1325 | REST_8GPRS(23, r1) | |
1326 | REST_GPR(31, r1) | |
1327 | lwz r2,_NIP(r1) /* Restore environment */ | |
1328 | lwz r0,_MSR(r1) | |
58ea142f MF |
1329 | mtspr SPRN_MCSRR0,r2 |
1330 | mtspr SPRN_MCSRR1,r0 | |
83b4cfa3 WD |
1331 | lwz r0,GPR0(r1) |
1332 | lwz r2,GPR2(r1) | |
1333 | lwz r1,GPR1(r1) | |
1334 | SYNC | |
1335 | rfmci | |
efa35cf1 GB |
1336 | #endif /* CONFIG_440 */ |
1337 | ||
1338 | ||
0442ed86 WD |
1339 | .globl get_pvr |
1340 | get_pvr: | |
1341 | mfspr r3, PVR | |
1342 | blr | |
1343 | ||
0442ed86 WD |
1344 | /*------------------------------------------------------------------------------- */ |
1345 | /* Function: out16 */ | |
1346 | /* Description: Output 16 bits */ | |
1347 | /*------------------------------------------------------------------------------- */ | |
1348 | .globl out16 | |
1349 | out16: | |
1350 | sth r4,0x0000(r3) | |
1351 | blr | |
1352 | ||
1353 | /*------------------------------------------------------------------------------- */ | |
1354 | /* Function: out16r */ | |
1355 | /* Description: Byte reverse and output 16 bits */ | |
1356 | /*------------------------------------------------------------------------------- */ | |
1357 | .globl out16r | |
1358 | out16r: | |
1359 | sthbrx r4,r0,r3 | |
1360 | blr | |
1361 | ||
0442ed86 WD |
1362 | /*------------------------------------------------------------------------------- */ |
1363 | /* Function: out32r */ | |
1364 | /* Description: Byte reverse and output 32 bits */ | |
1365 | /*------------------------------------------------------------------------------- */ | |
1366 | .globl out32r | |
1367 | out32r: | |
1368 | stwbrx r4,r0,r3 | |
1369 | blr | |
1370 | ||
1371 | /*------------------------------------------------------------------------------- */ | |
1372 | /* Function: in16 */ | |
1373 | /* Description: Input 16 bits */ | |
1374 | /*------------------------------------------------------------------------------- */ | |
1375 | .globl in16 | |
1376 | in16: | |
1377 | lhz r3,0x0000(r3) | |
1378 | blr | |
1379 | ||
1380 | /*------------------------------------------------------------------------------- */ | |
1381 | /* Function: in16r */ | |
1382 | /* Description: Input 16 bits and byte reverse */ | |
1383 | /*------------------------------------------------------------------------------- */ | |
1384 | .globl in16r | |
1385 | in16r: | |
1386 | lhbrx r3,r0,r3 | |
1387 | blr | |
1388 | ||
0442ed86 WD |
1389 | /*------------------------------------------------------------------------------- */ |
1390 | /* Function: in32r */ | |
1391 | /* Description: Input 32 bits and byte reverse */ | |
1392 | /*------------------------------------------------------------------------------- */ | |
1393 | .globl in32r | |
1394 | in32r: | |
1395 | lwbrx r3,r0,r3 | |
1396 | blr | |
1397 | ||
0442ed86 WD |
1398 | /* |
1399 | * void relocate_code (addr_sp, gd, addr_moni) | |
1400 | * | |
1401 | * This "function" does not return, instead it continues in RAM | |
1402 | * after relocating the monitor code. | |
1403 | * | |
c821b5f1 GE |
1404 | * r3 = Relocated stack pointer |
1405 | * r4 = Relocated global data pointer | |
1406 | * r5 = Relocated text pointer | |
0442ed86 WD |
1407 | */ |
1408 | .globl relocate_code | |
1409 | relocate_code: | |
6d0f6bcf | 1410 | #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) |
9b94ac61 | 1411 | /* |
7920954b SR |
1412 | * We need to flush the initial global data (gd_t) and bd_info |
1413 | * before the dcache will be invalidated. | |
9b94ac61 SR |
1414 | */ |
1415 | ||
c821b5f1 GE |
1416 | /* Save registers */ |
1417 | mr r9, r3 | |
1418 | mr r10, r4 | |
1419 | mr r11, r5 | |
9b94ac61 | 1420 | |
7920954b SR |
1421 | /* |
1422 | * Flush complete dcache, this is faster than flushing the | |
1423 | * ranges for global_data and bd_info instead. | |
1424 | */ | |
1425 | bl flush_dcache | |
9b94ac61 | 1426 | |
6d0f6bcf | 1427 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
c821b5f1 GE |
1428 | /* |
1429 | * Undo the earlier data cache set-up for the primordial stack and | |
1430 | * data area. First, invalidate the data cache and then disable data | |
1431 | * cacheability for that area. Finally, restore the EBC values, if | |
1432 | * any. | |
1433 | */ | |
1434 | ||
1435 | /* Invalidate the primordial stack and data area in cache */ | |
6d0f6bcf JCPV |
1436 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1437 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
c821b5f1 | 1438 | |
553f0982 WD |
1439 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
1440 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
1441 | add r4, r4, r3 |
1442 | ||
1443 | bl invalidate_dcache_range | |
1444 | ||
1445 | /* Disable cacheability for the region */ | |
1446 | mfdccr r3 | |
6d0f6bcf JCPV |
1447 | lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1448 | ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
c821b5f1 GE |
1449 | and r3, r3, r4 |
1450 | mtdccr r3 | |
1451 | ||
1452 | /* Restore the EBC parameters */ | |
1453 | li r3, PBxAP | |
d1c3b275 | 1454 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1455 | lis r3, PBxAP_VAL@h |
1456 | ori r3, r3, PBxAP_VAL@l | |
d1c3b275 | 1457 | mtdcr EBC0_CFGDATA, r3 |
c821b5f1 GE |
1458 | |
1459 | li r3, PBxCR | |
d1c3b275 | 1460 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1461 | lis r3, PBxCR_VAL@h |
1462 | ori r3, r3, PBxCR_VAL@l | |
d1c3b275 | 1463 | mtdcr EBC0_CFGDATA, r3 |
6d0f6bcf | 1464 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
c821b5f1 GE |
1465 | |
1466 | /* Restore registers */ | |
1467 | mr r3, r9 | |
1468 | mr r4, r10 | |
1469 | mr r5, r11 | |
6d0f6bcf | 1470 | #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
e02c521d | 1471 | |
6d0f6bcf | 1472 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
e02c521d SR |
1473 | /* |
1474 | * Unlock the previously locked d-cache | |
1475 | */ | |
1476 | msync | |
1477 | isync | |
1478 | /* set TFLOOR/NFLOOR to 0 again */ | |
1479 | lis r6,0x0001 | |
1480 | ori r6,r6,0xf800 | |
58ea142f | 1481 | mtspr SPRN_DVLIM,r6 |
e02c521d SR |
1482 | lis r6,0x0000 |
1483 | ori r6,r6,0x0000 | |
58ea142f MF |
1484 | mtspr SPRN_DNV0,r6 |
1485 | mtspr SPRN_DNV1,r6 | |
1486 | mtspr SPRN_DNV2,r6 | |
1487 | mtspr SPRN_DNV3,r6 | |
1488 | mtspr SPRN_DTV0,r6 | |
1489 | mtspr SPRN_DTV1,r6 | |
1490 | mtspr SPRN_DTV2,r6 | |
1491 | mtspr SPRN_DTV3,r6 | |
e02c521d SR |
1492 | msync |
1493 | isync | |
f3cac538 SR |
1494 | |
1495 | /* Invalidate data cache, now no longer our stack */ | |
1496 | dccci 0,0 | |
1497 | sync | |
1498 | isync | |
6d0f6bcf | 1499 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
e02c521d | 1500 | |
a4c8d138 SR |
1501 | /* |
1502 | * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) | |
1503 | * to speed up the boot process. Now this cache needs to be disabled. | |
1504 | */ | |
4978e605 | 1505 | #if defined(CONFIG_440) |
25fb4eaa | 1506 | /* Clear all potential pending exceptions */ |
58ea142f MF |
1507 | mfspr r1,SPRN_MCSR |
1508 | mtspr SPRN_MCSR,r1 | |
6d0f6bcf | 1509 | addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ |
c157d8e2 | 1510 | tlbre r0,r1,0x0002 /* Read contents */ |
6e7fb6ea | 1511 | ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ |
f901a83b | 1512 | tlbwe r0,r1,0x0002 /* Save it out */ |
a4c8d138 | 1513 | sync |
c157d8e2 | 1514 | isync |
4978e605 | 1515 | #endif /* defined(CONFIG_440) */ |
0442ed86 WD |
1516 | mr r1, r3 /* Set new stack pointer */ |
1517 | mr r9, r4 /* Save copy of Init Data pointer */ | |
1518 | mr r10, r5 /* Save copy of Destination Address */ | |
1519 | ||
0f8aa159 | 1520 | GET_GOT |
0442ed86 | 1521 | mr r3, r5 /* Destination Address */ |
6d0f6bcf JCPV |
1522 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
1523 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
3b57fe0a WD |
1524 | lwz r5, GOT(__init_end) |
1525 | sub r5, r5, r4 | |
9b94ac61 | 1526 | li r6, L1_CACHE_BYTES /* Cache Line Size */ |
0442ed86 WD |
1527 | |
1528 | /* | |
1529 | * Fix GOT pointer: | |
1530 | * | |
6d0f6bcf | 1531 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
0442ed86 WD |
1532 | * |
1533 | * Offset: | |
1534 | */ | |
1535 | sub r15, r10, r4 | |
1536 | ||
1537 | /* First our own GOT */ | |
0f8aa159 | 1538 | add r12, r12, r15 |
c821b5f1 | 1539 | /* then the one used by the C code */ |
0442ed86 WD |
1540 | add r30, r30, r15 |
1541 | ||
1542 | /* | |
1543 | * Now relocate code | |
1544 | */ | |
1545 | ||
1546 | cmplw cr1,r3,r4 | |
1547 | addi r0,r5,3 | |
1548 | srwi. r0,r0,2 | |
1549 | beq cr1,4f /* In place copy is not necessary */ | |
1550 | beq 7f /* Protect against 0 count */ | |
1551 | mtctr r0 | |
1552 | bge cr1,2f | |
1553 | ||
1554 | la r8,-4(r4) | |
1555 | la r7,-4(r3) | |
1556 | 1: lwzu r0,4(r8) | |
1557 | stwu r0,4(r7) | |
1558 | bdnz 1b | |
1559 | b 4f | |
1560 | ||
1561 | 2: slwi r0,r0,2 | |
1562 | add r8,r4,r0 | |
1563 | add r7,r3,r0 | |
1564 | 3: lwzu r0,-4(r8) | |
1565 | stwu r0,-4(r7) | |
1566 | bdnz 3b | |
1567 | ||
1568 | /* | |
1569 | * Now flush the cache: note that we must start from a cache aligned | |
1570 | * address. Otherwise we might miss one cache line. | |
1571 | */ | |
1572 | 4: cmpwi r6,0 | |
1573 | add r5,r3,r5 | |
1574 | beq 7f /* Always flush prefetch queue in any case */ | |
1575 | subi r0,r6,1 | |
1576 | andc r3,r3,r0 | |
1577 | mr r4,r3 | |
1578 | 5: dcbst 0,r4 | |
1579 | add r4,r4,r6 | |
1580 | cmplw r4,r5 | |
1581 | blt 5b | |
1582 | sync /* Wait for all dcbst to complete on bus */ | |
1583 | mr r4,r3 | |
1584 | 6: icbi 0,r4 | |
1585 | add r4,r4,r6 | |
1586 | cmplw r4,r5 | |
1587 | blt 6b | |
1588 | 7: sync /* Wait for all icbi to complete on bus */ | |
1589 | isync | |
1590 | ||
1591 | /* | |
1592 | * We are done. Do not return, instead branch to second part of board | |
1593 | * initialization, now running from RAM. | |
1594 | */ | |
1595 | ||
efa35cf1 | 1596 | addi r0, r10, in_ram - _start + _START_OFFSET |
0442ed86 WD |
1597 | mtlr r0 |
1598 | blr /* NEVER RETURNS! */ | |
1599 | ||
1600 | in_ram: | |
1601 | ||
1602 | /* | |
0f8aa159 | 1603 | * Relocation Function, r12 point to got2+0x8000 |
0442ed86 WD |
1604 | * |
1605 | * Adjust got2 pointers, no need to check for 0, this code | |
1606 | * already puts a few entries in the table. | |
1607 | */ | |
1608 | li r0,__got2_entries@sectoff@l | |
1609 | la r3,GOT(_GOT2_TABLE_) | |
1610 | lwz r11,GOT(_GOT2_TABLE_) | |
1611 | mtctr r0 | |
1612 | sub r11,r3,r11 | |
1613 | addi r3,r3,-4 | |
1614 | 1: lwzu r0,4(r3) | |
afc3ba0f JT |
1615 | cmpwi r0,0 |
1616 | beq- 2f | |
0442ed86 WD |
1617 | add r0,r0,r11 |
1618 | stw r0,0(r3) | |
afc3ba0f | 1619 | 2: bdnz 1b |
0442ed86 WD |
1620 | |
1621 | /* | |
1622 | * Now adjust the fixups and the pointers to the fixups | |
1623 | * in case we need to move ourselves again. | |
1624 | */ | |
afc3ba0f | 1625 | li r0,__fixup_entries@sectoff@l |
0442ed86 WD |
1626 | lwz r3,GOT(_FIXUP_TABLE_) |
1627 | cmpwi r0,0 | |
1628 | mtctr r0 | |
1629 | addi r3,r3,-4 | |
1630 | beq 4f | |
1631 | 3: lwzu r4,4(r3) | |
1632 | lwzux r0,r4,r11 | |
d1e0b10a | 1633 | cmpwi r0,0 |
0442ed86 | 1634 | add r0,r0,r11 |
34bbf618 | 1635 | stw r4,0(r3) |
d1e0b10a | 1636 | beq- 5f |
0442ed86 | 1637 | stw r0,0(r4) |
d1e0b10a | 1638 | 5: bdnz 3b |
0442ed86 WD |
1639 | 4: |
1640 | clear_bss: | |
1641 | /* | |
1642 | * Now clear BSS segment | |
1643 | */ | |
5d232d0e | 1644 | lwz r3,GOT(__bss_start) |
44c6e659 | 1645 | lwz r4,GOT(__bss_end__) |
0442ed86 WD |
1646 | |
1647 | cmplw 0, r3, r4 | |
42ed33ff | 1648 | beq 7f |
0442ed86 WD |
1649 | |
1650 | li r0, 0 | |
42ed33ff AG |
1651 | |
1652 | andi. r5, r4, 3 | |
1653 | beq 6f | |
1654 | sub r4, r4, r5 | |
1655 | mtctr r5 | |
1656 | mr r5, r4 | |
1657 | 5: stb r0, 0(r5) | |
1658 | addi r5, r5, 1 | |
1659 | bdnz 5b | |
1660 | 6: | |
0442ed86 WD |
1661 | stw r0, 0(r3) |
1662 | addi r3, r3, 4 | |
1663 | cmplw 0, r3, r4 | |
42ed33ff | 1664 | bne 6b |
0442ed86 | 1665 | |
42ed33ff | 1666 | 7: |
0442ed86 WD |
1667 | mr r3, r9 /* Init Data pointer */ |
1668 | mr r4, r10 /* Destination Address */ | |
1669 | bl board_init_r | |
1670 | ||
0442ed86 WD |
1671 | /* |
1672 | * Copy exception vector code to low memory | |
1673 | * | |
1674 | * r3: dest_addr | |
1675 | * r7: source address, r8: end address, r9: target address | |
1676 | */ | |
1677 | .globl trap_init | |
1678 | trap_init: | |
0f8aa159 JT |
1679 | mflr r4 /* save link register */ |
1680 | GET_GOT | |
efa35cf1 | 1681 | lwz r7, GOT(_start_of_vectors) |
0442ed86 WD |
1682 | lwz r8, GOT(_end_of_vectors) |
1683 | ||
682011ff | 1684 | li r9, 0x100 /* reset vector always at 0x100 */ |
0442ed86 WD |
1685 | |
1686 | cmplw 0, r7, r8 | |
1687 | bgelr /* return if r7>=r8 - just in case */ | |
0442ed86 WD |
1688 | 1: |
1689 | lwz r0, 0(r7) | |
1690 | stw r0, 0(r9) | |
1691 | addi r7, r7, 4 | |
1692 | addi r9, r9, 4 | |
1693 | cmplw 0, r7, r8 | |
1694 | bne 1b | |
1695 | ||
1696 | /* | |
1697 | * relocate `hdlr' and `int_return' entries | |
1698 | */ | |
efa35cf1 GB |
1699 | li r7, .L_MachineCheck - _start + _START_OFFSET |
1700 | li r8, Alignment - _start + _START_OFFSET | |
0442ed86 WD |
1701 | 2: |
1702 | bl trap_reloc | |
efa35cf1 | 1703 | addi r7, r7, 0x100 /* next exception vector */ |
0442ed86 WD |
1704 | cmplw 0, r7, r8 |
1705 | blt 2b | |
1706 | ||
efa35cf1 | 1707 | li r7, .L_Alignment - _start + _START_OFFSET |
0442ed86 WD |
1708 | bl trap_reloc |
1709 | ||
efa35cf1 | 1710 | li r7, .L_ProgramCheck - _start + _START_OFFSET |
0442ed86 WD |
1711 | bl trap_reloc |
1712 | ||
efa35cf1 GB |
1713 | #ifdef CONFIG_440 |
1714 | li r7, .L_FPUnavailable - _start + _START_OFFSET | |
83b4cfa3 | 1715 | bl trap_reloc |
0442ed86 | 1716 | |
efa35cf1 | 1717 | li r7, .L_Decrementer - _start + _START_OFFSET |
83b4cfa3 | 1718 | bl trap_reloc |
efa35cf1 GB |
1719 | |
1720 | li r7, .L_APU - _start + _START_OFFSET | |
83b4cfa3 | 1721 | bl trap_reloc |
df8a24cd | 1722 | |
83b4cfa3 WD |
1723 | li r7, .L_InstructionTLBError - _start + _START_OFFSET |
1724 | bl trap_reloc | |
efa35cf1 | 1725 | |
83b4cfa3 WD |
1726 | li r7, .L_DataTLBError - _start + _START_OFFSET |
1727 | bl trap_reloc | |
efa35cf1 GB |
1728 | #else /* CONFIG_440 */ |
1729 | li r7, .L_PIT - _start + _START_OFFSET | |
83b4cfa3 | 1730 | bl trap_reloc |
efa35cf1 GB |
1731 | |
1732 | li r7, .L_InstructionTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1733 | bl trap_reloc |
efa35cf1 GB |
1734 | |
1735 | li r7, .L_DataTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1736 | bl trap_reloc |
efa35cf1 GB |
1737 | #endif /* CONFIG_440 */ |
1738 | ||
83b4cfa3 WD |
1739 | li r7, .L_DebugBreakpoint - _start + _START_OFFSET |
1740 | bl trap_reloc | |
0442ed86 | 1741 | |
887e2ec9 | 1742 | #if !defined(CONFIG_440) |
9a7b408c SR |
1743 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1744 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1745 | mtmsr r7 /* change MSR */ | |
1746 | #else | |
887e2ec9 SR |
1747 | bl __440_msr_set |
1748 | b __440_msr_continue | |
9a7b408c | 1749 | |
887e2ec9 | 1750 | __440_msr_set: |
9a7b408c SR |
1751 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1752 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
58ea142f | 1753 | mtspr SPRN_SRR1,r7 |
9a7b408c | 1754 | mflr r7 |
58ea142f | 1755 | mtspr SPRN_SRR0,r7 |
9a7b408c | 1756 | rfi |
887e2ec9 | 1757 | __440_msr_continue: |
9a7b408c SR |
1758 | #endif |
1759 | ||
0442ed86 WD |
1760 | mtlr r4 /* restore link register */ |
1761 | blr | |
1762 | ||
cf959c7d SR |
1763 | #if defined(CONFIG_440) |
1764 | /*----------------------------------------------------------------------------+ | |
1765 | | dcbz_area. | |
1766 | +----------------------------------------------------------------------------*/ | |
1767 | function_prolog(dcbz_area) | |
1768 | rlwinm. r5,r4,0,27,31 | |
83b4cfa3 WD |
1769 | rlwinm r5,r4,27,5,31 |
1770 | beq ..d_ra2 | |
1771 | addi r5,r5,0x0001 | |
1772 | ..d_ra2:mtctr r5 | |
1773 | ..d_ag2:dcbz r0,r3 | |
1774 | addi r3,r3,32 | |
1775 | bdnz ..d_ag2 | |
cf959c7d SR |
1776 | sync |
1777 | blr | |
1778 | function_epilog(dcbz_area) | |
cf959c7d | 1779 | #endif /* CONFIG_440 */ |
887e2ec9 | 1780 | #endif /* CONFIG_NAND_SPL */ |
b867d705 | 1781 | |
cf959c7d SR |
1782 | /*------------------------------------------------------------------------------- */ |
1783 | /* Function: in8 */ | |
1784 | /* Description: Input 8 bits */ | |
1785 | /*------------------------------------------------------------------------------- */ | |
1786 | .globl in8 | |
1787 | in8: | |
1788 | lbz r3,0x0000(r3) | |
1789 | blr | |
1790 | ||
1791 | /*------------------------------------------------------------------------------- */ | |
1792 | /* Function: out8 */ | |
1793 | /* Description: Output 8 bits */ | |
1794 | /*------------------------------------------------------------------------------- */ | |
1795 | .globl out8 | |
1796 | out8: | |
1797 | stb r4,0x0000(r3) | |
1798 | blr | |
1799 | ||
1800 | /*------------------------------------------------------------------------------- */ | |
1801 | /* Function: out32 */ | |
1802 | /* Description: Output 32 bits */ | |
1803 | /*------------------------------------------------------------------------------- */ | |
1804 | .globl out32 | |
1805 | out32: | |
1806 | stw r4,0x0000(r3) | |
1807 | blr | |
1808 | ||
1809 | /*------------------------------------------------------------------------------- */ | |
1810 | /* Function: in32 */ | |
1811 | /* Description: Input 32 bits */ | |
1812 | /*------------------------------------------------------------------------------- */ | |
1813 | .globl in32 | |
1814 | in32: | |
1815 | lwz 3,0x0000(3) | |
1816 | blr | |
b867d705 SR |
1817 | |
1818 | /**************************************************************************/ | |
f901a83b | 1819 | /* PPC405EP specific stuff */ |
b867d705 SR |
1820 | /**************************************************************************/ |
1821 | #ifdef CONFIG_405EP | |
1822 | ppc405ep_init: | |
b828dda6 | 1823 | |
c157d8e2 | 1824 | #ifdef CONFIG_BUBINGA |
b828dda6 SR |
1825 | /* |
1826 | * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate | |
1827 | * function) to support FPGA and NVRAM accesses below. | |
1828 | */ | |
1829 | ||
1830 | lis r3,GPIO0_OSRH@h /* config GPIO output select */ | |
1831 | ori r3,r3,GPIO0_OSRH@l | |
6d0f6bcf JCPV |
1832 | lis r4,CONFIG_SYS_GPIO0_OSRH@h |
1833 | ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l | |
b828dda6 SR |
1834 | stw r4,0(r3) |
1835 | lis r3,GPIO0_OSRL@h | |
1836 | ori r3,r3,GPIO0_OSRL@l | |
6d0f6bcf JCPV |
1837 | lis r4,CONFIG_SYS_GPIO0_OSRL@h |
1838 | ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l | |
b828dda6 SR |
1839 | stw r4,0(r3) |
1840 | ||
1841 | lis r3,GPIO0_ISR1H@h /* config GPIO input select */ | |
1842 | ori r3,r3,GPIO0_ISR1H@l | |
6d0f6bcf JCPV |
1843 | lis r4,CONFIG_SYS_GPIO0_ISR1H@h |
1844 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l | |
b828dda6 SR |
1845 | stw r4,0(r3) |
1846 | lis r3,GPIO0_ISR1L@h | |
1847 | ori r3,r3,GPIO0_ISR1L@l | |
6d0f6bcf JCPV |
1848 | lis r4,CONFIG_SYS_GPIO0_ISR1L@h |
1849 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l | |
b828dda6 SR |
1850 | stw r4,0(r3) |
1851 | ||
1852 | lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ | |
1853 | ori r3,r3,GPIO0_TSRH@l | |
6d0f6bcf JCPV |
1854 | lis r4,CONFIG_SYS_GPIO0_TSRH@h |
1855 | ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l | |
b828dda6 SR |
1856 | stw r4,0(r3) |
1857 | lis r3,GPIO0_TSRL@h | |
1858 | ori r3,r3,GPIO0_TSRL@l | |
6d0f6bcf JCPV |
1859 | lis r4,CONFIG_SYS_GPIO0_TSRL@h |
1860 | ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l | |
b828dda6 SR |
1861 | stw r4,0(r3) |
1862 | ||
1863 | lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ | |
1864 | ori r3,r3,GPIO0_TCR@l | |
6d0f6bcf JCPV |
1865 | lis r4,CONFIG_SYS_GPIO0_TCR@h |
1866 | ori r4,r4,CONFIG_SYS_GPIO0_TCR@l | |
b828dda6 SR |
1867 | stw r4,0(r3) |
1868 | ||
d1c3b275 SR |
1869 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1870 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1871 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1872 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1873 | mtdcr EBC0_CFGDATA,r3 |
1874 | li r3,PB1CR | |
1875 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1876 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1877 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1878 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1879 | |
d1c3b275 SR |
1880 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1881 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1882 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1883 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1884 | mtdcr EBC0_CFGDATA,r3 |
1885 | li r3,PB1CR | |
1886 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1887 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1888 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1889 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1890 | |
d1c3b275 SR |
1891 | li r3,PB4AP /* program EBC bank 4 for FPGA access */ |
1892 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1893 | lis r3,CONFIG_SYS_EBC_PB4AP@h |
1894 | ori r3,r3,CONFIG_SYS_EBC_PB4AP@l | |
d1c3b275 SR |
1895 | mtdcr EBC0_CFGDATA,r3 |
1896 | li r3,PB4CR | |
1897 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1898 | lis r3,CONFIG_SYS_EBC_PB4CR@h |
1899 | ori r3,r3,CONFIG_SYS_EBC_PB4CR@l | |
d1c3b275 | 1900 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1901 | #endif |
8bde7f77 WD |
1902 | |
1903 | /* | |
1904 | !----------------------------------------------------------------------- | |
1905 | ! Check to see if chip is in bypass mode. | |
1906 | ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a | |
1907 | ! CPU reset Otherwise, skip this step and keep going. | |
f901a83b WD |
1908 | ! Note: Running BIOS in bypass mode is not supported since PLB speed |
1909 | ! will not be fast enough for the SDRAM (min 66MHz) | |
8bde7f77 | 1910 | !----------------------------------------------------------------------- |
b867d705 | 1911 | */ |
f901a83b | 1912 | mfdcr r5, CPC0_PLLMR1 |
53677ef1 | 1913 | rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ |
f901a83b | 1914 | cmpi cr0,0,r4,0x1 |
b867d705 | 1915 | |
53677ef1 WD |
1916 | beq pll_done /* if SSCS =b'1' then PLL has */ |
1917 | /* already been set */ | |
1918 | /* and CPU has been reset */ | |
1919 | /* so skip to next section */ | |
b867d705 | 1920 | |
c157d8e2 | 1921 | #ifdef CONFIG_BUBINGA |
b867d705 | 1922 | /* |
8bde7f77 WD |
1923 | !----------------------------------------------------------------------- |
1924 | ! Read NVRAM to get value to write in PLLMR. | |
1925 | ! If value has not been correctly saved, write default value | |
1926 | ! Default config values (assuming on-board 33MHz SYS_CLK) are above. | |
1927 | ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. | |
1928 | ! | |
1929 | ! WARNING: This code assumes the first three words in the nvram_t | |
f901a83b WD |
1930 | ! structure in openbios.h. Changing the beginning of |
1931 | ! the structure will break this code. | |
8bde7f77 WD |
1932 | ! |
1933 | !----------------------------------------------------------------------- | |
b867d705 | 1934 | */ |
f901a83b WD |
1935 | addis r3,0,NVRAM_BASE@h |
1936 | addi r3,r3,NVRAM_BASE@l | |
1937 | ||
1938 | lwz r4, 0(r3) | |
1939 | addis r5,0,NVRVFY1@h | |
1940 | addi r5,r5,NVRVFY1@l | |
53677ef1 | 1941 | cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ |
f901a83b WD |
1942 | bne ..no_pllset |
1943 | addi r3,r3,4 | |
1944 | lwz r4, 0(r3) | |
1945 | addis r5,0,NVRVFY2@h | |
1946 | addi r5,r5,NVRVFY2@l | |
53677ef1 | 1947 | cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ |
f901a83b WD |
1948 | bne ..no_pllset |
1949 | addi r3,r3,8 /* Skip over conf_size */ | |
1950 | lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ | |
1951 | lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ | |
1952 | rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ | |
1953 | cmpi cr0,0,r5,1 /* See if PLL is locked */ | |
1954 | beq pll_write | |
b867d705 | 1955 | ..no_pllset: |
c157d8e2 | 1956 | #endif /* CONFIG_BUBINGA */ |
b867d705 | 1957 | |
d4024bb7 JO |
1958 | #ifdef CONFIG_TAIHU |
1959 | mfdcr r4, CPC0_BOOT | |
1960 | andi. r5, r4, CPC0_BOOT_SEP@l | |
1961 | bne strap_1 /* serial eeprom present */ | |
1962 | addis r5,0,CPLD_REG0_ADDR@h | |
1963 | ori r5,r5,CPLD_REG0_ADDR@l | |
1964 | andi. r5, r5, 0x10 | |
1965 | bne _pci_66mhz | |
1966 | #endif /* CONFIG_TAIHU */ | |
1967 | ||
779e9751 SR |
1968 | #if defined(CONFIG_ZEUS) |
1969 | mfdcr r4, CPC0_BOOT | |
1970 | andi. r5, r4, CPC0_BOOT_SEP@l | |
53677ef1 | 1971 | bne strap_1 /* serial eeprom present */ |
779e9751 SR |
1972 | lis r3,0x0000 |
1973 | addi r3,r3,0x3030 | |
1974 | lis r4,0x8042 | |
1975 | addi r4,r4,0x223e | |
1976 | b 1f | |
1977 | strap_1: | |
1978 | mfdcr r3, CPC0_PLLMR0 | |
1979 | mfdcr r4, CPC0_PLLMR1 | |
1980 | b 1f | |
1981 | #endif | |
1982 | ||
53677ef1 WD |
1983 | addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ |
1984 | ori r3,r3,PLLMR0_DEFAULT@l /* */ | |
1985 | addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ | |
1986 | ori r4,r4,PLLMR1_DEFAULT@l /* */ | |
b867d705 | 1987 | |
d4024bb7 JO |
1988 | #ifdef CONFIG_TAIHU |
1989 | b 1f | |
1990 | _pci_66mhz: | |
1991 | addis r3,0,PLLMR0_DEFAULT_PCI66@h | |
1992 | ori r3,r3,PLLMR0_DEFAULT_PCI66@l | |
1993 | addis r4,0,PLLMR1_DEFAULT_PCI66@h | |
1994 | ori r4,r4,PLLMR1_DEFAULT_PCI66@l | |
1995 | b 1f | |
1996 | strap_1: | |
1997 | mfdcr r3, CPC0_PLLMR0 | |
1998 | mfdcr r4, CPC0_PLLMR1 | |
d4024bb7 JO |
1999 | #endif /* CONFIG_TAIHU */ |
2000 | ||
779e9751 | 2001 | 1: |
53677ef1 | 2002 | b pll_write /* Write the CPC0_PLLMR with new value */ |
b867d705 SR |
2003 | |
2004 | pll_done: | |
8bde7f77 WD |
2005 | /* |
2006 | !----------------------------------------------------------------------- | |
2007 | ! Clear Soft Reset Register | |
2008 | ! This is needed to enable PCI if not booting from serial EPROM | |
2009 | !----------------------------------------------------------------------- | |
b867d705 | 2010 | */ |
f901a83b WD |
2011 | addi r3, 0, 0x0 |
2012 | mtdcr CPC0_SRR, r3 | |
b867d705 | 2013 | |
f901a83b WD |
2014 | addis r3,0,0x0010 |
2015 | mtctr r3 | |
b867d705 | 2016 | pci_wait: |
f901a83b | 2017 | bdnz pci_wait |
b867d705 | 2018 | |
53677ef1 | 2019 | blr /* return to main code */ |
b867d705 SR |
2020 | |
2021 | /* | |
2022 | !----------------------------------------------------------------------------- | |
f901a83b WD |
2023 | ! Function: pll_write |
2024 | ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation | |
2025 | ! That is: | |
2026 | ! 1. Pll is first disabled (de-activated by putting in bypass mode) | |
2027 | ! 2. PLL is reset | |
2028 | ! 3. Clock dividers are set while PLL is held in reset and bypassed | |
2029 | ! 4. PLL Reset is cleared | |
2030 | ! 5. Wait 100us for PLL to lock | |
2031 | ! 6. A core reset is performed | |
b867d705 SR |
2032 | ! Input: r3 = Value to write to CPC0_PLLMR0 |
2033 | ! Input: r4 = Value to write to CPC0_PLLMR1 | |
2034 | ! Output r3 = none | |
2035 | !----------------------------------------------------------------------------- | |
2036 | */ | |
0580e48f | 2037 | .globl pll_write |
b867d705 | 2038 | pll_write: |
8bde7f77 WD |
2039 | mfdcr r5, CPC0_UCR |
2040 | andis. r5,r5,0xFFFF | |
53677ef1 WD |
2041 | ori r5,r5,0x0101 /* Stop the UART clocks */ |
2042 | mtdcr CPC0_UCR,r5 /* Before changing PLL */ | |
8bde7f77 WD |
2043 | |
2044 | mfdcr r5, CPC0_PLLMR1 | |
53677ef1 | 2045 | rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ |
f901a83b | 2046 | mtdcr CPC0_PLLMR1,r5 |
53677ef1 | 2047 | oris r5,r5,0x4000 /* Set PLL Reset */ |
f901a83b WD |
2048 | mtdcr CPC0_PLLMR1,r5 |
2049 | ||
53677ef1 WD |
2050 | mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ |
2051 | rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ | |
2052 | oris r5,r5,0x4000 /* Set PLL Reset */ | |
2053 | mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ | |
2054 | rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ | |
f901a83b | 2055 | mtdcr CPC0_PLLMR1,r5 |
b867d705 SR |
2056 | |
2057 | /* | |
8bde7f77 WD |
2058 | ! Wait min of 100us for PLL to lock. |
2059 | ! See CMOS 27E databook for more info. | |
2060 | ! At 200MHz, that means waiting 20,000 instructions | |
b867d705 | 2061 | */ |
f901a83b WD |
2062 | addi r3,0,20000 /* 2000 = 0x4e20 */ |
2063 | mtctr r3 | |
b867d705 | 2064 | pll_wait: |
f901a83b | 2065 | bdnz pll_wait |
8bde7f77 | 2066 | |
f901a83b WD |
2067 | oris r5,r5,0x8000 /* Enable PLL */ |
2068 | mtdcr CPC0_PLLMR1,r5 /* Engage */ | |
8bde7f77 WD |
2069 | |
2070 | /* | |
2071 | * Reset CPU to guarantee timings are OK | |
2072 | * Not sure if this is needed... | |
2073 | */ | |
2074 | addis r3,0,0x1000 | |
58ea142f | 2075 | mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ |
53677ef1 WD |
2076 | /* execution will continue from the poweron */ |
2077 | /* vector of 0xfffffffc */ | |
b867d705 | 2078 | #endif /* CONFIG_405EP */ |
4745acaa SR |
2079 | |
2080 | #if defined(CONFIG_440) | |
4745acaa SR |
2081 | /*----------------------------------------------------------------------------+ |
2082 | | mttlb3. | |
2083 | +----------------------------------------------------------------------------*/ | |
2084 | function_prolog(mttlb3) | |
2085 | TLBWE(4,3,2) | |
2086 | blr | |
2087 | function_epilog(mttlb3) | |
2088 | ||
2089 | /*----------------------------------------------------------------------------+ | |
2090 | | mftlb3. | |
2091 | +----------------------------------------------------------------------------*/ | |
2092 | function_prolog(mftlb3) | |
74357114 | 2093 | TLBRE(3,3,2) |
4745acaa SR |
2094 | blr |
2095 | function_epilog(mftlb3) | |
2096 | ||
2097 | /*----------------------------------------------------------------------------+ | |
2098 | | mttlb2. | |
2099 | +----------------------------------------------------------------------------*/ | |
2100 | function_prolog(mttlb2) | |
2101 | TLBWE(4,3,1) | |
2102 | blr | |
2103 | function_epilog(mttlb2) | |
2104 | ||
2105 | /*----------------------------------------------------------------------------+ | |
2106 | | mftlb2. | |
2107 | +----------------------------------------------------------------------------*/ | |
2108 | function_prolog(mftlb2) | |
74357114 | 2109 | TLBRE(3,3,1) |
4745acaa SR |
2110 | blr |
2111 | function_epilog(mftlb2) | |
2112 | ||
2113 | /*----------------------------------------------------------------------------+ | |
2114 | | mttlb1. | |
2115 | +----------------------------------------------------------------------------*/ | |
2116 | function_prolog(mttlb1) | |
2117 | TLBWE(4,3,0) | |
2118 | blr | |
2119 | function_epilog(mttlb1) | |
2120 | ||
2121 | /*----------------------------------------------------------------------------+ | |
2122 | | mftlb1. | |
2123 | +----------------------------------------------------------------------------*/ | |
2124 | function_prolog(mftlb1) | |
74357114 | 2125 | TLBRE(3,3,0) |
4745acaa SR |
2126 | blr |
2127 | function_epilog(mftlb1) | |
2128 | #endif /* CONFIG_440 */ | |
64852d09 SR |
2129 | |
2130 | #if defined(CONFIG_NAND_SPL) | |
2131 | /* | |
2132 | * void nand_boot_relocate(dst, src, bytes) | |
2133 | * | |
2134 | * r3 = Destination address to copy code to (in SDRAM) | |
2135 | * r4 = Source address to copy code from | |
2136 | * r5 = size to copy in bytes | |
2137 | */ | |
2138 | nand_boot_relocate: | |
2139 | mr r6,r3 | |
2140 | mr r7,r4 | |
2141 | mflr r8 | |
2142 | ||
2143 | /* | |
2144 | * Copy SPL from icache into SDRAM | |
2145 | */ | |
2146 | subi r3,r3,4 | |
2147 | subi r4,r4,4 | |
2148 | srwi r5,r5,2 | |
2149 | mtctr r5 | |
2150 | ..spl_loop: | |
2151 | lwzu r0,4(r4) | |
2152 | stwu r0,4(r3) | |
2153 | bdnz ..spl_loop | |
2154 | ||
2155 | /* | |
2156 | * Calculate "corrected" link register, so that we "continue" | |
2157 | * in execution in destination range | |
2158 | */ | |
2159 | sub r3,r7,r6 /* r3 = src - dst */ | |
2160 | sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ | |
2161 | mtlr r8 | |
2162 | blr | |
2163 | ||
2164 | nand_boot_common: | |
2165 | /* | |
2166 | * First initialize SDRAM. It has to be available *before* calling | |
2167 | * nand_boot(). | |
2168 | */ | |
6d0f6bcf JCPV |
2169 | lis r3,CONFIG_SYS_SDRAM_BASE@h |
2170 | ori r3,r3,CONFIG_SYS_SDRAM_BASE@l | |
64852d09 SR |
2171 | bl initdram |
2172 | ||
2173 | /* | |
2174 | * Now copy the 4k SPL code into SDRAM and continue execution | |
2175 | * from there. | |
2176 | */ | |
6d0f6bcf JCPV |
2177 | lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h |
2178 | ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l | |
2179 | lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h | |
2180 | ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l | |
2181 | lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h | |
2182 | ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l | |
64852d09 SR |
2183 | bl nand_boot_relocate |
2184 | ||
2185 | /* | |
2186 | * We're running from SDRAM now!!! | |
2187 | * | |
2188 | * It is necessary for 4xx systems to relocate from running at | |
2189 | * the original location (0xfffffxxx) to somewhere else (SDRAM | |
2190 | * preferably). This is because CS0 needs to be reconfigured for | |
2191 | * NAND access. And we can't reconfigure this CS when currently | |
2192 | * "running" from it. | |
2193 | */ | |
2194 | ||
2195 | /* | |
2196 | * Finally call nand_boot() to load main NAND U-Boot image from | |
2197 | * NAND and jump to it. | |
2198 | */ | |
2199 | bl nand_boot /* will not return */ | |
2200 | #endif /* CONFIG_NAND_SPL */ |