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[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h
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42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
19a8dbdc 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
837f1ba0 5 *
42d1f039
WD		 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 10 */
11
12#ifndef __IMMAP_85xx__
13#define __IMMAP_85xx__
14
3dfa9cfd 15#include <asm/types.h>
b1f12650 16#include <asm/fsl_dma.h>
3dfa9cfd 17#include <asm/fsl_i2c.h>
d789b5f5 18#include <asm/fsl_ifc.h>
4e190b03 19#include <asm/fsl_lbc.h>
ebd7cb0b 20#include <asm/fsl_fman.h>
3dfa9cfd 21
01df5212 22typedef struct ccsr_local {
8280912e
KG		 23 u32 ccsrbarh; /* CCSR Base Addr High */
24 u32 ccsrbarl; /* CCSR Base Addr Low */
25 u32 ccsrar; /* CCSR Attr */
01df5212
KG		 26#define CCSRAR_C 0x80000000 /* Commit */
27 u8 res1[4];
8280912e
KG		 28 u32 altcbarh; /* Alternate Configuration Base Addr High */
29 u32 altcbarl; /* Alternate Configuration Base Addr Low */
30 u32 altcar; /* Alternate Configuration Attr */
01df5212 31 u8 res2[4];
8280912e
KG		 32 u32 bstrh; /* Boot space translation high */
33 u32 bstrl; /* Boot space translation Low */
34 u32 bstrar; /* Boot space translation attributes */
01df5212
KG		 35 u8 res3[0xbd4];
36 struct {
8280912e
KG		 37 u32 lawbarh; /* LAWn base addr high */
38 u32 lawbarl; /* LAWn base addr low */
39 u32 lawar; /* LAWn attributes */
01df5212
KG		 40 u8 res4[4];
41 } law[32];
42 u8 res35[0x204];
43} ccsr_local_t;
44
8280912e 45/* Local-Access Registers & ECM Registers */
42d1f039 46typedef struct ccsr_local_ecm {
8280912e
KG		 47 u32 ccsrbar; /* CCSR Base Addr */
48 u8 res1[4];
49 u32 altcbar; /* Alternate Configuration Base Addr */
50 u8 res2[4];
51 u32 altcar; /* Alternate Configuration Attr */
52 u8 res3[12];
53 u32 bptr; /* Boot Page Translation */
54 u8 res4[3044];
55 u32 lawbar0; /* Local Access Window 0 Base Addr */
56 u8 res5[4];
57 u32 lawar0; /* Local Access Window 0 Attrs */
58 u8 res6[20];
59 u32 lawbar1; /* Local Access Window 1 Base Addr */
60 u8 res7[4];
61 u32 lawar1; /* Local Access Window 1 Attrs */
62 u8 res8[20];
63 u32 lawbar2; /* Local Access Window 2 Base Addr */
64 u8 res9[4];
65 u32 lawar2; /* Local Access Window 2 Attrs */
66 u8 res10[20];
67 u32 lawbar3; /* Local Access Window 3 Base Addr */
68 u8 res11[4];
69 u32 lawar3; /* Local Access Window 3 Attrs */
70 u8 res12[20];
71 u32 lawbar4; /* Local Access Window 4 Base Addr */
72 u8 res13[4];
73 u32 lawar4; /* Local Access Window 4 Attrs */
74 u8 res14[20];
75 u32 lawbar5; /* Local Access Window 5 Base Addr */
76 u8 res15[4];
77 u32 lawar5; /* Local Access Window 5 Attrs */
78 u8 res16[20];
79 u32 lawbar6; /* Local Access Window 6 Base Addr */
80 u8 res17[4];
81 u32 lawar6; /* Local Access Window 6 Attrs */
82 u8 res18[20];
83 u32 lawbar7; /* Local Access Window 7 Base Addr */
84 u8 res19[4];
85 u32 lawar7; /* Local Access Window 7 Attrs */
86 u8 res19_8a[20];
87 u32 lawbar8; /* Local Access Window 8 Base Addr */
88 u8 res19_8b[4];
89 u32 lawar8; /* Local Access Window 8 Attrs */
90 u8 res19_9a[20];
91 u32 lawbar9; /* Local Access Window 9 Base Addr */
92 u8 res19_9b[4];
93 u32 lawar9; /* Local Access Window 9 Attrs */
94 u8 res19_10a[20];
95 u32 lawbar10; /* Local Access Window 10 Base Addr */
96 u8 res19_10b[4];
97 u32 lawar10; /* Local Access Window 10 Attrs */
98 u8 res19_11a[20];
99 u32 lawbar11; /* Local Access Window 11 Base Addr */
100 u8 res19_11b[4];
101 u32 lawar11; /* Local Access Window 11 Attrs */
102 u8 res20[652];
103 u32 eebacr; /* ECM CCB Addr Configuration */
104 u8 res21[12];
105 u32 eebpcr; /* ECM CCB Port Configuration */
106 u8 res22[3564];
107 u32 eedr; /* ECM Error Detect */
108 u8 res23[4];
109 u32 eeer; /* ECM Error Enable */
110 u32 eeatr; /* ECM Error Attrs Capture */
111 u32 eeadr; /* ECM Error Addr Capture */
112 u8 res24[492];
42d1f039
WD		 113} ccsr_local_ecm_t;
114
8280912e 115/* DDR memory controller registers */
42d1f039 116typedef struct ccsr_ddr {
8280912e
KG		 117 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
118 u8 res1[4];
119 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
120 u8 res2[4];
121 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
122 u8 res3[4];
123 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
124 u8 res4[100];
125 u32 cs0_config; /* Chip Select Configuration */
126 u32 cs1_config; /* Chip Select Configuration */
127 u32 cs2_config; /* Chip Select Configuration */
128 u32 cs3_config; /* Chip Select Configuration */
129 u8 res4a[48];
130 u32 cs0_config_2; /* Chip Select Configuration 2 */
131 u32 cs1_config_2; /* Chip Select Configuration 2 */
132 u32 cs2_config_2; /* Chip Select Configuration 2 */
133 u32 cs3_config_2; /* Chip Select Configuration 2 */
134 u8 res5[48];
135 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
136 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
137 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
138 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
139 u32 sdram_cfg; /* SDRAM Control Configuration */
140 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
141 u32 sdram_mode; /* SDRAM Mode Configuration */
142 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
143 u32 sdram_md_cntl; /* SDRAM Mode Control */
144 u32 sdram_interval; /* SDRAM Interval Configuration */
145 u32 sdram_data_init; /* SDRAM Data initialization */
146 u8 res6[4];
147 u32 sdram_clk_cntl; /* SDRAM Clock Control */
148 u8 res7[20];
149 u32 init_addr; /* training init addr */
150 u32 init_ext_addr; /* training init extended addr */
151 u8 res8_1[16];
152 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
153 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
154 u8 reg8_1a[8];
155 u32 ddr_zq_cntl; /* ZQ calibration control*/
156 u32 ddr_wrlvl_cntl; /* write leveling control*/
157 u8 reg8_1aa[4];
158 u32 ddr_sr_cntr; /* self refresh counter */
159 u32 ddr_sdram_rcw_1; /* Control Words 1 */
160 u32 ddr_sdram_rcw_2; /* Control Words 2 */
9ab87d04
KG		 161 u8 reg_1ab[8];
162 u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
163 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
164 u8 res8_1b[104];
165 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
166 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
167 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
168 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
169 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
170 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
171 u8 res8_1ba[0x908];
8280912e
KG		 172 u32 ddr_dsr1; /* Debug Status 1 */
173 u32 ddr_dsr2; /* Debug Status 2 */
174 u32 ddr_cdr1; /* Control Driver 1 */
175 u32 ddr_cdr2; /* Control Driver 2 */
176 u8 res8_1c[200];
177 u32 ip_rev1; /* IP Block Revision 1 */
178 u32 ip_rev2; /* IP Block Revision 2 */
9ab87d04
KG		 179 u32 eor; /* Enhanced Optimization Register */
180 u8 res8_2[252];
181 u32 mtcr; /* Memory Test Control Register */
182 u8 res8_3[28];
183 u32 mtp1; /* Memory Test Pattern 1 */
184 u32 mtp2; /* Memory Test Pattern 2 */
185 u32 mtp3; /* Memory Test Pattern 3 */
186 u32 mtp4; /* Memory Test Pattern 4 */
187 u32 mtp5; /* Memory Test Pattern 5 */
188 u32 mtp6; /* Memory Test Pattern 6 */
189 u32 mtp7; /* Memory Test Pattern 7 */
190 u32 mtp8; /* Memory Test Pattern 8 */
191 u32 mtp9; /* Memory Test Pattern 9 */
192 u32 mtp10; /* Memory Test Pattern 10 */
193 u8 res8_4[184];
8280912e
KG		 194 u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
195 u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
196 u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
197 u8 res9[20];
198 u32 capture_data_hi; /* Data Path Read Capture High */
199 u32 capture_data_lo; /* Data Path Read Capture Low */
200 u32 capture_ecc; /* Data Path Read Capture ECC */
201 u8 res10[20];
202 u32 err_detect; /* Error Detect */
203 u32 err_disable; /* Error Disable */
204 u32 err_int_en;
205 u32 capture_attributes; /* Error Attrs Capture */
206 u32 capture_address; /* Error Addr Capture */
207 u32 capture_ext_address; /* Error Extended Addr Capture */
208 u32 err_sbe; /* Single-Bit ECC Error Management */
209 u8 res11[164];
d2a9568c
YS		 210 u32 debug[32]; /* debug_1 to debug_32 */
211 u8 res12[128];
42d1f039
WD		 212} ccsr_ddr_t;
213
9ab87d04
KG		 214#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
215#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
216
8280912e 217/* I2C Registers */
42d1f039 218typedef struct ccsr_i2c {
3dfa9cfd
JL		 219 struct fsl_i2c i2c[1];
220 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
42d1f039
WD		 221} ccsr_i2c_t;
222
03f5c550
WD		 223#if defined(CONFIG_MPC8540) \
224 || defined(CONFIG_MPC8541) \
d9b94f28 225 || defined(CONFIG_MPC8548) \
03f5c550 226 || defined(CONFIG_MPC8555)
8280912e 227/* DUART Registers */
42d1f039 228typedef struct ccsr_duart {
8280912e
KG		 229 u8 res1[1280];
230/* URBR1, UTHR1, UDLB1 with the same addr */
231 u8 urbr1_uthr1_udlb1;
232/* UIER1, UDMB1 with the same addr01 */
233 u8 uier1_udmb1;
234/* UIIR1, UFCR1, UAFR1 with the same addr */
235 u8 uiir1_ufcr1_uafr1;
236 u8 ulcr1; /* UART1 Line Control */
237 u8 umcr1; /* UART1 Modem Control */
238 u8 ulsr1; /* UART1 Line Status */
239 u8 umsr1; /* UART1 Modem Status */
240 u8 uscr1; /* UART1 Scratch */
241 u8 res2[8];
242 u8 udsr1; /* UART1 DMA Status */
243 u8 res3[239];
244/* URBR2, UTHR2, UDLB2 with the same addr */
245 u8 urbr2_uthr2_udlb2;
246/* UIER2, UDMB2 with the same addr */
247 u8 uier2_udmb2;
248/* UIIR2, UFCR2, UAFR2 with the same addr */
249 u8 uiir2_ufcr2_uafr2;
250 u8 ulcr2; /* UART2 Line Control */
251 u8 umcr2; /* UART2 Modem Control */
252 u8 ulsr2; /* UART2 Line Status */
253 u8 umsr2; /* UART2 Modem Status */
254 u8 uscr2; /* UART2 Scratch */
255 u8 res4[8];
256 u8 udsr2; /* UART2 DMA Status */
257 u8 res5[2543];
42d1f039
WD		 258} ccsr_duart_t;
259#else /* MPC8560 uses UART on its CPM */
260typedef struct ccsr_duart {
8280912e 261 u8 res[4096];
42d1f039
WD		 262} ccsr_duart_t;
263#endif
264
8280912e 265/* eSPI Registers */
7fa96a9a 266typedef struct ccsr_espi {
8280912e
KG		 267 u32 mode; /* eSPI mode */
268 u32 event; /* eSPI event */
269 u32 mask; /* eSPI mask */
270 u32 com; /* eSPI command */
271 u32 tx; /* eSPI transmit FIFO access */
272 u32 rx; /* eSPI receive FIFO access */
273 u8 res1[8]; /* reserved */
274 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
275 u8 res2[4048]; /* fill up to 0x1000 */
7fa96a9a
MH		 276} ccsr_espi_t;
277
8280912e 278/* PCI Registers */
42d1f039 279typedef struct ccsr_pcix {
8280912e
KG		 280 u32 cfg_addr; /* PCIX Configuration Addr */
281 u32 cfg_data; /* PCIX Configuration Data */
282 u32 int_ack; /* PCIX IRQ Acknowledge */
e389a377
LT		 283 u8 res000c[52];
284 u32 liodn_base; /* PCIX LIODN base register */
285 u8 res0044[3004];
8280912e
KG		 286 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
287 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
288 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
289 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
290 u32 powar0; /* PCIX Outbound Window Attrs 0 */
291 u8 res2[12];
292 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
293 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
294 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
295 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
296 u32 powar1; /* PCIX Outbound Window Attrs 1 */
297 u8 res3[12];
298 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
299 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
300 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
301 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
302 u32 powar2; /* PCIX Outbound Window Attrs 2 */
303 u8 res4[12];
304 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
305 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
306 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
307 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
308 u32 powar3; /* PCIX Outbound Window Attrs 3 */
309 u8 res5[12];
310 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
311 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
312 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
313 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
314 u32 powar4; /* PCIX Outbound Window Attrs 4 */
315 u8 res6[268];
316 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
317 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
318 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
319 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
320 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
321 u8 res7[12];
322 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
323 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
324 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
325 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
326 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
327 u8 res8[12];
328 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
329 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
330 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
331 u8 res9[4];
332 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
333 u8 res10[12];
334 u32 pedr; /* PCIX Error Detect */
335 u32 pecdr; /* PCIX Error Capture Disable */
336 u32 peer; /* PCIX Error Enable */
337 u32 peattrcr; /* PCIX Error Attrs Capture */
338 u32 peaddrcr; /* PCIX Error Addr Capture */
339 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
340 u32 pedlcr; /* PCIX Error Data Low Capture */
341 u32 pedhcr; /* PCIX Error Error Data High Capture */
342 u32 gas_timr; /* PCIX Gasket Timer */
343 u8 res11[476];
42d1f039
WD		 344} ccsr_pcix_t;
345
97074ed9
MM		 346#define PCIX_COMMAND 0x62
347#define POWAR_EN 0x80000000
348#define POWAR_IO_READ 0x00080000
349#define POWAR_MEM_READ 0x00040000
350#define POWAR_IO_WRITE 0x00008000
351#define POWAR_MEM_WRITE 0x00004000
352#define POWAR_MEM_512M 0x0000001c
353#define POWAR_IO_1M 0x00000013
354
355#define PIWAR_EN 0x80000000
356#define PIWAR_PF 0x20000000
357#define PIWAR_LOCAL 0x00f00000
358#define PIWAR_READ_SNOOP 0x00050000
359#define PIWAR_WRITE_SNOOP 0x00005000
360#define PIWAR_MEM_2G 0x0000001e
361
8280912e
KG		 362typedef struct ccsr_gpio {
363 u32 gpdir;
364 u32 gpodr;
365 u32 gpdat;
366 u32 gpier;
367 u32 gpimr;
368 u32 gpicr;
369} ccsr_gpio_t;
97074ed9 370
8280912e 371/* L2 Cache Registers */
42d1f039 372typedef struct ccsr_l2cache {
8280912e
KG		 373 u32 l2ctl; /* L2 configuration 0 */
374 u8 res1[12];
375 u32 l2cewar0; /* L2 cache external write addr 0 */
376 u8 res2[4];
377 u32 l2cewcr0; /* L2 cache external write control 0 */
378 u8 res3[4];
379 u32 l2cewar1; /* L2 cache external write addr 1 */
380 u8 res4[4];
381 u32 l2cewcr1; /* L2 cache external write control 1 */
382 u8 res5[4];
383 u32 l2cewar2; /* L2 cache external write addr 2 */
384 u8 res6[4];
385 u32 l2cewcr2; /* L2 cache external write control 2 */
386 u8 res7[4];
387 u32 l2cewar3; /* L2 cache external write addr 3 */
388 u8 res8[4];
389 u32 l2cewcr3; /* L2 cache external write control 3 */
390 u8 res9[180];
391 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
392 u8 res10[4];
393 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
394 u8 res11[3316];
395 u32 l2errinjhi; /* L2 error injection mask high */
396 u32 l2errinjlo; /* L2 error injection mask low */
397 u32 l2errinjctl; /* L2 error injection tag/ECC control */
398 u8 res12[20];
399 u32 l2captdatahi; /* L2 error data high capture */
400 u32 l2captdatalo; /* L2 error data low capture */
401 u32 l2captecc; /* L2 error ECC capture */
402 u8 res13[20];
403 u32 l2errdet; /* L2 error detect */
404 u32 l2errdis; /* L2 error disable */
405 u32 l2errinten; /* L2 error interrupt enable */
406 u32 l2errattr; /* L2 error attributes capture */
407 u32 l2erraddr; /* L2 error addr capture */
408 u8 res14[4];
409 u32 l2errctl; /* L2 error control */
410 u8 res15[420];
42d1f039
WD		 411} ccsr_l2cache_t;
412
76b474e2
MH		 413#define MPC85xx_L2CTL_L2E 0x80000000
414#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
415#define MPC85xx_L2ERRDIS_MBECC 0x00000008
416#define MPC85xx_L2ERRDIS_SBECC 0x00000004
417
8280912e 418/* DMA Registers */
42d1f039 419typedef struct ccsr_dma {
8280912e 420 u8 res1[256];
b1f12650 421 struct fsl_dma dma[4];
8280912e
KG		 422 u32 dgsr; /* DMA General Status */
423 u8 res2[11516];
42d1f039
WD		 424} ccsr_dma_t;
425
8280912e 426/* tsec */
42d1f039 427typedef struct ccsr_tsec {
8280912e
KG		 428 u8 res1[16];
429 u32 ievent; /* IRQ Event */
430 u32 imask; /* IRQ Mask */
431 u32 edis; /* Error Disabled */
432 u8 res2[4];
433 u32 ecntrl; /* Ethernet Control */
434 u32 minflr; /* Minimum Frame Len */
435 u32 ptv; /* Pause Time Value */
436 u32 dmactrl; /* DMA Control */
437 u32 tbipa; /* TBI PHY Addr */
438 u8 res3[88];
439 u32 fifo_tx_thr; /* FIFO transmit threshold */
440 u8 res4[8];
441 u32 fifo_tx_starve; /* FIFO transmit starve */
442 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
443 u8 res5[96];
444 u32 tctrl; /* TX Control */
445 u32 tstat; /* TX Status */
446 u8 res6[4];
447 u32 tbdlen; /* TX Buffer Desc Data Len */
448 u8 res7[16];
449 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
450 u32 ctbptr; /* Current TX Buffer Desc Ptr */
451 u8 res8[88];
452 u32 tbptrh; /* TX Buffer Desc Ptr High */
453 u32 tbptr; /* TX Buffer Desc Ptr Low */
454 u8 res9[120];
455 u32 tbaseh; /* TX Desc Base Addr High */
456 u32 tbase; /* TX Desc Base Addr */
457 u8 res10[168];
458 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
459 u32 ostbdp; /* OOS TX Data Buffer Ptr */
460 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
461 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
462 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
463 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
464 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
465 u8 res11[52];
466 u32 rctrl; /* RX Control */
467 u32 rstat; /* RX Status */
468 u8 res12[4];
469 u32 rbdlen; /* RxBD Data Len */
470 u8 res13[16];
471 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
472 u32 crbptr; /* Current RX Buffer Desc Ptr */
473 u8 res14[24];
474 u32 mrblr; /* Maximum RX Buffer Len */
475 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
476 u8 res15[56];
477 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
478 u32 rbptr; /* RX Buffer Desc Ptr */
479 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
480 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
481 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
482 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
483 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
484 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
485 u8 res16[96];
486 u32 rbaseh; /* RX Desc Base Addr High 0 */
487 u32 rbase; /* RX Desc Base Addr */
488 u32 rbaseh1; /* RX Desc Base Addr High 1 */
489 u32 rbasel1; /* RX Desc Base Addr Low 1 */
490 u32 rbaseh2; /* RX Desc Base Addr High 2 */
491 u32 rbasel2; /* RX Desc Base Addr Low 2 */
492 u32 rbaseh3; /* RX Desc Base Addr High 3 */
493 u32 rbasel3; /* RX Desc Base Addr Low 3 */
494 u8 res17[224];
495 u32 maccfg1; /* MAC Configuration 1 */
496 u32 maccfg2; /* MAC Configuration 2 */
497 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
498 u32 hafdup; /* Half Duplex */
499 u32 maxfrm; /* Maximum Frame Len */
500 u8 res18[12];
501 u32 miimcfg; /* MII Management Configuration */
502 u32 miimcom; /* MII Management Cmd */
503 u32 miimadd; /* MII Management Addr */
504 u32 miimcon; /* MII Management Control */
505 u32 miimstat; /* MII Management Status */
506 u32 miimind; /* MII Management Indicator */
507 u8 res19[4];
508 u32 ifstat; /* Interface Status */
509 u32 macstnaddr1; /* Station Addr Part 1 */
510 u32 macstnaddr2; /* Station Addr Part 2 */
511 u8 res20[312];
512 u32 tr64; /* TX & RX 64-byte Frame Counter */
513 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
514 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
515 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
516 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
517 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
518 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
519 u32 rbyt; /* RX Byte Counter */
520 u32 rpkt; /* RX Packet Counter */
521 u32 rfcs; /* RX FCS Error Counter */
522 u32 rmca; /* RX Multicast Packet Counter */
523 u32 rbca; /* RX Broadcast Packet Counter */
524 u32 rxcf; /* RX Control Frame Packet Counter */
525 u32 rxpf; /* RX Pause Frame Packet Counter */
526 u32 rxuo; /* RX Unknown OP Code Counter */
527 u32 raln; /* RX Alignment Error Counter */
528 u32 rflr; /* RX Frame Len Error Counter */
529 u32 rcde; /* RX Code Error Counter */
530 u32 rcse; /* RX Carrier Sense Error Counter */
531 u32 rund; /* RX Undersize Packet Counter */
532 u32 rovr; /* RX Oversize Packet Counter */
533 u32 rfrg; /* RX Fragments Counter */
534 u32 rjbr; /* RX Jabber Counter */
535 u32 rdrp; /* RX Drop Counter */
536 u32 tbyt; /* TX Byte Counter Counter */
537 u32 tpkt; /* TX Packet Counter */
538 u32 tmca; /* TX Multicast Packet Counter */
539 u32 tbca; /* TX Broadcast Packet Counter */
540 u32 txpf; /* TX Pause Control Frame Counter */
541 u32 tdfr; /* TX Deferral Packet Counter */
542 u32 tedf; /* TX Excessive Deferral Packet Counter */
543 u32 tscl; /* TX Single Collision Packet Counter */
544 u32 tmcl; /* TX Multiple Collision Packet Counter */
545 u32 tlcl; /* TX Late Collision Packet Counter */
546 u32 txcl; /* TX Excessive Collision Packet Counter */
547 u32 tncl; /* TX Total Collision Counter */
548 u8 res21[4];
549 u32 tdrp; /* TX Drop Frame Counter */
550 u32 tjbr; /* TX Jabber Frame Counter */
551 u32 tfcs; /* TX FCS Error Counter */
552 u32 txcf; /* TX Control Frame Counter */
553 u32 tovr; /* TX Oversize Frame Counter */
554 u32 tund; /* TX Undersize Frame Counter */
555 u32 tfrg; /* TX Fragments Frame Counter */
556 u32 car1; /* Carry One */
557 u32 car2; /* Carry Two */
558 u32 cam1; /* Carry Mask One */
559 u32 cam2; /* Carry Mask Two */
560 u8 res22[192];
561 u32 iaddr0; /* Indivdual addr 0 */
562 u32 iaddr1; /* Indivdual addr 1 */
563 u32 iaddr2; /* Indivdual addr 2 */
564 u32 iaddr3; /* Indivdual addr 3 */
565 u32 iaddr4; /* Indivdual addr 4 */
566 u32 iaddr5; /* Indivdual addr 5 */
567 u32 iaddr6; /* Indivdual addr 6 */
568 u32 iaddr7; /* Indivdual addr 7 */
569 u8 res23[96];
570 u32 gaddr0; /* Global addr 0 */
571 u32 gaddr1; /* Global addr 1 */
572 u32 gaddr2; /* Global addr 2 */
573 u32 gaddr3; /* Global addr 3 */
574 u32 gaddr4; /* Global addr 4 */
575 u32 gaddr5; /* Global addr 5 */
576 u32 gaddr6; /* Global addr 6 */
577 u32 gaddr7; /* Global addr 7 */
578 u8 res24[96];
579 u32 pmd0; /* Pattern Match Data */
580 u8 res25[4];
581 u32 pmask0; /* Pattern Mask */
582 u8 res26[4];
583 u32 pcntrl0; /* Pattern Match Control */
584 u8 res27[4];
585 u32 pattrb0; /* Pattern Match Attrs */
586 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
587 u32 pmd1; /* Pattern Match Data */
588 u8 res28[4];
589 u32 pmask1; /* Pattern Mask */
590 u8 res29[4];
591 u32 pcntrl1; /* Pattern Match Control */
592 u8 res30[4];
593 u32 pattrb1; /* Pattern Match Attrs */
594 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
595 u32 pmd2; /* Pattern Match Data */
596 u8 res31[4];
597 u32 pmask2; /* Pattern Mask */
598 u8 res32[4];
599 u32 pcntrl2; /* Pattern Match Control */
600 u8 res33[4];
601 u32 pattrb2; /* Pattern Match Attrs */
602 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
603 u32 pmd3; /* Pattern Match Data */
604 u8 res34[4];
605 u32 pmask3; /* Pattern Mask */
606 u8 res35[4];
607 u32 pcntrl3; /* Pattern Match Control */
608 u8 res36[4];
609 u32 pattrb3; /* Pattern Match Attrs */
610 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
611 u32 pmd4; /* Pattern Match Data */
612 u8 res37[4];
613 u32 pmask4; /* Pattern Mask */
614 u8 res38[4];
615 u32 pcntrl4; /* Pattern Match Control */
616 u8 res39[4];
617 u32 pattrb4; /* Pattern Match Attrs */
618 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
619 u32 pmd5; /* Pattern Match Data */
620 u8 res40[4];
621 u32 pmask5; /* Pattern Mask */
622 u8 res41[4];
623 u32 pcntrl5; /* Pattern Match Control */
624 u8 res42[4];
625 u32 pattrb5; /* Pattern Match Attrs */
626 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
627 u32 pmd6; /* Pattern Match Data */
628 u8 res43[4];
629 u32 pmask6; /* Pattern Mask */
630 u8 res44[4];
631 u32 pcntrl6; /* Pattern Match Control */
632 u8 res45[4];
633 u32 pattrb6; /* Pattern Match Attrs */
634 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
635 u32 pmd7; /* Pattern Match Data */
636 u8 res46[4];
637 u32 pmask7; /* Pattern Mask */
638 u8 res47[4];
639 u32 pcntrl7; /* Pattern Match Control */
640 u8 res48[4];
641 u32 pattrb7; /* Pattern Match Attrs */
642 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
643 u32 pmd8; /* Pattern Match Data */
644 u8 res49[4];
645 u32 pmask8; /* Pattern Mask */
646 u8 res50[4];
647 u32 pcntrl8; /* Pattern Match Control */
648 u8 res51[4];
649 u32 pattrb8; /* Pattern Match Attrs */
650 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
651 u32 pmd9; /* Pattern Match Data */
652 u8 res52[4];
653 u32 pmask9; /* Pattern Mask */
654 u8 res53[4];
655 u32 pcntrl9; /* Pattern Match Control */
656 u8 res54[4];
657 u32 pattrb9; /* Pattern Match Attrs */
658 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
659 u32 pmd10; /* Pattern Match Data */
660 u8 res55[4];
661 u32 pmask10; /* Pattern Mask */
662 u8 res56[4];
663 u32 pcntrl10; /* Pattern Match Control */
664 u8 res57[4];
665 u32 pattrb10; /* Pattern Match Attrs */
666 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
667 u32 pmd11; /* Pattern Match Data */
668 u8 res58[4];
669 u32 pmask11; /* Pattern Mask */
670 u8 res59[4];
671 u32 pcntrl11; /* Pattern Match Control */
672 u8 res60[4];
673 u32 pattrb11; /* Pattern Match Attrs */
674 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
675 u32 pmd12; /* Pattern Match Data */
676 u8 res61[4];
677 u32 pmask12; /* Pattern Mask */
678 u8 res62[4];
679 u32 pcntrl12; /* Pattern Match Control */
680 u8 res63[4];
681 u32 pattrb12; /* Pattern Match Attrs */
682 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
683 u32 pmd13; /* Pattern Match Data */
684 u8 res64[4];
685 u32 pmask13; /* Pattern Mask */
686 u8 res65[4];
687 u32 pcntrl13; /* Pattern Match Control */
688 u8 res66[4];
689 u32 pattrb13; /* Pattern Match Attrs */
690 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
691 u32 pmd14; /* Pattern Match Data */
692 u8 res67[4];
693 u32 pmask14; /* Pattern Mask */
694 u8 res68[4];
695 u32 pcntrl14; /* Pattern Match Control */
696 u8 res69[4];
697 u32 pattrb14; /* Pattern Match Attrs */
698 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
699 u32 pmd15; /* Pattern Match Data */
700 u8 res70[4];
701 u32 pmask15; /* Pattern Mask */
702 u8 res71[4];
703 u32 pcntrl15; /* Pattern Match Control */
704 u8 res72[4];
705 u32 pattrb15; /* Pattern Match Attrs */
706 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
707 u8 res73[248];
708 u32 attr; /* Attrs */
709 u32 attreli; /* Attrs Extract Len & Idx */
710 u8 res74[1024];
42d1f039
WD		 711} ccsr_tsec_t;
712
8280912e 713/* PIC Registers */
42d1f039 714typedef struct ccsr_pic {
8280912e
KG		 715 u8 res1[64];
716 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
717 u8 res2[12];
718 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
719 u8 res3[12];
720 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
721 u8 res4[12];
722 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
723 u8 res5[12];
724 u32 ctpr; /* Current Task Priority */
725 u8 res6[12];
726 u32 whoami; /* Who Am I */
727 u8 res7[12];
728 u32 iack; /* IRQ Acknowledge */
729 u8 res8[12];
730 u32 eoi; /* End Of IRQ */
731 u8 res9[3916];
732 u32 frr; /* Feature Reporting */
733 u8 res10[28];
734 u32 gcr; /* Global Configuration */
735#define MPC85xx_PICGCR_RST 0x80000000
736#define MPC85xx_PICGCR_M 0x20000000
737 u8 res11[92];
738 u32 vir; /* Vendor Identification */
739 u8 res12[12];
740 u32 pir; /* Processor Initialization */
741 u8 res13[12];
742 u32 ipivpr0; /* IPI Vector/Priority 0 */
743 u8 res14[12];
744 u32 ipivpr1; /* IPI Vector/Priority 1 */
745 u8 res15[12];
746 u32 ipivpr2; /* IPI Vector/Priority 2 */
747 u8 res16[12];
748 u32 ipivpr3; /* IPI Vector/Priority 3 */
749 u8 res17[12];
750 u32 svr; /* Spurious Vector */
751 u8 res18[12];
752 u32 tfrr; /* Timer Frequency Reporting */
753 u8 res19[12];
754 u32 gtccr0; /* Global Timer Current Count 0 */
755 u8 res20[12];
756 u32 gtbcr0; /* Global Timer Base Count 0 */
757 u8 res21[12];
758 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
759 u8 res22[12];
760 u32 gtdr0; /* Global Timer Destination 0 */
761 u8 res23[12];
762 u32 gtccr1; /* Global Timer Current Count 1 */
763 u8 res24[12];
764 u32 gtbcr1; /* Global Timer Base Count 1 */
765 u8 res25[12];
766 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
767 u8 res26[12];
768 u32 gtdr1; /* Global Timer Destination 1 */
769 u8 res27[12];
770 u32 gtccr2; /* Global Timer Current Count 2 */
771 u8 res28[12];
772 u32 gtbcr2; /* Global Timer Base Count 2 */
773 u8 res29[12];
774 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
775 u8 res30[12];
776 u32 gtdr2; /* Global Timer Destination 2 */
777 u8 res31[12];
778 u32 gtccr3; /* Global Timer Current Count 3 */
779 u8 res32[12];
780 u32 gtbcr3; /* Global Timer Base Count 3 */
781 u8 res33[12];
782 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
783 u8 res34[12];
784 u32 gtdr3; /* Global Timer Destination 3 */
785 u8 res35[268];
786 u32 tcr; /* Timer Control */
787 u8 res36[12];
788 u32 irqsr0; /* IRQ_OUT Summary 0 */
789 u8 res37[12];
790 u32 irqsr1; /* IRQ_OUT Summary 1 */
791 u8 res38[12];
792 u32 cisr0; /* Critical IRQ Summary 0 */
793 u8 res39[12];
794 u32 cisr1; /* Critical IRQ Summary 1 */
795 u8 res40[188];
796 u32 msgr0; /* Message 0 */
797 u8 res41[12];
798 u32 msgr1; /* Message 1 */
799 u8 res42[12];
800 u32 msgr2; /* Message 2 */
801 u8 res43[12];
802 u32 msgr3; /* Message 3 */
803 u8 res44[204];
804 u32 mer; /* Message Enable */
805 u8 res45[12];
806 u32 msr; /* Message Status */
807 u8 res46[60140];
808 u32 eivpr0; /* External IRQ Vector/Priority 0 */
809 u8 res47[12];
810 u32 eidr0; /* External IRQ Destination 0 */
811 u8 res48[12];
812 u32 eivpr1; /* External IRQ Vector/Priority 1 */
813 u8 res49[12];
814 u32 eidr1; /* External IRQ Destination 1 */
815 u8 res50[12];
816 u32 eivpr2; /* External IRQ Vector/Priority 2 */
817 u8 res51[12];
818 u32 eidr2; /* External IRQ Destination 2 */
819 u8 res52[12];
820 u32 eivpr3; /* External IRQ Vector/Priority 3 */
821 u8 res53[12];
822 u32 eidr3; /* External IRQ Destination 3 */
823 u8 res54[12];
824 u32 eivpr4; /* External IRQ Vector/Priority 4 */
825 u8 res55[12];
826 u32 eidr4; /* External IRQ Destination 4 */
827 u8 res56[12];
828 u32 eivpr5; /* External IRQ Vector/Priority 5 */
829 u8 res57[12];
830 u32 eidr5; /* External IRQ Destination 5 */
831 u8 res58[12];
832 u32 eivpr6; /* External IRQ Vector/Priority 6 */
833 u8 res59[12];
834 u32 eidr6; /* External IRQ Destination 6 */
835 u8 res60[12];
836 u32 eivpr7; /* External IRQ Vector/Priority 7 */
837 u8 res61[12];
838 u32 eidr7; /* External IRQ Destination 7 */
839 u8 res62[12];
840 u32 eivpr8; /* External IRQ Vector/Priority 8 */
841 u8 res63[12];
842 u32 eidr8; /* External IRQ Destination 8 */
843 u8 res64[12];
844 u32 eivpr9; /* External IRQ Vector/Priority 9 */
845 u8 res65[12];
846 u32 eidr9; /* External IRQ Destination 9 */
847 u8 res66[12];
848 u32 eivpr10; /* External IRQ Vector/Priority 10 */
849 u8 res67[12];
850 u32 eidr10; /* External IRQ Destination 10 */
851 u8 res68[12];
852 u32 eivpr11; /* External IRQ Vector/Priority 11 */
853 u8 res69[12];
854 u32 eidr11; /* External IRQ Destination 11 */
855 u8 res70[140];
856 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
857 u8 res71[12];
858 u32 iidr0; /* Internal IRQ Destination 0 */
859 u8 res72[12];
860 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
861 u8 res73[12];
862 u32 iidr1; /* Internal IRQ Destination 1 */
863 u8 res74[12];
864 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
865 u8 res75[12];
866 u32 iidr2; /* Internal IRQ Destination 2 */
867 u8 res76[12];
868 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
869 u8 res77[12];
870 u32 iidr3; /* Internal IRQ Destination 3 */
871 u8 res78[12];
872 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
873 u8 res79[12];
874 u32 iidr4; /* Internal IRQ Destination 4 */
875 u8 res80[12];
876 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
877 u8 res81[12];
878 u32 iidr5; /* Internal IRQ Destination 5 */
879 u8 res82[12];
880 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
881 u8 res83[12];
882 u32 iidr6; /* Internal IRQ Destination 6 */
883 u8 res84[12];
884 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
885 u8 res85[12];
886 u32 iidr7; /* Internal IRQ Destination 7 */
887 u8 res86[12];
888 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
889 u8 res87[12];
890 u32 iidr8; /* Internal IRQ Destination 8 */
891 u8 res88[12];
892 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
893 u8 res89[12];
894 u32 iidr9; /* Internal IRQ Destination 9 */
895 u8 res90[12];
896 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
897 u8 res91[12];
898 u32 iidr10; /* Internal IRQ Destination 10 */
899 u8 res92[12];
900 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
901 u8 res93[12];
902 u32 iidr11; /* Internal IRQ Destination 11 */
903 u8 res94[12];
904 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
905 u8 res95[12];
906 u32 iidr12; /* Internal IRQ Destination 12 */
907 u8 res96[12];
908 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
909 u8 res97[12];
910 u32 iidr13; /* Internal IRQ Destination 13 */
911 u8 res98[12];
912 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
913 u8 res99[12];
914 u32 iidr14; /* Internal IRQ Destination 14 */
915 u8 res100[12];
916 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
917 u8 res101[12];
918 u32 iidr15; /* Internal IRQ Destination 15 */
919 u8 res102[12];
920 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
921 u8 res103[12];
922 u32 iidr16; /* Internal IRQ Destination 16 */
923 u8 res104[12];
924 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
925 u8 res105[12];
926 u32 iidr17; /* Internal IRQ Destination 17 */
927 u8 res106[12];
928 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
929 u8 res107[12];
930 u32 iidr18; /* Internal IRQ Destination 18 */
931 u8 res108[12];
932 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
933 u8 res109[12];
934 u32 iidr19; /* Internal IRQ Destination 19 */
935 u8 res110[12];
936 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
937 u8 res111[12];
938 u32 iidr20; /* Internal IRQ Destination 20 */
939 u8 res112[12];
940 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
941 u8 res113[12];
942 u32 iidr21; /* Internal IRQ Destination 21 */
943 u8 res114[12];
944 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
945 u8 res115[12];
946 u32 iidr22; /* Internal IRQ Destination 22 */
947 u8 res116[12];
948 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
949 u8 res117[12];
950 u32 iidr23; /* Internal IRQ Destination 23 */
951 u8 res118[12];
952 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
953 u8 res119[12];
954 u32 iidr24; /* Internal IRQ Destination 24 */
955 u8 res120[12];
956 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
957 u8 res121[12];
958 u32 iidr25; /* Internal IRQ Destination 25 */
959 u8 res122[12];
960 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
961 u8 res123[12];
962 u32 iidr26; /* Internal IRQ Destination 26 */
963 u8 res124[12];
964 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
965 u8 res125[12];
966 u32 iidr27; /* Internal IRQ Destination 27 */
967 u8 res126[12];
968 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
969 u8 res127[12];
970 u32 iidr28; /* Internal IRQ Destination 28 */
971 u8 res128[12];
972 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
973 u8 res129[12];
974 u32 iidr29; /* Internal IRQ Destination 29 */
975 u8 res130[12];
976 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
977 u8 res131[12];
978 u32 iidr30; /* Internal IRQ Destination 30 */
979 u8 res132[12];
980 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
981 u8 res133[12];
982 u32 iidr31; /* Internal IRQ Destination 31 */
983 u8 res134[4108];
984 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
985 u8 res135[12];
986 u32 midr0; /* Messaging IRQ Destination 0 */
987 u8 res136[12];
988 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
989 u8 res137[12];
990 u32 midr1; /* Messaging IRQ Destination 1 */
991 u8 res138[12];
992 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
993 u8 res139[12];
994 u32 midr2; /* Messaging IRQ Destination 2 */
995 u8 res140[12];
996 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
997 u8 res141[12];
998 u32 midr3; /* Messaging IRQ Destination 3 */
999 u8 res142[59852];
1000 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
1001 u8 res143[12];
1002 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
1003 u8 res144[12];
1004 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
1005 u8 res145[12];
1006 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
1007 u8 res146[12];
1008 u32 ctpr0; /* Current Task Priority for Processor 0 */
1009 u8 res147[12];
1010 u32 whoami0; /* Who Am I for Processor 0 */
1011 u8 res148[12];
1012 u32 iack0; /* IRQ Acknowledge for Processor 0 */
1013 u8 res149[12];
1014 u32 eoi0; /* End Of IRQ for Processor 0 */
1015 u8 res150[130892];
42d1f039
WD		 1016} ccsr_pic_t;
1017
8280912e 1018/* CPM Block */
9c4c5ae3 1019#ifndef CONFIG_CPM2
42d1f039 1020typedef struct ccsr_cpm {
8280912e 1021 u8 res[262144];
42d1f039
WD		 1022} ccsr_cpm_t;
1023#else
de1d0a69 1024/*
8280912e
KG		 1025 * DPARM
1026 * General SIU
de1d0a69 1027 */
42d1f039 1028typedef struct ccsr_cpm_siu {
8280912e
KG		 1029 u8 res1[80];
1030 u32 smaer;
1031 u32 smser;
1032 u32 smevr;
1033 u8 res2[4];
1034 u32 lmaer;
1035 u32 lmser;
1036 u32 lmevr;
1037 u8 res3[2964];
42d1f039
WD		 1038} ccsr_cpm_siu_t;
1039
8280912e 1040/* IRQ Controller */
42d1f039 1041typedef struct ccsr_cpm_intctl {
8280912e
KG		 1042 u16 sicr;
1043 u8 res1[2];
1044 u32 sivec;
1045 u32 sipnrh;
1046 u32 sipnrl;
1047 u32 siprr;
1048 u32 scprrh;
1049 u32 scprrl;
1050 u32 simrh;
1051 u32 simrl;
1052 u32 siexr;
1053 u8 res2[88];
1054 u32 sccr;
1055 u8 res3[124];
42d1f039
WD		 1056} ccsr_cpm_intctl_t;
1057
8280912e 1058/* input/output port */
42d1f039 1059typedef struct ccsr_cpm_iop {
8280912e
KG		 1060 u32 pdira;
1061 u32 ppara;
1062 u32 psora;
1063 u32 podra;
1064 u32 pdata;
1065 u8 res1[12];
1066 u32 pdirb;
1067 u32 pparb;
1068 u32 psorb;
1069 u32 podrb;
1070 u32 pdatb;
1071 u8 res2[12];
1072 u32 pdirc;
1073 u32 pparc;
1074 u32 psorc;
1075 u32 podrc;
1076 u32 pdatc;
1077 u8 res3[12];
1078 u32 pdird;
1079 u32 ppard;
1080 u32 psord;
1081 u32 podrd;
1082 u32 pdatd;
1083 u8 res4[12];
42d1f039
WD		 1084} ccsr_cpm_iop_t;
1085
8280912e 1086/* CPM timers */
42d1f039 1087typedef struct ccsr_cpm_timer {
8280912e
KG		 1088 u8 tgcr1;
1089 u8 res1[3];
1090 u8 tgcr2;
1091 u8 res2[11];
1092 u16 tmr1;
1093 u16 tmr2;
1094 u16 trr1;
1095 u16 trr2;
1096 u16 tcr1;
1097 u16 tcr2;
1098 u16 tcn1;
1099 u16 tcn2;
1100 u16 tmr3;
1101 u16 tmr4;
1102 u16 trr3;
1103 u16 trr4;
1104 u16 tcr3;
1105 u16 tcr4;
1106 u16 tcn3;
1107 u16 tcn4;
1108 u16 ter1;
1109 u16 ter2;
1110 u16 ter3;
1111 u16 ter4;
1112 u8 res3[608];
42d1f039
WD		 1113} ccsr_cpm_timer_t;
1114
8280912e 1115/* SDMA */
42d1f039 1116typedef struct ccsr_cpm_sdma {
8280912e
KG		 1117 u8 sdsr;
1118 u8 res1[3];
1119 u8 sdmr;
1120 u8 res2[739];
42d1f039
WD		 1121} ccsr_cpm_sdma_t;
1122
8280912e 1123/* FCC1 */
42d1f039 1124typedef struct ccsr_cpm_fcc1 {
8280912e
KG		 1125 u32 gfmr;
1126 u32 fpsmr;
1127 u16 ftodr;
1128 u8 res1[2];
1129 u16 fdsr;
1130 u8 res2[2];
1131 u16 fcce;
1132 u8 res3[2];
1133 u16 fccm;
1134 u8 res4[2];
1135 u8 fccs;
1136 u8 res5[3];
1137 u8 ftirr_phy[4];
42d1f039
WD		 1138} ccsr_cpm_fcc1_t;
1139
8280912e 1140/* FCC2 */
42d1f039 1141typedef struct ccsr_cpm_fcc2 {
8280912e
KG		 1142 u32 gfmr;
1143 u32 fpsmr;
1144 u16 ftodr;
1145 u8 res1[2];
1146 u16 fdsr;
1147 u8 res2[2];
1148 u16 fcce;
1149 u8 res3[2];
1150 u16 fccm;
1151 u8 res4[2];
1152 u8 fccs;
1153 u8 res5[3];
1154 u8 ftirr_phy[4];
42d1f039
WD		 1155} ccsr_cpm_fcc2_t;
1156
8280912e 1157/* FCC3 */
42d1f039 1158typedef struct ccsr_cpm_fcc3 {
8280912e
KG		 1159 u32 gfmr;
1160 u32 fpsmr;
1161 u16 ftodr;
1162 u8 res1[2];
1163 u16 fdsr;
1164 u8 res2[2];
1165 u16 fcce;
1166 u8 res3[2];
1167 u16 fccm;
1168 u8 res4[2];
1169 u8 fccs;
1170 u8 res5[3];
1171 u8 res[36];
42d1f039
WD		 1172} ccsr_cpm_fcc3_t;
1173
8280912e 1174/* FCC1 extended */
42d1f039 1175typedef struct ccsr_cpm_fcc1_ext {
8280912e
KG		 1176 u32 firper;
1177 u32 firer;
1178 u32 firsr_h;
1179 u32 firsr_l;
1180 u8 gfemr;
1181 u8 res[15];
42d1f039
WD		 1182
1183} ccsr_cpm_fcc1_ext_t;
1184
8280912e 1185/* FCC2 extended */
42d1f039 1186typedef struct ccsr_cpm_fcc2_ext {
8280912e
KG		 1187 u32 firper;
1188 u32 firer;
1189 u32 firsr_h;
1190 u32 firsr_l;
1191 u8 gfemr;
1192 u8 res[31];
42d1f039
WD		 1193} ccsr_cpm_fcc2_ext_t;
1194
8280912e 1195/* FCC3 extended */
42d1f039 1196typedef struct ccsr_cpm_fcc3_ext {
8280912e
KG		 1197 u8 gfemr;
1198 u8 res[47];
42d1f039
WD		 1199} ccsr_cpm_fcc3_ext_t;
1200
8280912e 1201/* TC layers */
42d1f039 1202typedef struct ccsr_cpm_tmp1 {
8280912e 1203 u8 res[496];
42d1f039
WD		 1204} ccsr_cpm_tmp1_t;
1205
8280912e 1206/* BRGs:5,6,7,8 */
42d1f039 1207typedef struct ccsr_cpm_brg2 {
8280912e
KG		 1208 u32 brgc5;
1209 u32 brgc6;
1210 u32 brgc7;
1211 u32 brgc8;
1212 u8 res[608];
42d1f039
WD		 1213} ccsr_cpm_brg2_t;
1214
8280912e 1215/* I2C */
42d1f039 1216typedef struct ccsr_cpm_i2c {
8280912e
KG		 1217 u8 i2mod;
1218 u8 res1[3];
1219 u8 i2add;
1220 u8 res2[3];
1221 u8 i2brg;
1222 u8 res3[3];
1223 u8 i2com;
1224 u8 res4[3];
1225 u8 i2cer;
1226 u8 res5[3];
1227 u8 i2cmr;
1228 u8 res6[331];
42d1f039
WD		 1229} ccsr_cpm_i2c_t;
1230
8280912e 1231/* CPM core */
42d1f039 1232typedef struct ccsr_cpm_cp {
8280912e
KG		 1233 u32 cpcr;
1234 u32 rccr;
1235 u8 res1[14];
1236 u16 rter;
1237 u8 res2[2];
1238 u16 rtmr;
1239 u16 rtscr;
1240 u8 res3[2];
1241 u32 rtsr;
1242 u8 res4[12];
42d1f039
WD		 1243} ccsr_cpm_cp_t;
1244
8280912e 1245/* BRGs:1,2,3,4 */
42d1f039 1246typedef struct ccsr_cpm_brg1 {
8280912e
KG		 1247 u32 brgc1;
1248 u32 brgc2;
1249 u32 brgc3;
1250 u32 brgc4;
42d1f039
WD		 1251} ccsr_cpm_brg1_t;
1252
8280912e 1253/* SCC1-SCC4 */
42d1f039 1254typedef struct ccsr_cpm_scc {
8280912e
KG		 1255 u32 gsmrl;
1256 u32 gsmrh;
1257 u16 psmr;
1258 u8 res1[2];
1259 u16 todr;
1260 u16 dsr;
1261 u16 scce;
1262 u8 res2[2];
1263 u16 sccm;
1264 u8 res3;
1265 u8 sccs;
1266 u8 res4[8];
42d1f039
WD		 1267} ccsr_cpm_scc_t;
1268
42d1f039 1269typedef struct ccsr_cpm_tmp2 {
8280912e 1270 u8 res[32];
42d1f039
WD		 1271} ccsr_cpm_tmp2_t;
1272
8280912e 1273/* SPI */
42d1f039 1274typedef struct ccsr_cpm_spi {
8280912e
KG		 1275 u16 spmode;
1276 u8 res1[4];
1277 u8 spie;
1278 u8 res2[3];
1279 u8 spim;
1280 u8 res3[2];
1281 u8 spcom;
1282 u8 res4[82];
42d1f039
WD		 1283} ccsr_cpm_spi_t;
1284
8280912e 1285/* CPM MUX */
42d1f039 1286typedef struct ccsr_cpm_mux {
8280912e
KG		 1287 u8 cmxsi1cr;
1288 u8 res1;
1289 u8 cmxsi2cr;
1290 u8 res2;
1291 u32 cmxfcr;
1292 u32 cmxscr;
1293 u8 res3[2];
1294 u16 cmxuar;
1295 u8 res4[16];
42d1f039
WD		 1296} ccsr_cpm_mux_t;
1297
8280912e 1298/* SI,MCC,etc */
42d1f039 1299typedef struct ccsr_cpm_tmp3 {
8280912e 1300 u8 res[58592];
42d1f039
WD		 1301} ccsr_cpm_tmp3_t;
1302
1303typedef struct ccsr_cpm_iram {
8280912e
KG		 1304 u32 iram[8192];
1305 u8 res[98304];
42d1f039
WD		 1306} ccsr_cpm_iram_t;
1307
1308typedef struct ccsr_cpm {
8280912e 1309 /* Some references are into the unique & known dpram spaces,
42d1f039
WD		 1310 * others are from the generic base.
1311 */
53677ef1 1312#define im_dprambase im_dpram1
8280912e
KG		 1313 u8 im_dpram1[16*1024];
1314 u8 res1[16*1024];
1315 u8 im_dpram2[16*1024];
1316 u8 res2[16*1024];
1317 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1318 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1319 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1320 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1321 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
42d1f039
WD		 1322 ccsr_cpm_fcc1_t im_cpm_fcc1;
1323 ccsr_cpm_fcc2_t im_cpm_fcc2;
1324 ccsr_cpm_fcc3_t im_cpm_fcc3;
1325 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1326 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1327 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1328 ccsr_cpm_tmp1_t im_cpm_tmp1;
1329 ccsr_cpm_brg2_t im_cpm_brg2;
1330 ccsr_cpm_i2c_t im_cpm_i2c;
1331 ccsr_cpm_cp_t im_cpm_cp;
1332 ccsr_cpm_brg1_t im_cpm_brg1;
1333 ccsr_cpm_scc_t im_cpm_scc[4];
1334 ccsr_cpm_tmp2_t im_cpm_tmp2;
1335 ccsr_cpm_spi_t im_cpm_spi;
1336 ccsr_cpm_mux_t im_cpm_mux;
1337 ccsr_cpm_tmp3_t im_cpm_tmp3;
1338 ccsr_cpm_iram_t im_cpm_iram;
1339} ccsr_cpm_t;
1340#endif
42d1f039 1341
7d67ed58
LG		 1342#ifdef CONFIG_SYS_SRIO
1343/* Architectural regsiters */
1344struct rio_arch {
1345 u32 didcar; /* Device Identity CAR */
1346 u32 dicar; /* Device Information CAR */
1347 u32 aidcar; /* Assembly Identity CAR */
1348 u32 aicar; /* Assembly Information CAR */
1349 u32 pefcar; /* Processing Element Features CAR */
1350 u8 res0[4];
1351 u32 socar; /* Source Operations CAR */
1352 u32 docar; /* Destination Operations CAR */
8280912e 1353 u8 res1[32];
7d67ed58
LG		 1354 u32 mcsr; /* Mailbox CSR */
1355 u32 pwdcsr; /* Port-Write and Doorbell CSR */
8280912e
KG		 1356 u8 res2[4];
1357 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1358 u8 res3[12];
7d67ed58
LG		 1359 u32 lcsbacsr; /* Local Configuration Space BACSR */
1360 u32 bdidcsr; /* Base Device ID CSR */
8280912e 1361 u8 res4[4];
7d67ed58
LG		 1362 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1363 u32 ctcsr; /* Component Tag CSR */
1364};
1365
1366/* Extended Features Space: 1x/4x LP-Serial Port registers */
1367struct rio_lp_serial_port {
1368 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1369 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1370 u32 plascsr; /* Port Local Ackid Status CSR */
1371 u8 res0[12];
1372 u32 pescsr; /* Port Error and Status CSR */
1373 u32 pccsr; /* Port Control CSR */
1374};
1375
1376/* Extended Features Space: 1x/4x LP-Serial registers */
1377struct rio_lp_serial {
1378 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1379 u8 res0[28];
1380 u32 pltoccsr; /* Port Link Time-out CCSR */
1381 u32 prtoccsr; /* Port Response Time-out CCSR */
1382 u8 res1[20];
1383 u32 pgccsr; /* Port General CSR */
1384 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1385};
1386
1387/* Logical error reporting registers */
1388struct rio_logical_err {
1389 u32 erbh; /* Error Reporting Block Header Register */
1390 u8 res0[4];
1391 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1392 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1393 u8 res1[4];
1394 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1395 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1396 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1397};
1398
1399/* Physical error reporting port registers */
1400struct rio_phys_err_port {
1401 u32 edcsr; /* Port error detect CSR */
1402 u32 erecsr; /* Port error rate enable CSR */
1403 u32 ecacsr; /* Port error capture attributes CSR */
1404 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1405 u32 peccsr[3]; /* Port error capture CSR */
1406 u8 res0[12];
1407 u32 ercsr; /* Port error rate CSR */
1408 u32 ertcsr; /* Port error rate threshold CSR */
1409 u8 res1[16];
1410};
1411
1412/* Physical error reporting registers */
1413struct rio_phys_err {
1414 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1415};
1416
1417/* Implementation Space: General Port-Common */
1418struct rio_impl_common {
1419 u8 res0[4];
1420 u32 llcr; /* Logical Layer Configuration Register */
1421 u8 res1[8];
1422 u32 epwisr; /* Error / Port-Write Interrupt SR */
1423 u8 res2[12];
1424 u32 lretcr; /* Logical Retry Error Threshold CR */
1425 u8 res3[92];
1426 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1427 u8 res4[124];
1428};
1429
1430/* Implementation Space: Port Specific */
1431struct rio_impl_port_spec {
1432 u32 adidcsr; /* Port Alt. Device ID CSR */
1433 u8 res0[28];
1434 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1435 u32 lopttlcr;
1436 u8 res1[8];
1437 u32 iecsr; /* Port Implementation Error CSR */
1438 u8 res2[12];
1439 u32 pcr; /* Port Phsyical Configuration Register */
1440 u8 res3[20];
1441 u32 slcsr; /* Port Serial Link CSR */
1442 u8 res4[4];
1443 u32 sleicr; /* Port Serial Link Error Injection */
1444 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1445 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1446 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1447 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1448 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1449};
1450
1451/* Implementation Space: register */
1452struct rio_implement {
1453 struct rio_impl_common com;
1454 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1455};
1456
1457/* Revision Control Register */
1458struct rio_rev_ctrl {
1459 u32 ipbrr[2]; /* IP Block Revision Register */
1460};
1461
1462struct rio_atmu_row {
1463 u32 rowtar; /* RapidIO Outbound Window TAR */
1464 u32 rowtear; /* RapidIO Outbound Window TEAR */
1465 u32 rowbar;
1466 u8 res0[4];
1467 u32 rowar; /* RapidIO Outbound Attributes Register */
1468 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1469};
1470
1471struct rio_atmu_riw {
1472 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1473 u8 res0[4];
1474 u32 riwbar; /* RapidIO Inbound Window Base AR */
1475 u8 res1[4];
1476 u32 riwar; /* RapidIO Inbound Attributes Register */
1477 u8 res2[12];
1478};
1479
1480/* ATMU window registers */
1481struct rio_atmu_win {
1482 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1483 u8 res0[64];
1484 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1485};
1486
1487struct rio_atmu {
1488 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1489};
1490
1491#ifdef CONFIG_SYS_FSL_RMU
1492struct rio_msg {
1493 u32 omr; /* Outbound Mode Register */
1494 u32 osr; /* Outbound Status Register */
1495 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1496 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1497 u32 eosar; /* Extended Outbound Unit Source AR */
1498 u32 osar; /* Outbound Unit Source AR */
1499 u32 odpr; /* Outbound Destination Port Register */
1500 u32 odatr; /* Outbound Destination Attributes Register */
1501 u32 odcr; /* Outbound Doubleword Count Register */
1502 u32 eodqepar; /* Extended Outbound DQ EPAR */
1503 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1504 u32 oretr; /* Outbound Retry Error Threshold Register */
1505 u32 omgr; /* Outbound Multicast Group Register */
1506 u32 omlr; /* Outbound Multicast List Register */
1507 u8 res0[40];
1508 u32 imr; /* Outbound Mode Register */
1509 u32 isr; /* Inbound Status Register */
1510 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1511 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1512 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1513 u32 ifqepar; /* Inbound Frame Queue EPAR */
1514 u32 imirir; /* Inbound Maximum Interrutp RIR */
1515 u8 res1[4];
1516 u32 eihqepar; /* Extended inbound message header queue EPAR */
1517 u32 ihqepar; /* Inbound message header queue EPAR */
1518 u8 res2[120];
1519};
1520
1521struct rio_dbell {
1522 u32 odmr; /* Outbound Doorbell Mode Register */
1523 u32 odsr; /* Outbound Doorbell Status Register */
1524 u8 res0[16];
1525 u32 oddpr; /* Outbound Doorbell Destination Port */
1526 u32 oddatr; /* Outbound Doorbell Destination AR */
1527 u8 res1[12];
1528 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1529 u8 res2[48];
1530 u32 idmr; /* Inbound Doorbell Mode Register */
1531 u32 idsr; /* Inbound Doorbell Status Register */
1532 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1533 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1534 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1535 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1536 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1537};
1538
1539struct rio_pw {
1540 u32 pwmr; /* Port-Write Mode Register */
1541 u32 pwsr; /* Port-Write Status Register */
1542 u32 epwqbar; /* Extended Port-Write Queue BAR */
1543 u32 pwqbar; /* Port-Write Queue Base Address Register */
1544};
1545#endif
1546
1547/* RapidIO Registers */
1548struct ccsr_rio {
1549 struct rio_arch arch;
1550 u8 res0[144];
1551 struct rio_lp_serial lp_serial;
1552 u8 res1[1152];
1553 struct rio_logical_err logical_err;
1554 u8 res2[32];
1555 struct rio_phys_err phys_err;
1556 u8 res3[63808];
1557 struct rio_implement impl;
1558 u8 res4[2552];
1559 struct rio_rev_ctrl rev;
1560 struct rio_atmu atmu;
1561#ifdef CONFIG_SYS_FSL_RMU
1562 u8 res5[8192];
1563 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1564 u8 res6[512];
1565 struct rio_dbell dbell;
1566 u8 res7[100];
1567 struct rio_pw pw;
1568#endif
1569};
1570#endif
42d1f039 1571
8280912e 1572/* Quick Engine Block Pin Muxing Registers */
c59e4091 1573typedef struct par_io {
8280912e
KG		 1574 u32 cpodr;
1575 u32 cpdat;
1576 u32 cpdir1;
1577 u32 cpdir2;
1578 u32 cppar1;
1579 u32 cppar2;
1580 u8 res[8];
1581} par_io_t;
c59e4091 1582
8b0ab304
BB		 1583#ifdef CONFIG_SYS_FSL_CPC
1584/*
1585 * Define a single offset that is the start of all the CPC register
1586 * blocks - if there is more than one CPC, we expect these to be
1587 * contiguous 4k regions
1588 */
1589
1590typedef struct cpc_corenet {
1591 u32 cpccsr0; /* Config/status reg */
1592 u32 res1;
1593 u32 cpccfg0; /* Configuration register */
1594 u32 res2;
1595 u32 cpcewcr0; /* External Write reg 0 */
1596 u32 cpcewabr0; /* External write base reg 0 */
1597 u32 res3[2];
1598 u32 cpcewcr1; /* External Write reg 1 */
1599 u32 cpcewabr1; /* External write base reg 1 */
1600 u32 res4[54];
1601 u32 cpcsrcr1; /* SRAM control reg 1 */
1602 u32 cpcsrcr0; /* SRAM control reg 0 */
1603 u32 res5[62];
1604 struct {
1605 u32 id; /* partition ID */
1606 u32 res;
1607 u32 alloc; /* partition allocation */
1608 u32 way; /* partition way */
1609 } partition_regs[16];
1610 u32 res6[704];
1611 u32 cpcerrinjhi; /* Error injection high */
1612 u32 cpcerrinjlo; /* Error injection lo */
1613 u32 cpcerrinjctl; /* Error injection control */
1614 u32 res7[5];
1615 u32 cpccaptdatahi; /* capture data high */
1616 u32 cpccaptdatalo; /* capture data low */
1617 u32 cpcaptecc; /* capture ECC */
1618 u32 res8[5];
1619 u32 cpcerrdet; /* error detect */
1620 u32 cpcerrdis; /* error disable */
1621 u32 cpcerrinten; /* errir interrupt enable */
1622 u32 cpcerrattr; /* error attribute */
1623 u32 cpcerreaddr; /* error extended address */
1624 u32 cpcerraddr; /* error address */
1625 u32 cpcerrctl; /* error control */
3c6a22b9
KG		 1626 u32 res9[41]; /* pad out to 4k */
1627 u32 cpchdbcr0; /* hardware debug control register 0 */
1628 u32 res10[63]; /* pad out to 4k */
8b0ab304
BB		 1629} cpc_corenet_t;
1630
1631#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1632#define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1633#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1634#define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1635#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1636#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1637#define CPC_CFG0_SZ_MASK 0x00003fff
1638#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1639#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1640#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1641#define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1642#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1643 & CPC_SRCR1_SRBARU_MASK)
1644#define CPC_SRCR0_SRBARL_MASK 0xffff8000
1645#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1646#define CPC_SRCR0_INTLVEN 0x00000100
1647#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1648#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1649#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1650#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1651#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1652#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1653#define CPC_SRCR0_SRAMEN 0x00000001
1654#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
3c6a22b9 1655#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1d2c2a62 1656#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
868da593 1657#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
8b0ab304
BB		 1658#endif /* CONFIG_SYS_FSL_CPC */
1659
8280912e 1660/* Global Utilities Block */
01df5212
KG		 1661#ifdef CONFIG_FSL_CORENET
1662typedef struct ccsr_gur {
45c18853
YS		 1663 u32 porsr1; /* POR status 1 */
1664 u32 porsr2; /* POR status 2 */
1665 u8 res_008[0x20-0x8];
8280912e 1666 u32 gpporcr1; /* General-purpose POR configuration */
45c18853
YS		 1667 u32 gpporcr2; /* General-purpose POR configuration 2 */
1668 u32 dcfg_fusesr; /* Fuse status register */
1669#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1670#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1671#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1672#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1673 u8 res_02c[0x70-0x2c];
8280912e 1674 u32 devdisr; /* Device disable control */
9e758758
YS		 1675 u32 devdisr2; /* Device disable control 2 */
1676 u32 devdisr3; /* Device disable control 3 */
1677 u32 devdisr4; /* Device disable control 4 */
1678#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1679 u32 devdisr5; /* Device disable control 5 */
1680#define FSL_CORENET_DEVDISR_PBL 0x80000000
1681#define FSL_CORENET_DEVDISR_PMAN 0x40000000
1682#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1683#define FSL_CORENET_DEVDISR_DMA1 0x00800000
1684#define FSL_CORENET_DEVDISR_DMA2 0x00400000
1685#define FSL_CORENET_DEVDISR_USB1 0x00080000
1686#define FSL_CORENET_DEVDISR_USB2 0x00040000
1687#define FSL_CORENET_DEVDISR_SATA1 0x00008000
1688#define FSL_CORENET_DEVDISR_SATA2 0x00004000
1689#define FSL_CORENET_DEVDISR_PME 0x00000800
1690#define FSL_CORENET_DEVDISR_SEC 0x00000200
1691#define FSL_CORENET_DEVDISR_RMU 0x00000080
1692#define FSL_CORENET_DEVDISR_DCE 0x00000040
1693#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1694#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1695#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1696#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1697#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1698#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1699#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1700#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1701#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1702#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1703#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1704#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1705#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1706#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1707#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1708#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1709#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1710#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1711#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1712#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1713#define FSL_CORENET_DEVDISR2_FM1 0x00000080
1714#define FSL_CORENET_DEVDISR2_FM2 0x00000040
d2404141 1715#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
9e758758
YS		 1716#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1717#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1718#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1719#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1720#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1721#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1722#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1723#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1724#define FSL_CORENET_DEVDISR3_LA1 0x00008000
d2404141
YS		 1725#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1726#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1727#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
9e758758
YS		 1728#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1729#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1730#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1731#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1732#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1733#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1734#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1735#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1736#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1737#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1738#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1739#define FSL_CORENET_DEVDISR5_IFC 0x00800000
1740#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1741#define FSL_CORENET_DEVDISR5_DBG 0x00200000
1742#define FSL_CORENET_DEVDISR5_NAL 0x00100000
d2404141 1743#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
9e758758
YS		 1744#define FSL_CORENET_NUM_DEVDISR 5
1745#else
01df5212
KG		 1746#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1747#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1748#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
9ab87d04 1749#define FSL_CORENET_DEVDISR_PCIE4 0x10000000
01df5212
KG		 1750#define FSL_CORENET_DEVDISR_RMU 0x08000000
1751#define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1752#define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1753#define FSL_CORENET_DEVDISR_DMA1 0x00400000
1754#define FSL_CORENET_DEVDISR_DMA2 0x00200000
1755#define FSL_CORENET_DEVDISR_DDR1 0x00100000
1756#define FSL_CORENET_DEVDISR_DDR2 0x00080000
1757#define FSL_CORENET_DEVDISR_DBG 0x00010000
1758#define FSL_CORENET_DEVDISR_NAL 0x00008000
9ab87d04
KG		 1759#define FSL_CORENET_DEVDISR_SATA1 0x00004000
1760#define FSL_CORENET_DEVDISR_SATA2 0x00002000
01df5212
KG		 1761#define FSL_CORENET_DEVDISR_ELBC 0x00001000
1762#define FSL_CORENET_DEVDISR_USB1 0x00000800
1763#define FSL_CORENET_DEVDISR_USB2 0x00000400
1764#define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1765#define FSL_CORENET_DEVDISR_GPIO 0x00000080
1766#define FSL_CORENET_DEVDISR_ESPI 0x00000040
1767#define FSL_CORENET_DEVDISR_I2C1 0x00000020
1768#define FSL_CORENET_DEVDISR_I2C2 0x00000010
1769#define FSL_CORENET_DEVDISR_DUART1 0x00000002
1770#define FSL_CORENET_DEVDISR_DUART2 0x00000001
1231c498
KG		 1771#define FSL_CORENET_DEVDISR2_PME 0x80000000
1772#define FSL_CORENET_DEVDISR2_SEC 0x40000000
1773#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1774#define FSL_CORENET_DEVDISR2_FM1 0x02000000
1775#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1776#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1777#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1778#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1779#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
9ab87d04 1780#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1231c498
KG		 1781#define FSL_CORENET_DEVDISR2_FM2 0x00020000
1782#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1783#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1784#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1785#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1786#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
99abf7de 1787#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
9ab87d04 1788#define FSL_CORENET_NUM_DEVDISR 2
8280912e 1789 u32 powmgtcsr; /* Power management status & control */
9e758758 1790#endif
01df5212 1791 u8 res8[12];
8280912e
KG		 1792 u32 coredisru; /* uppper portion for support of 64 cores */
1793 u32 coredisrl; /* lower portion for support of 64 cores */
01df5212 1794 u8 res9[8];
8280912e
KG		 1795 u32 pvr; /* Processor version */
1796 u32 svr; /* System version */
01df5212 1797 u8 res10[8];
8280912e
KG		 1798 u32 rstcr; /* Reset control */
1799 u32 rstrqpblsr; /* Reset request preboot loader status */
01df5212 1800 u8 res11[8];
8280912e
KG		 1801 u32 rstrqmr1; /* Reset request mask */
1802 u8 res12[4];
1803 u32 rstrqsr1; /* Reset request status */
1804 u8 res13[4];
1805 u8 res14[4];
1806 u32 rstrqwdtmrl; /* Reset request WDT mask */
1807 u8 res15[4];
1808 u32 rstrqwdtsrl; /* Reset request WDT status */
1809 u8 res16[4];
1810 u32 brrl; /* Boot release */
01df5212 1811 u8 res17[24];
8280912e 1812 u32 rcwsr[16]; /* Reset control word status */
fd3cebd0
YS		 1813
1814#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
f77329cf
YS		 1815#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1816#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
b6240846 1817#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
fd3cebd0
YS		 1818#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1819#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1820#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1821#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1822#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1823#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1824#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1825#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
69fdf900 1826#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
e1dbdd81 1827#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
d2404141
YS		 1828#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1829#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1830#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1831#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
5870fe44 1832#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
5f208d11
YS		 1833#elif defined(CONFIG_PPC_T1040)
1834#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1835#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1836#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1837#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
9e758758 1838#endif
fd3cebd0
YS		 1839#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1840#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1841#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1842#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1843#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1844#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1845#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1846#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1847
1848#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1849#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1850#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
01df5212 1851#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
ab48ca1a
SS		 1852#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1853#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1231c498 1854#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
4905443f 1855#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
81fa73ba 1856#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
9ab87d04
KG		 1857#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1858#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
fd3cebd0
YS		 1859#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1860
01df5212
KG		 1861#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1862#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1863#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
9ab87d04 1864#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
055ce080 1865#ifdef CONFIG_PPC_P4080
c916d7c9
KG		 1866#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1867#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
9ab87d04 1868#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
c916d7c9
KG		 1869#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1870#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1871#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1872#endif
3e978f5d 1873#if defined(CONFIG_PPC_P2041) \
c916d7c9
KG		 1874 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1875#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1876#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1877#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1878#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1879#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1880#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1881#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
4905443f
TT		 1882#endif
1883#if defined(CONFIG_PPC_P5040)
1884#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1885#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1886#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1887#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1888#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1889#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1890#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
9e758758 1891#endif
b6240846 1892#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
9e758758
YS		 1893#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1894#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1895#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1896#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1897#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1898#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1899#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
c916d7c9 1900#endif
8280912e
KG		 1901 u8 res18[192];
1902 u32 scratchrw[4]; /* Scratch Read/Write */
1903 u8 res19[240];
1904 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1905 u8 res20[240];
1906 u32 scrtsr[8]; /* Core reset status */
1907 u8 res21[224];
1908 u32 pex1liodnr; /* PCI Express 1 LIODN */
1909 u32 pex2liodnr; /* PCI Express 2 LIODN */
1910 u32 pex3liodnr; /* PCI Express 3 LIODN */
1911 u32 pex4liodnr; /* PCI Express 4 LIODN */
1912 u32 rio1liodnr; /* RIO 1 LIODN */
1913 u32 rio2liodnr; /* RIO 2 LIODN */
1914 u32 rio3liodnr; /* RIO 3 LIODN */
1915 u32 rio4liodnr; /* RIO 4 LIODN */
1916 u32 usb1liodnr; /* USB 1 LIODN */
1917 u32 usb2liodnr; /* USB 2 LIODN */
1918 u32 usb3liodnr; /* USB 3 LIODN */
1919 u32 usb4liodnr; /* USB 4 LIODN */
1920 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1921 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1922 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1923 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
9ab87d04
KG		 1924 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1925 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1926 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1927 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1928 u32 sata1liodnr; /* SATA 1 LIODN */
1929 u32 sata2liodnr; /* SATA 2 LIODN */
1930 u32 sata3liodnr; /* SATA 3 LIODN */
1931 u32 sata4liodnr; /* SATA 4 LIODN */
1932 u8 res22[32];
8280912e
KG		 1933 u32 dma1liodnr; /* DMA 1 LIODN */
1934 u32 dma2liodnr; /* DMA 2 LIODN */
1935 u32 dma3liodnr; /* DMA 3 LIODN */
1936 u32 dma4liodnr; /* DMA 4 LIODN */
1937 u8 res23[48];
1938 u8 res24[64];
1939 u32 pblsr; /* Preboot loader status */
1940 u32 pamubypenr; /* PAMU bypass enable */
1941 u32 dmacr1; /* DMA control */
1942 u8 res25[4];
1943 u32 gensr1; /* General status */
1944 u8 res26[12];
1945 u32 gencr1; /* General control */
1946 u8 res27[12];
1947 u8 res28[4];
1948 u32 cgensrl; /* Core general status */
1949 u8 res29[8];
1950 u8 res30[4];
1951 u32 cgencrl; /* Core general control */
1952 u8 res31[184];
1953 u32 sriopstecr; /* SRIO prescaler timer enable control */
f110fe94 1954 u32 dcsrcr; /* DCSR Control register */
1ca8690d
YS		 1955 u8 res31a[56];
1956 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1957 struct {
1958 u32 upper;
1959 u32 lower;
1960 } tp_cluster[16]; /* Core Cluster n Topology Register */
1961 u8 res32[1344];
17d90f31
DL		 1962 u32 pmuxcr; /* Pin multiplexing control */
1963 u8 res33[60];
1964 u32 iovselsr; /* I/O voltage selection status */
1965 u8 res34[28];
1966 u32 ddrclkdr; /* DDR clock disable */
1967 u8 res35;
1968 u32 elbcclkdr; /* eLBC clock disable */
1969 u8 res36[20];
1970 u32 sdhcpcr; /* eSDHC polarity configuration */
1971 u8 res37[380];
01df5212
KG		 1972} ccsr_gur_t;
1973
1ca8690d
YS		 1974#define TP_ITYP_AV 0x00000001 /* Initiator available */
1975#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1976#define TP_ITYP_TYPE_OTHER 0x0
1977#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1978#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1979#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1980#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1981#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1982
1983#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1984#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
f6981439 1985#define TP_INIT_PER_CLUSTER 4
1ca8690d 1986
f110fe94
SG		 1987#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1988#define FSL_CORENET_DCSR_SZ_4M 0x0
1989#define FSL_CORENET_DCSR_SZ_1G 0x3
1990
9ab87d04
KG		 1991/*
1992 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1993 * everything after has RMan thus msg unit LIODN is used for maintenance
1994 */
1995#define rmuliodnr rio1maintliodnr
1996
01df5212 1997typedef struct ccsr_clk {
f6981439
YS		 1998 struct {
1999 u32 clkcncsr; /* core cluster n clock control status */
2000 u8 res_004[0x0c];
2001 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
2002 u8 res_014[0x0c];
2003 } clkcsr[8];
2004 u8 res_100[0x700]; /* 0x100 */
9a653a98 2005 u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
8280912e 2006 u8 res10[0x1c];
9a653a98 2007 u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
8280912e 2008 u8 res11[0x1c];
9a653a98 2009 u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
8280912e 2010 u8 res12[0x1c];
9a653a98
YS		 2011 u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
2012 u8 res13[0x1c];
2013 u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
8280912e 2014 u8 res14[0x1c];
9a653a98
YS		 2015 u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
2016 u8 res15[0x35c];
2017 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
2018 u8 res16[0x1c];
2019 u32 plldgsr; /* 0xc20 DDR PLL General Status */
2020 u8 res17[0x3dc];
01df5212
KG		 2021} ccsr_clk_t;
2022
1ca8690d
YS		 2023#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2024typedef struct ccsr_rcpm {
2025 u8 res_00[12];
2026 u32 tph10sr0; /* Thread PH10 Status Register */
2027 u8 res_10[12];
2028 u32 tph10setr0; /* Thread PH10 Set Control Register */
2029 u8 res_20[12];
2030 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
2031 u8 res_30[12];
2032 u32 tph10psr0; /* Thread PH10 Previous Status Register */
2033 u8 res_40[12];
2034 u32 twaitsr0; /* Thread Wait Status Register */
2035 u8 res_50[96];
2036 u32 pcph15sr; /* Physical Core PH15 Status Register */
2037 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
2038 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
2039 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
2040 u8 res_c0[16];
2041 u32 pcph20sr; /* Physical Core PH20 Status Register */
2042 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
2043 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
2044 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
2045 u32 pcpw20sr; /* Physical Core PW20 Status Register */
2046 u8 res_e0[12];
2047 u32 pcph30sr; /* Physical Core PH30 Status Register */
2048 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
2049 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
2050 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
2051 u8 res_100[32];
2052 u32 ippwrgatecr; /* IP Power Gating Control Register */
2053 u8 res_124[12];
2054 u32 powmgtcsr; /* Power Management Control & Status Reg */
2055 u8 res_134[12];
2056 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
2057 u8 res_150[12];
2058 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
2059 u8 res_160[12];
2060 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
2061 u8 res_170[12];
2062 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
2063 u8 res_180[12];
2064 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
2065 u8 res_190[12];
2066 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
2067 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2068 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2069 u32 tbclkdivr; /* Time Base Clock Divider Register */
2070 u8 res_1ac[4];
2071 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2072 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2073 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2074 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2075 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2076 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2077 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2078 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2079 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2080 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2081 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2082 u8 res_1e8[8];
2083 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2084 u8 res_300[3568];
2085} ccsr_rcpm_t;
2086
2087#define ctbenrl pctbenr
2088
2089#else
01df5212 2090typedef struct ccsr_rcpm {
8280912e
KG		 2091 u8 res1[4];
2092 u32 cdozsrl; /* Core Doze Status */
2093 u8 res2[4];
2094 u32 cdozcrl; /* Core Doze Control */
2095 u8 res3[4];
2096 u32 cnapsrl; /* Core Nap Status */
2097 u8 res4[4];
2098 u32 cnapcrl; /* Core Nap Control */
2099 u8 res5[4];
2100 u32 cdozpsrl; /* Core Doze Previous Status */
2101 u8 res6[4];
2102 u32 cdozpcrl; /* Core Doze Previous Control */
2103 u8 res7[4];
2104 u32 cwaitsrl; /* Core Wait Status */
2105 u8 res8[8];
2106 u32 powmgtcsr; /* Power Mangement Control & Status */
2107 u8 res9[12];
2108 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2109 u8 res10[12];
2110 u8 res11[4];
2111 u32 cpmimrl; /* Core PM IRQ Masking */
2112 u8 res12[4];
2113 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2114 u8 res13[4];
2115 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2116 u8 res14[4];
2117 u32 cpmnmimrl; /* Core PM NMI Masking */
2118 u8 res15[4];
2119 u32 ctbenrl; /* Core Time Base Enable */
2120 u8 res16[4];
2121 u32 ctbclkselrl; /* Core Time Base Clock Select */
2122 u8 res17[4];
2123 u32 ctbhltcrl; /* Core Time Base Halt Control */
01df5212
KG		 2124 u8 res18[0xf68];
2125} ccsr_rcpm_t;
1ca8690d 2126#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
01df5212
KG		 2127
2128#else
42d1f039 2129typedef struct ccsr_gur {
8280912e 2130 u32 porpllsr; /* POR PLL ratio status */
c0391111
JJ		 2131#ifdef CONFIG_MPC8536
2132#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2133#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2134#else
35fe948e 2135#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
19a8dbdc
PK		 2136#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2137#else
c0391111 2138#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
19a8dbdc 2139#endif
c0391111
JJ		 2140#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2141#endif
b3d7f20f
HW		 2142#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2143#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
266139b8 2144#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
8280912e
KG		 2145#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2146 u32 porbmsr; /* POR boot mode status */
53677ef1 2147#define MPC85xx_PORBMSR_HA 0x00070000
6442b71b 2148#define MPC85xx_PORBMSR_HA_SHIFT 16
8bd00c94 2149#define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
35fe948e
PK		 2150#define PORBMSR_ROMLOC_SPI 0x6
2151#define PORBMSR_ROMLOC_SDHC 0x7
2152#define PORBMSR_ROMLOC_NAND_2K 0x9
2153#define PORBMSR_ROMLOC_NOR 0xf
8280912e
KG		 2154 u32 porimpscr; /* POR I/O impedance status & control */
2155 u32 pordevsr; /* POR I/O device status regsiter */
67a719da
RZ		 2156#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2157#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2158#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
c916d7c9 2159#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
67a719da 2160#else
837f1ba0
ES		 2161#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2162#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
67a719da 2163#endif
837f1ba0
ES		 2164#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2165#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
8280912e 2166#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
9427ccde 2167#define MPC85xx_PORDEVSR_PCI1 0x00800000
0c955daf
DL		 2168#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2169#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2170#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
67a719da
RZ		 2171#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2172#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2173#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
0c955daf 2174#else
28747f9b
PK		 2175#if defined(CONFIG_P1010)
2176#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2177#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
35fe948e
PK		 2178#elif defined(CONFIG_BSC9132)
2179#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2180#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
28747f9b 2181#else
4442f45b 2182#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
6442b71b 2183#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
28747f9b 2184#endif /* if defined(CONFIG_P1010) */
0c955daf 2185#endif
53677ef1
WD		 2186#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2187#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2188#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2189#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2190#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
837f1ba0 2191#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
53677ef1 2192#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
837f1ba0 2193#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
8280912e
KG		 2194 u32 pordbgmsr; /* POR debug mode status */
2195 u32 pordevsr2; /* POR I/O device status 2 */
681c02d0 2196/* The 8544 RM says this is bit 26, but it's really bit 24 */
f7d190b1 2197#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
8280912e
KG		 2198 u8 res1[8];
2199 u32 gpporcr; /* General-purpose POR configuration */
2200 u8 res2[12];
ae2044d8
XX		 2201#if defined(CONFIG_MPC8536)
2202 u32 gencfgr; /* General Configuration Register */
2203#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2204#else
8280912e 2205 u32 gpiocr; /* GPIO control */
ae2044d8 2206#endif
8280912e 2207 u8 res3[12];
22b6dbc1 2208#if defined(CONFIG_MPC8569)
8280912e
KG		 2209 u32 plppar1; /* Platform port pin assignment 1 */
2210 u32 plppar2; /* Platform port pin assignment 2 */
2211 u32 plpdir1; /* Platform port pin direction 1 */
2212 u32 plpdir2; /* Platform port pin direction 2 */
22b6dbc1 2213#else
8280912e
KG		 2214 u32 gpoutdr; /* General-purpose output data */
2215 u8 res4[12];
22b6dbc1 2216#endif
8280912e
KG		 2217 u32 gpindr; /* General-purpose input data */
2218 u8 res5[12];
2219 u32 pmuxcr; /* Alt. function signal multiplex control */
4b77047c
DD		 2220#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2221#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2222#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2223#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2224#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2225#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2226#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2227#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2228#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2229#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2230#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2231#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2232#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2233#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2234#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2235#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2236#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2237#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2238#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2239#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2240#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2241#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2242#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2243#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2244#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2245#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2246#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2247#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2248#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2249#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2250#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2251#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2252#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2253#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2254#define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2255#define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2256#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2257#define MPC85xx_PMUXCR_SPI_RES 0x00000030
2258#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2259#define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2260#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2261#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2262#define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2263#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2264#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2265#endif
fe1a1da0
RZ		 2266#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2267#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2268#else
80522dc8
AF		 2269#define MPC85xx_PMUXCR_SD_DATA 0x80000000
2270#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2271#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2bad42a0 2272#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
4aa8405c 2273#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
a52d2f81
HW		 2274#define MPC85xx_PMUXCR_QE0 0x00008000
2275#define MPC85xx_PMUXCR_QE1 0x00004000
2276#define MPC85xx_PMUXCR_QE2 0x00002000
2277#define MPC85xx_PMUXCR_QE3 0x00001000
2278#define MPC85xx_PMUXCR_QE4 0x00000800
2279#define MPC85xx_PMUXCR_QE5 0x00000400
2280#define MPC85xx_PMUXCR_QE6 0x00000200
2281#define MPC85xx_PMUXCR_QE7 0x00000100
2282#define MPC85xx_PMUXCR_QE8 0x00000080
2283#define MPC85xx_PMUXCR_QE9 0x00000040
2284#define MPC85xx_PMUXCR_QE10 0x00000020
2285#define MPC85xx_PMUXCR_QE11 0x00000010
2286#define MPC85xx_PMUXCR_QE12 0x00000008
fe1a1da0 2287#endif
b93f81a4
JY		 2288#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2289#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2290#define MPC85xx_PMUXCR_TDM 0x00014800
2291#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2292#define MPC85xx_PMUXCR_SPI 0x00000000
19a8dbdc
PK		 2293#endif
2294#if defined(CONFIG_BSC9131)
2295#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2296#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2297#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2298#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2299#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2300#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2301#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2302#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2303#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2304#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2305#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2306#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2307#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2308#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2309#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2310#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2311#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2312#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2313#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2314#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2315#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2316#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2317#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2318#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2319#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2320#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2321#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2322#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2323#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2324#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2325#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2326#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2327#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2328#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2329#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2330#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2331#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2332#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2333#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2334#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2335#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2336#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
35fe948e
PK		 2337#endif
2338#ifdef CONFIG_BSC9132
2339#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2340#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
b93f81a4 2341#endif
6e37a044 2342 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
4b77047c
DD		 2343#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2344#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2345#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2346#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2347#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2348#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2349#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2350#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2351#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2352#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2353#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2354#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2355#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2356#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2357#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2358#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2359#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2360#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2361#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2362#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2363#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2364#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2365#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2366#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2367#endif
b93f81a4 2368#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
aeb6716a 2369#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
b93f81a4
JY		 2370#define MPC85xx_PMUXCR2_USB 0x00150000
2371#endif
35fe948e 2372#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
19a8dbdc
PK		 2373#if defined(CONFIG_BSC9131)
2374#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2375#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2376#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2377#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2378#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2379#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2380#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2381#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2382#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2383#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2384#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2385#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2386#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2387#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2388#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2389#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2390#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2391#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2392#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2393#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2394#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2395#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2396#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2397#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2398#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2399#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2400#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2401#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2402#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2403#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2404#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2405#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2406#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2407#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2408#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2409#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2410#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2411#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2412#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2413#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2414#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2415#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
35fe948e 2416#endif
19a8dbdc 2417 u32 pmuxcr3;
35fe948e 2418#if defined(CONFIG_BSC9131)
19a8dbdc
PK		 2419#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2420#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2421#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2422#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2423#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2424#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2425#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2426#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2427#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2428#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2429#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2430#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2431#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2432#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
35fe948e
PK		 2433#endif
2434#ifdef CONFIG_BSC9132
2435#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2436#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2437#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2438#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2439#endif
19a8dbdc
PK		 2440 u32 pmuxcr4;
2441#else
6e37a044 2442 u8 res6[8];
19a8dbdc 2443#endif
8280912e 2444 u32 devdisr; /* Device disable control */
837f1ba0
ES		 2445#define MPC85xx_DEVDISR_PCI1 0x80000000
2446#define MPC85xx_DEVDISR_PCI2 0x40000000
2447#define MPC85xx_DEVDISR_PCIE 0x20000000
2448#define MPC85xx_DEVDISR_LBC 0x08000000
2449#define MPC85xx_DEVDISR_PCIE2 0x04000000
2450#define MPC85xx_DEVDISR_PCIE3 0x02000000
2451#define MPC85xx_DEVDISR_SEC 0x01000000
2452#define MPC85xx_DEVDISR_SRIO 0x00080000
2453#define MPC85xx_DEVDISR_RMSG 0x00040000
53677ef1
WD		 2454#define MPC85xx_DEVDISR_DDR 0x00010000
2455#define MPC85xx_DEVDISR_CPU 0x00008000
2456#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2457#define MPC85xx_DEVDISR_TB 0x00004000
2458#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2459#define MPC85xx_DEVDISR_CPU1 0x00002000
2460#define MPC85xx_DEVDISR_TB1 0x00001000
837f1ba0
ES		 2461#define MPC85xx_DEVDISR_DMA 0x00000400
2462#define MPC85xx_DEVDISR_TSEC1 0x00000080
2463#define MPC85xx_DEVDISR_TSEC2 0x00000040
2464#define MPC85xx_DEVDISR_TSEC3 0x00000020
2465#define MPC85xx_DEVDISR_TSEC4 0x00000010
2466#define MPC85xx_DEVDISR_I2C 0x00000004
2467#define MPC85xx_DEVDISR_DUART 0x00000002
8280912e
KG		 2468 u8 res7[12];
2469 u32 powmgtcsr; /* Power management status & control */
2470 u8 res8[12];
2471 u32 mcpsumr; /* Machine check summary */
2472 u8 res9[12];
2473 u32 pvr; /* Processor version */
2474 u32 svr; /* System version */
a52d2f81 2475 u8 res10[8];
8280912e 2476 u32 rstcr; /* Reset control */
22b6dbc1 2477#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
a52d2f81 2478 u8 res11a[76];
8280912e 2479 par_io_t qe_par_io[7];
a52d2f81 2480 u8 res11b[1600];
be7bebea 2481#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
a52d2f81
HW		 2482 u8 res11a[12];
2483 u32 iovselsr;
2484 u8 res11b[60];
2485 par_io_t qe_par_io[3];
2486 u8 res11c[1496];
c59e4091 2487#else
a52d2f81 2488 u8 res11a[1868];
c59e4091 2489#endif
6e37a044 2490 u32 clkdvdr; /* Clock Divide register */
a52d2f81 2491 u8 res12[1532];
8280912e 2492 u32 clkocr; /* Clock out select */
a52d2f81 2493 u8 res13[12];
8280912e 2494 u32 ddrdllcr; /* DDR DLL control */
a52d2f81 2495 u8 res14[12];
8280912e 2496 u32 lbcdllcr; /* LBC DLL control */
19a8dbdc
PK		 2497#if defined(CONFIG_BSC9131)
2498 u8 res15[12];
2499 u32 halt_req_mask;
2500#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2501 u8 res18[232];
2502#else
a52d2f81 2503 u8 res15[248];
19a8dbdc 2504#endif
8280912e
KG		 2505 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2506 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2507 u32 ddrioovcr; /* DDR IO Override Control */
2508 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2509 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
4aa8405c
ZC		 2510 u8 res16[52];
2511 u32 sdhcdcr; /* SDHC debug control register */
2512 u8 res17[61592];
42d1f039 2513} ccsr_gur_t;
01df5212
KG		 2514#endif
2515
4aa8405c
ZC		 2516#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2517
fd3cebd0
YS		 2518#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2519#define MAX_SERDES 4
d1001e3f
YS		 2520#define SRDS_MAX_LANES 8
2521#define SRDS_MAX_BANK 2
fd3cebd0
YS		 2522typedef struct serdes_corenet {
2523 struct {
2524 u32 rstctl; /* Reset Control Register */
2525#define SRDS_RSTCTL_RST 0x80000000
2526#define SRDS_RSTCTL_RSTDONE 0x40000000
2527#define SRDS_RSTCTL_RSTERR 0x20000000
2528#define SRDS_RSTCTL_SWRST 0x10000000
2529#define SRDS_RSTCTL_SDPD 0x00000020
2530 u32 pllcr0; /* PLL Control Register 0 */
2531#define SRDS_PLLCR0_POFF 0x80000000
2532#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2533#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2534#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2535#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2536#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2537#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2538#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2539#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2540#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2541#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2542#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2543#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2544#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2545#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
2546 u32 pllcr1; /* PLL Control Register 1 */
2547#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2548 u32 res_0c; /* 0x00c */
2549 u32 pllcr3;
2550 u32 pllcr4;
2551 u8 res_18[0x20-0x18];
2552 } bank[2];
2553 u8 res_40[0x90-0x40];
2554 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2555 u8 res_94[0xa0-0x94];
2556 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2557 u8 res_a4[0xb0-0xa4];
2558 u32 srdsgr0; /* 0xb0 General Register 0 */
2559 u8 res_b4[0xe0-0xb4];
2560 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2561 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2562 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2563 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2564 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2565 u8 res_f4[0x100-0xf4];
2566 struct {
2567 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2568 u8 res_104[0x120-0x104];
2569 } srdslnpssr[8];
2570 u8 res_200[0x800-0x200];
2571 struct {
2572 u32 gcr0; /* 0x800 General Control Register 0 */
2573 u32 gcr1; /* 0x804 General Control Register 1 */
2574 u32 gcr2; /* 0x808 General Control Register 2 */
2575 u32 res_80c;
2576 u32 recr0; /* 0x810 Receive Equalization Control */
2577 u32 res_814;
2578 u32 tecr0; /* 0x818 Transmit Equalization Control */
2579 u32 res_81c;
2580 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2581 u8 res_824[0x840-0x824];
2582 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2583 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2584} serdes_corenet_t;
2585
2586#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2587
d1001e3f
YS		 2588#define SRDS_MAX_LANES 18
2589#define SRDS_MAX_BANK 3
11588b5d
KG		 2590typedef struct serdes_corenet {
2591 struct {
2592 u32 rstctl; /* Reset Control Register */
2593#define SRDS_RSTCTL_RST 0x80000000
2594#define SRDS_RSTCTL_RSTDONE 0x40000000
2595#define SRDS_RSTCTL_RSTERR 0x20000000
1231c498 2596#define SRDS_RSTCTL_SDPD 0x00000020
11588b5d 2597 u32 pllcr0; /* PLL Control Register 0 */
f8f85b04 2598#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
4905443f 2599#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
1231c498
KG		 2600#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2601#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2602#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
e02aea61 2603#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
f8f85b04 2604#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
1231c498
KG		 2605#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2606#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2607#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
11588b5d
KG		 2608 u32 pllcr1; /* PLL Control Register 1 */
2609#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2610 u32 res[5];
2611 } bank[3];
2612 u32 res1[12];
2613 u32 srdstcalcr; /* TX Calibration Control */
2614 u32 res2[3];
2615 u32 srdsrcalcr; /* RX Calibration Control */
2616 u32 res3[3];
2617 u32 srdsgr0; /* General Register 0 */
2618 u32 res4[11];
2619 u32 srdspccr0; /* Protocol Converter Config 0 */
2620 u32 srdspccr1; /* Protocol Converter Config 1 */
2621 u32 srdspccr2; /* Protocol Converter Config 2 */
2622#define SRDS_PCCR2_RST_XGMII1 0x00800000
2623#define SRDS_PCCR2_RST_XGMII2 0x00400000
2624 u32 res5[197];
d607b968 2625 struct serdes_lane {
11588b5d
KG		 2626 u32 gcr0; /* General Control Register 0 */
2627#define SRDS_GCR0_RRST 0x00400000
2628#define SRDS_GCR0_1STLANE 0x00010000
4905443f 2629#define SRDS_GCR0_UOTHL 0x00100000
11588b5d
KG		 2630 u32 gcr1; /* General Control Register 1 */
2631#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2632#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2633#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2634#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2635#define SRDS_GCR1_OPAD_CTL 0x04000000
2636 u32 res1[4];
2637 u32 tecr0; /* TX Equalization Control Reg 0 */
2638#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2639#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2640 u32 res3;
2641 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
df8af0b4 2642#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
b25f6de7
TT		 2643#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2644#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
f68d3063 2645#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
df8af0b4 2646#define SRDS_TTLCR0_PM_DIS 0x00004000
b25f6de7 2647#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
11588b5d
KG		 2648 u32 res4[7];
2649 } lane[24];
2650 u32 res6[384];
2651} serdes_corenet_t;
fd3cebd0 2652#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
11588b5d
KG		 2653
2654enum {
2655 FSL_SRDS_B1_LANE_A = 0,
2656 FSL_SRDS_B1_LANE_B = 1,
2657 FSL_SRDS_B1_LANE_C = 2,
2658 FSL_SRDS_B1_LANE_D = 3,
2659 FSL_SRDS_B1_LANE_E = 4,
2660 FSL_SRDS_B1_LANE_F = 5,
2661 FSL_SRDS_B1_LANE_G = 6,
2662 FSL_SRDS_B1_LANE_H = 7,
2663 FSL_SRDS_B1_LANE_I = 8,
2664 FSL_SRDS_B1_LANE_J = 9,
2665 FSL_SRDS_B2_LANE_A = 16,
2666 FSL_SRDS_B2_LANE_B = 17,
2667 FSL_SRDS_B2_LANE_C = 18,
2668 FSL_SRDS_B2_LANE_D = 19,
2669 FSL_SRDS_B3_LANE_A = 20,
2670 FSL_SRDS_B3_LANE_B = 21,
2671 FSL_SRDS_B3_LANE_C = 22,
2672 FSL_SRDS_B3_LANE_D = 23,
2673};
2674
22f292c7
KP		 2675/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2676#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2677typedef struct ccsr_sec {
9ab87d04
KG		 2678 u32 res0;
2679 u32 mcfgr; /* Master CFG Register */
2680 u8 res1[0x8];
2681 struct {
2682 u32 ms; /* Job Ring LIODN Register, MS */
2683 u32 ls; /* Job Ring LIODN Register, LS */
ed062e0f 2684 } jrliodnr[4];
9ab87d04
KG		 2685 u8 res2[0x30];
2686 struct {
2687 u32 ms; /* RTIC LIODN Register, MS */
2688 u32 ls; /* RTIC LIODN Register, LS */
2689 } rticliodnr[4];
2690 u8 res3[0x1c];
2691 u32 decorr; /* DECO Request Register */
2692 struct {
2693 u32 ms; /* DECO LIODN Register, MS */
2694 u32 ls; /* DECO LIODN Register, LS */
f311838d
AF		 2695 } decoliodnr[8];
2696 u8 res4[0x40];
9ab87d04
KG		 2697 u32 dar; /* DECO Avail Register */
2698 u32 drr; /* DECO Reset Register */
2699 u8 res5[0xe78];
22f292c7
KP		 2700 u32 crnr_ms; /* CHA Revision Number Register, MS */
2701 u32 crnr_ls; /* CHA Revision Number Register, LS */
2702 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
22f292c7 2703 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
9ab87d04 2704 u8 res6[0x10];
22f292c7
KP		 2705 u32 far_ms; /* Fault Address Register, MS */
2706 u32 far_ls; /* Fault Address Register, LS */
2707 u32 falr; /* Fault Address LIODN Register */
2708 u32 fadr; /* Fault Address Detail Register */
9ab87d04 2709 u8 res7[0x4];
22f292c7 2710 u32 csta; /* CAAM Status Register */
9ab87d04 2711 u8 res8[0x8];
22f292c7 2712 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
22f292c7
KP		 2713 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2714 u32 chavid_ms; /* CHA Version ID Register, MS */
2715 u32 chavid_ls; /* CHA Version ID Register, LS */
2716 u32 chanum_ms; /* CHA Number Register, MS */
9ab87d04
KG		 2717 u32 chanum_ls; /* CHA Number Register, LS */
2718 u32 secvid_ms; /* SEC Version ID Register, MS */
2719 u32 secvid_ls; /* SEC Version ID Register, LS */
2720 u8 res9[0x6020];
2721 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2722 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2723 u8 res10[0x8fd8];
2724} ccsr_sec_t;
2725
2726#define SEC_CTPR_MS_AXI_LIODN 0x08000000
2727#define SEC_CTPR_MS_QI 0x02000000
2728#define SEC_RVID_MA 0x0f000000
ed062e0f
KG		 2729#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2730#define SEC_CHANUM_MS_JRNUM_SHIFT 28
22f292c7
KP		 2731#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2732#define SEC_CHANUM_MS_DECONUM_SHIFT 24
5e95e2d8
VG		 2733#define SEC_SECVID_MS_IPID_MASK 0xffff0000
2734#define SEC_SECVID_MS_IPID_SHIFT 16
2735#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2736#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2737#define SEC_CCBVID_ERA_MASK 0xff000000
2738#define SEC_CCBVID_ERA_SHIFT 24
22f292c7
KP		 2739#endif
2740
9ab87d04 2741typedef struct ccsr_qman {
92230d49
YS		 2742#ifdef CONFIG_SYS_FSL_QMAN_V3
2743 u8 res0[0x200];
2744#else
9ab87d04
KG		 2745 struct {
2746 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2747 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2748 u32 res;
2749 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2750 } qcsp[32];
92230d49 2751#endif
9ab87d04
KG		 2752 /* Not actually reserved, but irrelevant to u-boot */
2753 u8 res[0xbf8 - 0x200];
2754 u32 ip_rev_1;
2755 u32 ip_rev_2;
2756 u32 fqd_bare; /* FQD Extended Base Addr Register */
2757 u32 fqd_bar; /* FQD Base Addr Register */
2758 u8 res1[0x8];
2759 u32 fqd_ar; /* FQD Attributes Register */
2760 u8 res2[0xc];
2761 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2762 u32 pfdr_bar; /* PFDR Base Addr Register */
2763 u8 res3[0x8];
2764 u32 pfdr_ar; /* PFDR Attributes Register */
2765 u8 res4[0x4c];
2766 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2767 u32 qcsp_bar; /* QCSP Base Addr Register */
2768 u8 res5[0x78];
2769 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2770 u32 srcidr; /* Source ID Register */
2771 u32 liodnr; /* LIODN Register */
2772 u8 res6[4];
2773 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2774 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2775 u8 res7[0x2e8];
92230d49
YS		 2776#ifdef CONFIG_SYS_FSL_QMAN_V3
2777 struct {
2778 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2779 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2780 u32 res;
2781 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2782 } qcsp[50];
2783#endif
9ab87d04
KG		 2784} ccsr_qman_t;
2785
2786typedef struct ccsr_bman {
2787 /* Not actually reserved, but irrelevant to u-boot */
2788 u8 res[0xbf8];
2789 u32 ip_rev_1;
2790 u32 ip_rev_2;
2791 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2792 u32 fbpr_bar; /* FBPR Base Addr Register */
2793 u8 res1[0x8];
2794 u32 fbpr_ar; /* FBPR Attributes Register */
2795 u8 res2[0xf0];
2796 u32 srcidr; /* Source ID Register */
2797 u32 liodnr; /* LIODN Register */
2798 u8 res7[0x2f4];
2799} ccsr_bman_t;
2800
2801typedef struct ccsr_pme {
2802 u8 res0[0x804];
2803 u32 liodnbr; /* LIODN Base Register */
2804 u8 res1[0x1f8];
2805 u32 srcidr; /* Source ID Register */
2806 u8 res2[8];
2807 u32 liodnr; /* LIODN Register */
2808 u8 res3[0x1e8];
2809 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2810 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2811 u8 res4[0x400];
2812} ccsr_pme_t;
2813
1e501f91
RZ		 2814#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
2815struct ccsr_usb_port_ctrl {
2816 u32 ctrl;
2817 u32 drvvbuscfg;
2818 u32 pwrfltcfg;
2819 u32 sts;
2820 u8 res_14[0xc];
2821 u32 bistcfg;
2822 u32 biststs;
2823 u32 abistcfg;
2824 u32 abiststs;
2825 u8 res_30[0x10];
2826 u32 xcvrprg;
2827 u32 anaprg;
2828 u32 anadrv;
2829 u32 anasts;
2830};
2831
2832typedef struct ccsr_usb_phy {
2833 u32 id;
2834 struct ccsr_usb_port_ctrl port1;
2835 u8 res_50[0xc];
2836 u32 tvr;
2837 u32 pllprg[4];
2838 u8 res_70[0x4];
2839 u32 anaccfg;
2840 u32 dbg;
2841 u8 res_7c[0x4];
2842 struct ccsr_usb_port_ctrl port2;
2843 u8 res_dc[0x334];
2844} ccsr_usb_phy_t;
2845
2846#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
2847#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
2848#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
2849#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
2850#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
2851#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
2852#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
2853#else
86221f09
RZ		 2854typedef struct ccsr_usb_phy {
2855 u8 res0[0x18];
2856 u32 usb_enable_override;
2857 u8 res[0xe4];
2858} ccsr_usb_phy_t;
2859#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
1e501f91 2860#endif
86221f09 2861
6b3a8d00
KG		 2862#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2863struct ccsr_raide {
2864 u8 res0[0x543];
2865 u32 liodnbr; /* LIODN Base Register */
2866 u8 res1[0xab8];
2867 struct {
2868 struct {
2869 u32 cfg0; /* cfg register 0 */
2870 u32 cfg1; /* cfg register 1 */
2871 u8 res1[0x3f8];
2872 } ring[2];
2873 u8 res[0x800];
2874 } jq[2];
2875};
2876#endif
2877
4d28db8a
KG		 2878#ifdef CONFIG_SYS_DPAA_RMAN
2879struct ccsr_rman {
2880 u8 res0[0xf64];
2881 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2882 u32 mmitar; /* RMAN Inbound Translation Address Register */
2883 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2884 u8 res4[0x1f090];
2885};
2886#endif
2887
f311838d
AF		 2888#ifdef CONFIG_SYS_PMAN
2889struct ccsr_pman {
2890 u8 res_00[0x40];
2891 u32 poes1; /* PMAN Operation Error Status Register 1 */
2892 u32 poes2; /* PMAN Operation Error Status Register 2 */
2893 u32 poeah; /* PMAN Operation Error Address High */
2894 u32 poeal; /* PMAN Operation Error Address Low */
2895 u8 res_50[0x50];
2896 u32 pr1; /* PMAN Revision Register 1 */
2897 u32 pr2; /* PMAN Revision Register 2 */
2898 u8 res_a8[0x8];
2899 u32 pcap; /* PMAN Capabilities Register */
2900 u8 res_b4[0xc];
2901 u32 pc1; /* PMAN Control Register 1 */
2902 u32 pc2; /* PMAN Control Register 2 */
2903 u32 pc3; /* PMAN Control Register 3 */
2904 u32 pc4; /* PMAN Control Register 4 */
2905 u32 pc5; /* PMAN Control Register 5 */
2906 u32 pc6; /* PMAN Control Register 6 */
2907 u8 res_d8[0x8];
2908 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2909 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2910 u8 res_e8[0x8];
2911 u32 pics; /* PMAN Interrupt Control and Status */
2912 u8 res_f4[0xf0c];
2913};
2914#endif
2915
01df5212
KG		 2916#ifdef CONFIG_FSL_CORENET
2917#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
f311838d
AF		 2918#ifdef CONFIG_SYS_PMAN
2919#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2920#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2921#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2922#endif
e76cd5d4
AF		 2923#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2924#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2925#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
01df5212
KG		 2926#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2927#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
11588b5d 2928#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
4905443f 2929#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
8b0ab304 2930#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
9ab87d04
KG		 2931#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2932#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2933#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
01df5212
KG		 2934#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2935#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2936#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
50d96e95 2937#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
01df5212 2938#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
4d28db8a 2939#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
ada961e2
LG		 2940#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2941 && !defined(CONFIG_PPC_B4420)
9e758758
YS		 2942#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2943#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2944#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2945#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2946#else
9ab87d04
KG		 2947#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2948#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2949#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2950#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
9e758758 2951#endif
9ab87d04
KG		 2952#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2953#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2954#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
86221f09
RZ		 2955#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2956#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
9ab87d04
KG		 2957#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2958#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
22f292c7 2959#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
9ab87d04 2960#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
24995d82
HW		 2961#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2962#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
6b3a8d00 2963#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
9ab87d04
KG		 2964#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2965#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2966#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2967#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2968#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2969#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
f311838d 2970#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
9ab87d04 2971#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
f311838d 2972#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
9ab87d04
KG		 2973#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2974#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2975#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2976#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2977#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2978#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2979#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
f311838d 2980#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
9ab87d04 2981#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
f311838d 2982#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
6d2b9da1 2983#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
01df5212
KG		 2984#else
2985#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
e76cd5d4 2986#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
01df5212 2987#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
e76cd5d4 2988#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
01df5212 2989#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
99d9c07e 2990#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
01df5212 2991#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
99d9c07e 2992#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
01df5212 2993#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
99d9c07e
KG		 2994#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2995#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2996#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2997#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2998#else
2999#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
3000#endif
01df5212
KG		 3001#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
3002#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
3003#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
d789b5f5 3004#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
01df5212
KG		 3005#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
3006#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
8280912e 3007#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
9839709e 3008#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
3ad89c4e
KG		 3009#ifdef CONFIG_TSECV2
3010#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
3011#else
b9e186fc 3012#define CONFIG_SYS_TSEC1_OFFSET 0x24000
3ad89c4e
KG		 3013#endif
3014#define CONFIG_SYS_MDIO1_OFFSET 0x24000
01df5212 3015#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
5e95e2d8 3016#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
01df5212
KG		 3017#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
3018#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
7065b7d4
RG		 3019#define CONFIG_SYS_SNVS_OFFSET 0xE6000
3020#define CONFIG_SYS_SFP_OFFSET 0xE7000
01df5212 3021#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
67a719da
RZ		 3022#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
3023#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
3024#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
3025#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
3026#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
3027#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
01df5212
KG		 3028#endif
3029
3030#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
3031#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
5ffa88ec 3032#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
42d1f039 3033
8b0ab304
BB		 3034#define CONFIG_SYS_FSL_CPC_ADDR \
3035 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
24995d82
HW		 3036#define CONFIG_SYS_FSL_QMAN_ADDR \
3037 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
3038#define CONFIG_SYS_FSL_BMAN_ADDR \
3039 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
9ab87d04
KG		 3040#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
3041 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
6b3a8d00
KG		 3042#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
3043 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
4d28db8a
KG		 3044#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
3045 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
8280912e
KG		 3046#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
3047 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
3048#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
3049 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
3050#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
3051 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
3052#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
3053 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
3054#define CONFIG_SYS_MPC85xx_ECM_ADDR \
3055 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
e76cd5d4
AF		 3056#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
3057 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
3058#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
3059 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
3060#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
3061 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
f51cdaf1 3062#define CONFIG_SYS_LBC_ADDR \
8280912e 3063 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
d789b5f5
DD		 3064#define CONFIG_SYS_IFC_ADDR \
3065 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
8280912e
KG		 3066#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
3067 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
3068#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
3069 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
3070#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3071 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3072#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3073 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3074#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3075 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3076#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3077 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3078#define CONFIG_SYS_MPC85xx_L2_ADDR \
3079 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3080#define CONFIG_SYS_MPC85xx_DMA_ADDR \
3081 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3082#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3083 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
680c613a 3084#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
8280912e
KG		 3085 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3086#define CONFIG_SYS_MPC85xx_CPM_ADDR \
3087 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3088#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
17028be2 3089 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
8280912e
KG		 3090#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3091 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
11588b5d
KG		 3092#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3093 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
4905443f
TT		 3094#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3095 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
a07bf180 3096#define CONFIG_SYS_MPC85xx_USB_ADDR \
8280912e 3097 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
86221f09
RZ		 3098#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3099 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3100#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3101 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
22f292c7
KP		 3102#define CONFIG_SYS_FSL_SEC_ADDR \
3103 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
9ab87d04
KG		 3104#define CONFIG_SYS_FSL_FM1_ADDR \
3105 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3106#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3107 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3108#define CONFIG_SYS_FSL_FM2_ADDR \
3109 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
5ffa88ec
LG		 3110#define CONFIG_SYS_FSL_SRIO_ADDR \
3111 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
aafeefbd 3112
99d9c07e
KG		 3113#define CONFIG_SYS_PCI1_ADDR \
3114 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3115#define CONFIG_SYS_PCI2_ADDR \
3116 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3117#define CONFIG_SYS_PCIE1_ADDR \
3118 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3119#define CONFIG_SYS_PCIE2_ADDR \
3120 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3121#define CONFIG_SYS_PCIE3_ADDR \
3122 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
9ab87d04
KG		 3123#define CONFIG_SYS_PCIE4_ADDR \
3124 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
99d9c07e 3125
b9e186fc
SG		 3126#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3127#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3128
6d2b9da1
YS		 3129#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3130struct ccsr_cluster_l2 {
3131 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3132 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3133 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3134 u8 res_0c[500];/* 0x00c - 0x1ff */
3135 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3136 u8 res_204[4];
3137 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3138 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3139 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3140 u8 res_214[4];
3141 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3142 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3143 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3144 u8 res_224[4];
3145 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3146 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3147 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3148 u8 res_234[4];
3149 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3150 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3151 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3152 u8 res244[4];
3153 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3154 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3155 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3156 u8 res_254[4];
3157 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3158 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3159 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3160 u8 res_264[4];
3161 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3162 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3163 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3164 u8 res274[4];
3165 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3166 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3167 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3168 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3169 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3170 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3171 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3172 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3173 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3174 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3175 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3176 u32 l2errdet; /* 0xe40 L2 cache error detect */
3177 u32 l2errdis; /* 0xe44 L2 cache error disable */
3178 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3179 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3180 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3181 u32 l2erraddr; /* 0xe54 L2 cache error address */
3182 u32 l2errctl; /* 0xe58 L2 cache error control */
3183};
3184#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3185 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3186#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
99d7b0a4
X		 3187
3188#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3189struct dcsr_dcfg_regs {
3190 u8 res_0[0x520];
3191 u32 ecccr1;
3192#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3193#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3194 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3195};
42d1f039 3196#endif /*__IMMAP_85xx__*/
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