]>
Commit | Line | Data |
---|---|---|
5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2000 - 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f08abe31 WD |
6 | ******************************************************************** |
7 | * NOTE: This header file defines an interface to U-Boot. Including | |
8 | * this (unmodified) header file in another file is considered normal | |
9 | * use of U-Boot, and does *not* fall under the heading of "derived | |
10 | * work". | |
11 | ******************************************************************** | |
5b1d7137 WD |
12 | */ |
13 | ||
14 | #ifndef __U_BOOT_H__ | |
15 | #define __U_BOOT_H__ | |
16 | ||
17 | /* | |
18 | * Board information passed to Linux kernel from U-Boot | |
19 | * | |
20 | * include/asm-ppc/u-boot.h | |
21 | */ | |
22 | ||
660c60c4 SG |
23 | #ifdef CONFIG_SYS_GENERIC_BOARD |
24 | /* Use the generic board which requires a unified bd_info */ | |
25 | #include <asm-generic/u-boot.h> | |
26 | #else | |
27 | ||
5b1d7137 | 28 | #ifndef __ASSEMBLY__ |
5b1d7137 WD |
29 | |
30 | typedef struct bd_info { | |
31 | unsigned long bi_memstart; /* start of DRAM memory */ | |
b57ca3e1 | 32 | phys_size_t bi_memsize; /* size of DRAM memory in bytes */ |
5b1d7137 WD |
33 | unsigned long bi_flashstart; /* start of FLASH memory */ |
34 | unsigned long bi_flashsize; /* size of FLASH memory */ | |
35 | unsigned long bi_flashoffset; /* reserved area for startup monitor */ | |
36 | unsigned long bi_sramstart; /* start of SRAM memory */ | |
37 | unsigned long bi_sramsize; /* size of SRAM memory */ | |
42d1f039 | 38 | #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ |
debb7354 | 39 | || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
5b1d7137 | 40 | unsigned long bi_immr_base; /* base of IMMR register */ |
945af8d7 | 41 | #endif |
cbd8a35c | 42 | #if defined(CONFIG_MPC5xxx) |
945af8d7 | 43 | unsigned long bi_mbar_base; /* base of internal registers */ |
983fda83 | 44 | #endif |
0f898604 | 45 | #if defined(CONFIG_MPC83xx) |
f046ccd1 | 46 | unsigned long bi_immrbar; |
5b1d7137 | 47 | #endif |
d98b0523 | 48 | unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ |
e5ab702a | 49 | unsigned long bi_ip_addr; /* IP Address */ |
eb85aa59 | 50 | unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ |
5b1d7137 WD |
51 | unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ |
52 | unsigned long bi_intfreq; /* Internal Freq, in MHz */ | |
53 | unsigned long bi_busfreq; /* Bus Freq, in MHz */ | |
9c4c5ae3 | 54 | #if defined(CONFIG_CPM2) |
5b1d7137 WD |
55 | unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ |
56 | unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ | |
57 | unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ | |
58 | unsigned long bi_vco; /* VCO Out from PLL, in MHz */ | |
945af8d7 | 59 | #endif |
281ff9a4 GB |
60 | #if defined(CONFIG_MPC512X) |
61 | unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ | |
62 | #endif /* CONFIG_MPC512X */ | |
cbd8a35c | 63 | #if defined(CONFIG_MPC5xxx) |
945af8d7 WD |
64 | unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ |
65 | unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ | |
5b1d7137 | 66 | #endif |
a7e5ee9e | 67 | unsigned int bi_baudrate; /* Console Baudrate */ |
12f34241 WD |
68 | #if defined(CONFIG_405) || \ |
69 | defined(CONFIG_405GP) || \ | |
5b1d7137 | 70 | defined(CONFIG_405CR) || \ |
12f34241 | 71 | defined(CONFIG_405EP) || \ |
e01bd218 | 72 | defined(CONFIG_405EZ) || \ |
dbbd1257 | 73 | defined(CONFIG_405EX) || \ |
12f34241 | 74 | defined(CONFIG_440) |
5b1d7137 | 75 | unsigned char bi_s_version[4]; /* Version of this structure */ |
0c8721a4 | 76 | unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ |
5b1d7137 WD |
77 | unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ |
78 | unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ | |
79 | unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ | |
80 | unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ | |
81 | #endif | |
82 | #if defined(CONFIG_HYMOD) | |
83 | hymod_conf_t bi_hymod_conf; /* hymod configuration information */ | |
84 | #endif | |
03f5c550 | 85 | |
e2ffd59b | 86 | #ifdef CONFIG_HAS_ETH1 |
eb85aa59 | 87 | unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ |
5b1d7137 | 88 | #endif |
e2ffd59b | 89 | #ifdef CONFIG_HAS_ETH2 |
eb85aa59 | 90 | unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ |
5b1d7137 | 91 | #endif |
e2ffd59b | 92 | #ifdef CONFIG_HAS_ETH3 |
eb85aa59 | 93 | unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ |
ba56f625 | 94 | #endif |
c68a05fe | 95 | #ifdef CONFIG_HAS_ETH4 |
eb85aa59 | 96 | unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ |
c68a05fe | 97 | #endif |
98 | #ifdef CONFIG_HAS_ETH5 | |
eb85aa59 | 99 | unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ |
c68a05fe | 100 | #endif |
03f5c550 | 101 | |
e01bd218 SR |
102 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
103 | defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ | |
887e2ec9 | 104 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
999ecd5a SR |
105 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
106 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
5bb226e8 WD |
107 | unsigned int bi_opbfreq; /* OPB clock in Hz */ |
108 | int bi_iic_fast[2]; /* Use fast i2c mode */ | |
109 | #endif | |
5b1d7137 WD |
110 | #if defined(CONFIG_NX823) |
111 | unsigned char bi_sernum[8]; | |
112 | #endif | |
d6c61aab | 113 | #if defined(CONFIG_4xx) |
999ecd5a SR |
114 | #if defined(CONFIG_440GX) || \ |
115 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
53677ef1 WD |
116 | int bi_phynum[4]; /* Determines phy mapping */ |
117 | int bi_phymode[4]; /* Determines phy mode */ | |
25fb02ab | 118 | #elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440) |
53677ef1 WD |
119 | int bi_phynum[2]; /* Determines phy mapping */ |
120 | int bi_phymode[2]; /* Determines phy mode */ | |
d6c61aab | 121 | #else |
53677ef1 WD |
122 | int bi_phynum[1]; /* Determines phy mapping */ |
123 | int bi_phymode[1]; /* Determines phy mode */ | |
3c74e32a | 124 | #endif |
d6c61aab | 125 | #endif /* defined(CONFIG_4xx) */ |
5b1d7137 WD |
126 | } bd_t; |
127 | ||
128 | #endif /* __ASSEMBLY__ */ | |
476af299 | 129 | |
660c60c4 SG |
130 | #endif /* !CONFIG_SYS_GENERIC_BOARD */ |
131 | ||
476af299 MF |
132 | /* For image.h:image_check_target_arch() */ |
133 | #define IH_ARCH_DEFAULT IH_ARCH_PPC | |
134 | ||
5b1d7137 | 135 | #endif /* __U_BOOT_H__ */ |