[people/ms/u-boot.git] / arch / x86 / cpu / ivybridge / sata.c

/*
 * From Coreboot
 * Copyright (C) 2008-2009 coresystems GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>

DECLARE_GLOBAL_DATA_PTR;

static void common_sata_init(struct udevice *dev, unsigned int port_map)
{
	u32 reg32;
	u16 reg16;

	/* Set IDE I/O Configuration */
	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
	dm_pci_write_config32(dev, IDE_CONFIG, reg32);

	/* Port enable */
	dm_pci_read_config16(dev, 0x92, &reg16);
	reg16 &= ~0x3f;
	reg16 |= port_map;
	dm_pci_write_config16(dev, 0x92, reg16);

	/* SATA Initialization register */
	port_map &= 0xff;
	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
}

static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
{
	unsigned int port_map, speed_support, port_tx;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	const char *mode;
	u32 reg32;
	u16 reg16;

	debug("SATA: Initializing...\n");

	/* SATA configuration */
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	speed_support = fdtdec_get_int(blob, node,
				       "sata_interface_speed_support", 0);

	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (!mode || !strcmp(mode, "ahci")) {
		ulong abar;

		debug("SATA: Controller in AHCI mode\n");

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);

		common_sata_init(dev, 0x8000 | port_map);

		/* Initialize AHCI memory-mapped space */
		abar = dm_pci_read_bar32(dev, 5);
		debug("ABAR: %08lx\n", abar);
		/* CAP (HBA Capabilities) : enable power management */
		reg32 = readl(abar + 0x00);
		reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
		reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
		/* Set ISS, if available */
		if (speed_support) {
			reg32 &= ~0x00f00000;
			reg32 |= (speed_support & 0x03) << 20;
		}
		writel(reg32, abar + 0x00);
		/* PI (Ports implemented) */
		writel(port_map, abar + 0x0c);
		(void) readl(abar + 0x0c); /* Read back 1 */
		(void) readl(abar + 0x0c); /* Read back 2 */
		/* CAP2 (HBA Capabilities Extended)*/
		reg32 = readl(abar + 0x24);
		reg32 &= ~0x00000002;
		writel(reg32, abar + 0x24);
		/* VSP (Vendor Specific Register */
		reg32 = readl(abar + 0xa0);
		reg32 &= ~0x00000005;
		writel(reg32, abar + 0xa0);
	} else if (!strcmp(mode, "combined")) {
		debug("SATA: Controller in combined mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);
		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		dm_pci_write_config8(dev, 0x09, 0x80);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);

		common_sata_init(dev, port_map);
	} else {
		debug("SATA: Controller in plain-ide mode\n");

		/* No AHCI: clear AHCI base */
		dm_pci_write_bar32(dev, 5, 0x00000000);

		/* And without AHCI BAR no memory decoding */
		dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
		reg16 &= ~PCI_COMMAND_MEMORY;
		dm_pci_write_config16(dev, PCI_COMMAND, reg16);

		/*
		 * Native mode capable on both primary and secondary (0xa)
		 * OR'ed with enabled (0x50) = 0xf
		 */
		dm_pci_write_config8(dev, 0x09, 0x8f);

		/* Set timings */
		dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
		dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
				IDE_SITRE | IDE_ISP_3_CLOCKS |
				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);

		/* Sync DMA */
		dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
		dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);

		common_sata_init(dev, port_map);
	}

	/* Set Gen3 Transmitter settings if needed */
	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);

	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	if (port_tx)
		pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);

	/* Additional Programming Requirements */
	pch_common_sir_write(dev, 0x04, 0x00001600);
	pch_common_sir_write(dev, 0x28, 0xa0000033);
	reg32 = pch_common_sir_read(dev, 0x54);
	reg32 &= 0xff000000;
	reg32 |= 0x5555aa;
	pch_common_sir_write(dev, 0x54, reg32);
	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	reg32 = pch_common_sir_read(dev, 0x68);
	reg32 &= 0xffff0000;
	reg32 |= 0xcccc;
	pch_common_sir_write(dev, 0x68, reg32);
	reg32 = pch_common_sir_read(dev, 0x78);
	reg32 &= 0x0000ffff;
	reg32 |= 0x88880000;
	pch_common_sir_write(dev, 0x78, reg32);
	pch_common_sir_write(dev, 0x84, 0x001c7000);
	pch_common_sir_write(dev, 0x88, 0x88338822);
	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	pch_common_sir_write(dev, 0xd4, 0x10000000);

	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
}

static void bd82x6x_sata_enable(struct udevice *dev)
{
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(dev);
	unsigned port_map;
	const char *mode;
	u16 map = 0;

	/*
	 * Set SATA controller mode early so the resource allocator can
	 * properly assign IO/Memory resources for the controller.
	 */
	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	if (mode && !strcmp(mode, "ahci"))
		map = 0x0060;
	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);

	map |= (port_map ^ 0x3f) << 8;
	dm_pci_write_config16(dev, 0x90, map);
}

static int bd82x6x_sata_probe(struct udevice *dev)
{
	struct udevice *pch;
	int ret;

	ret = uclass_first_device_err(UCLASS_PCH, &pch);
	if (ret)
		return ret;

	if (!(gd->flags & GD_FLG_RELOC))
		bd82x6x_sata_enable(dev);
	else
		bd82x6x_sata_init(dev, pch);

	return 0;
}

static const struct udevice_id bd82x6x_ahci_ids[] = {
	{ .compatible = "intel,pantherpoint-ahci" },
	{ }
};

U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	.name		= "ahci_ivybridge",
	.id		= UCLASS_AHCI,
	.of_match	= bd82x6x_ahci_ids,
	.probe		= bd82x6x_sata_probe,
};
Commit	Line	Data
3ac83935 SG	1	/*
	2	* From Coreboot
	3	* Copyright (C) 2008-2009 coresystems GmbH
	4	*
	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#include <common.h>
d46f2a68	9	#include <dm.h>
3ac83935 SG	10	#include <fdtdec.h>
3ac83935 SG	11	#include <asm/io.h>
7e4a6ae6	12	#include <asm/pch_common.h>
3ac83935 SG	13	#include <asm/pci.h>
3ac83935 SG	14	#include <asm/arch/pch.h>
3ac83935	15
d46f2a68 SG	16	DECLARE_GLOBAL_DATA_PTR;
d46f2a68 SG	17
ddf10c20	18	static void common_sata_init(struct udevice *dev, unsigned int port_map)
3ac83935 SG	19	{
	20	u32 reg32;
	21	u16 reg16;
	22
	23	/* Set IDE I/O Configuration */
	24	reg32 = SIG_MODE_PRI_NORMAL \| FAST_PCB1 \| FAST_PCB0 \| PCB1 \| PCB0;
ddf10c20	25	dm_pci_write_config32(dev, IDE_CONFIG, reg32);
3ac83935 SG	26
3ac83935 SG	27	/* Port enable */
ddf10c20	28	dm_pci_read_config16(dev, 0x92, &reg16);
3ac83935 SG	29	reg16 &= ~0x3f;
3ac83935 SG	30	reg16 \|= port_map;
ddf10c20	31	dm_pci_write_config16(dev, 0x92, reg16);
3ac83935 SG	32
	33	/* SATA Initialization register */
	34	port_map &= 0xff;
ddf10c20	35	dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) \| 0x183);
3ac83935 SG	36	}
3ac83935 SG	37
9434c7a3	38	static void bd82x6x_sata_init(struct udevice dev, struct udevice pch)
3ac83935 SG	39	{
3ac83935 SG	40	unsigned int port_map, speed_support, port_tx;
ddf10c20	41	const void *blob = gd->fdt_blob;
e160f7d4	42	int node = dev_of_offset(dev);
3ac83935 SG	43	const char *mode;
	44	u32 reg32;
	45	u16 reg16;
	46
	47	debug("SATA: Initializing...\n");
	48
	49	/* SATA configuration */
	50	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	51	speed_support = fdtdec_get_int(blob, node,
	52	"sata_interface_speed_support", 0);
	53
3ac83935 SG	54	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
3ac83935 SG	55	if (!mode \|\| !strcmp(mode, "ahci")) {
c7ccb2c0	56	ulong abar;
3ac83935 SG	57
	58	debug("SATA: Controller in AHCI mode\n");
	59
3ac83935	60	/* Set timings */
ddf10c20	61	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	62	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	63	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	64	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	65	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
	66
	67	/* Sync DMA */
ddf10c20 SG	68	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
ddf10c20 SG	69	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
3ac83935 SG	70
	71	common_sata_init(dev, 0x8000 \| port_map);
	72
	73	/* Initialize AHCI memory-mapped space */
ddf10c20	74	abar = dm_pci_read_bar32(dev, 5);
c7ccb2c0	75	debug("ABAR: %08lx\n", abar);
3ac83935 SG	76	/* CAP (HBA Capabilities) : enable power management */
	77	reg32 = readl(abar + 0x00);
	78	reg32 \|= 0x0c006000; /* set PSC+SSC+SALP+SSS */
	79	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
	80	/* Set ISS, if available */
	81	if (speed_support) {
	82	reg32 &= ~0x00f00000;
	83	reg32 \|= (speed_support & 0x03) << 20;
	84	}
	85	writel(reg32, abar + 0x00);
	86	/* PI (Ports implemented) */
	87	writel(port_map, abar + 0x0c);
	88	(void) readl(abar + 0x0c); /* Read back 1 */
	89	(void) readl(abar + 0x0c); /* Read back 2 */
	90	/* CAP2 (HBA Capabilities Extended)*/
	91	reg32 = readl(abar + 0x24);
	92	reg32 &= ~0x00000002;
	93	writel(reg32, abar + 0x24);
	94	/* VSP (Vendor Specific Register */
	95	reg32 = readl(abar + 0xa0);
	96	reg32 &= ~0x00000005;
	97	writel(reg32, abar + 0xa0);
	98	} else if (!strcmp(mode, "combined")) {
	99	debug("SATA: Controller in combined mode\n");
	100
	101	/* No AHCI: clear AHCI base */
ddf10c20	102	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935	103	/* And without AHCI BAR no memory decoding */
ddf10c20	104	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	105	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	106	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935	107
ddf10c20	108	dm_pci_write_config8(dev, 0x09, 0x80);
3ac83935 SG	109
3ac83935 SG	110	/* Set timings */
ddf10c20	111	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935	112	IDE_ISP_5_CLOCKS \| IDE_RCT_4_CLOCKS);
ddf10c20	113	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	114	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
	115	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
	116
	117	/* Sync DMA */
ddf10c20 SG	118	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
ddf10c20 SG	119	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
3ac83935 SG	120
	121	common_sata_init(dev, port_map);
	122	} else {
	123	debug("SATA: Controller in plain-ide mode\n");
	124
	125	/* No AHCI: clear AHCI base */
ddf10c20	126	dm_pci_write_bar32(dev, 5, 0x00000000);
3ac83935 SG	127
3ac83935 SG	128	/* And without AHCI BAR no memory decoding */
ddf10c20	129	dm_pci_read_config16(dev, PCI_COMMAND, &reg16);
3ac83935	130	reg16 &= ~PCI_COMMAND_MEMORY;
ddf10c20	131	dm_pci_write_config16(dev, PCI_COMMAND, reg16);
3ac83935 SG	132
	133	/*
	134	* Native mode capable on both primary and secondary (0xa)
	135	* OR'ed with enabled (0x50) = 0xf
	136	*/
ddf10c20	137	dm_pci_write_config8(dev, 0x09, 0x8f);
3ac83935 SG	138
3ac83935 SG	139	/* Set timings */
ddf10c20	140	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE \|
3ac83935 SG	141	IDE_ISP_3_CLOCKS \| IDE_RCT_1_CLOCKS \|
3ac83935 SG	142	IDE_PPE0 \| IDE_IE0 \| IDE_TIME0);
ddf10c20	143	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE \|
3ac83935 SG	144	IDE_SITRE \| IDE_ISP_3_CLOCKS \|
	145	IDE_RCT_1_CLOCKS \| IDE_IE0 \| IDE_TIME0);
	146
	147	/* Sync DMA */
ddf10c20 SG	148	dm_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 \| IDE_PSDE0);
ddf10c20 SG	149	dm_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
3ac83935 SG	150
	151	common_sata_init(dev, port_map);
	152	}
	153
	154	/* Set Gen3 Transmitter settings if needed */
	155	port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
	156	if (port_tx)
9434c7a3	157	pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
3ac83935 SG	158
	159	port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
	160	if (port_tx)
9434c7a3	161	pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
3ac83935 SG	162
3ac83935 SG	163	/* Additional Programming Requirements */
7e4a6ae6 SG	164	pch_common_sir_write(dev, 0x04, 0x00001600);
	165	pch_common_sir_write(dev, 0x28, 0xa0000033);
	166	reg32 = pch_common_sir_read(dev, 0x54);
3ac83935 SG	167	reg32 &= 0xff000000;
3ac83935 SG	168	reg32 \|= 0x5555aa;
7e4a6ae6 SG	169	pch_common_sir_write(dev, 0x54, reg32);
	170	pch_common_sir_write(dev, 0x64, 0xcccc8484);
	171	reg32 = pch_common_sir_read(dev, 0x68);
3ac83935 SG	172	reg32 &= 0xffff0000;
3ac83935 SG	173	reg32 \|= 0xcccc;
7e4a6ae6 SG	174	pch_common_sir_write(dev, 0x68, reg32);
7e4a6ae6 SG	175	reg32 = pch_common_sir_read(dev, 0x78);
3ac83935 SG	176	reg32 &= 0x0000ffff;
3ac83935 SG	177	reg32 \|= 0x88880000;
7e4a6ae6 SG	178	pch_common_sir_write(dev, 0x78, reg32);
	179	pch_common_sir_write(dev, 0x84, 0x001c7000);
	180	pch_common_sir_write(dev, 0x88, 0x88338822);
	181	pch_common_sir_write(dev, 0xa0, 0x001c7000);
	182	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
	183	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
	184	pch_common_sir_write(dev, 0xd4, 0x10000000);
3ac83935	185
9434c7a3 SG	186	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
9434c7a3 SG	187	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
3ac83935 SG	188	}
3ac83935 SG	189
ddf10c20	190	static void bd82x6x_sata_enable(struct udevice *dev)
3ac83935	191	{
ddf10c20	192	const void *blob = gd->fdt_blob;
e160f7d4	193	int node = dev_of_offset(dev);
3ac83935 SG	194	unsigned port_map;
	195	const char *mode;
	196	u16 map = 0;
	197
	198	/*
	199	* Set SATA controller mode early so the resource allocator can
	200	* properly assign IO/Memory resources for the controller.
	201	*/
	202	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
	203	if (mode && !strcmp(mode, "ahci"))
	204	map = 0x0060;
	205	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
	206
	207	map \|= (port_map ^ 0x3f) << 8;
ddf10c20	208	dm_pci_write_config16(dev, 0x90, map);
3ac83935	209	}
d46f2a68 SG	210
	211	static int bd82x6x_sata_probe(struct udevice *dev)
	212	{
9434c7a3 SG	213	struct udevice *pch;
	214	int ret;
	215
3f603cbb	216	ret = uclass_first_device_err(UCLASS_PCH, &pch);
9434c7a3 SG	217	if (ret)
9434c7a3 SG	218	return ret;
9434c7a3	219
d46f2a68	220	if (!(gd->flags & GD_FLG_RELOC))
ddf10c20	221	bd82x6x_sata_enable(dev);
01a67908	222	else
9434c7a3	223	bd82x6x_sata_init(dev, pch);
d46f2a68 SG	224
	225	return 0;
	226	}
	227
	228	static const struct udevice_id bd82x6x_ahci_ids[] = {
	229	{ .compatible = "intel,pantherpoint-ahci" },
	230	{ }
	231	};
	232
	233	U_BOOT_DRIVER(ahci_ivybridge_drv) = {
	234	.name = "ahci_ivybridge",
a219639d	235	.id = UCLASS_AHCI,
d46f2a68 SG	236	.of_match = bd82x6x_ahci_ids,
	237	.probe = bd82x6x_sata_probe,
	238	};