[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/ppc4xx-gpio.h>
#include <asm/errno.h>
#include <usb.h>

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

struct board_bcsr {
	u8	board_id;
	u8	cpld_rev;
	u8	led_user;
	u8	board_status;
	u8	reset_ctrl;
	u8	flash_ctrl;
	u8	eth_ctrl;
	u8	usb_ctrl;
	u8	irq_ctrl;
};

#define BOARD_CANYONLANDS_PCIE	1
#define BOARD_CANYONLANDS_SATA	2
#define BOARD_GLACIER		3
#define BOARD_ARCHES		4

/*
 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
#if defined(CONFIG_ARCHES)
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
}
#else
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#endif

#if defined(CONFIG_ARCHES)
/*
 * FPGA read/write helper macros
 */
static inline int board_fpga_read(int offset)
{
	int data;

	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));

	return data;
}

static inline void board_fpga_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
}

/*
 * CPLD read/write helper macros
 */
static inline int board_cpld_read(int offset)
{
	int data;

	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));

	return data;
}

static inline void board_cpld_write(int offset, int data)
{
	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
#else
static int pvr_460ex(void)
{
	u32 pvr = get_pvr();

	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
	    (pvr == PVR_460EX_RB))
		return 1;

	return 0;
}
#endif	/* defined(CONFIG_ARCHES) */

int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
	u32 sdr0_cust0;
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;

#endif

	/*
	 * Setup the interrupt controller polarities, triggers, etc.
	 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
	mtdcr(UIC0ER, 0x00000000);	/* disable all */
	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC0SR, 0xffffffff);	/* clear all */

	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
	mtdcr(UIC1ER, 0x00000000);	/* disable all */
	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC1SR, 0xffffffff);	/* clear all */

	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
	mtdcr(UIC2ER, 0x00000000);	/* disable all */
	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC2SR, 0xffffffff);	/* clear all */

	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
	mtdcr(UIC3ER, 0x00000000);	/* disable all */
	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(UIC3SR, 0xffffffff);	/* clear all */

#if !defined(CONFIG_ARCHES)
	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);
#endif

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

#if !defined(CONFIG_ARCHES)
	/* Enable ethernet and take out of reset */
	out_8(&bcsr_data->eth_ctrl, 0) ;

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8(&bcsr_data->flash_ctrl, 0) ;
	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	/* Setup PLB4-AHB bridge based on the system address map */
	mtdcr(AHB_TOP, 0x8000004B);
	mtdcr(AHB_BOT, 0x8000004B);

#endif

	return 0;
}

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int board_usb_init(int index, enum usb_init_type init)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Enable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/*
	 * Configure USB-STP pins as alternate and not GPIO
	 * It seems to be neccessary to configure the STP pins as GPIO
	 * input at powerup (perhaps while USB reset is asserted). So
	 * we configure those pins to their "real" function now.
	 */
	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);

	return 0;
}

int usb_board_stop(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	u8 val;

	/* Disable USB host & USB-OTG */
	val = in_8(&bcsr_data->usb_ctrl);
	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
	out_8(&bcsr_data->usb_ctrl, val);

	/* Reconfigure USB-STP pins as input */
	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);

	return 0;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */

#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
	u32 reg;

	if (board_type == BOARD_CANYONLANDS_SATA) {
		/* Put SATA in reset */
		SDR_WRITE(SDR0_SRST1, 0x00020001);

		/* Set the phy for SATA, not PCI-E port 0 */
		reg = SDR_READ(PESDR0_PHY_CTL_RST);
		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
		reg = SDR_READ(PESDR0_L0CLK);
		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
		SDR_WRITE(PESDR0_L0DRV, 0x00000104);

		/* Bring SATA out of reset */
		SDR_WRITE(SDR0_SRST1, 0x00000000);
	}
}
#endif	/* !defined(CONFIG_ARCHES) */

int get_cpu_num(void)
{
	int cpu = NA_OR_UNKNOWN_CPU;

#if defined(CONFIG_ARCHES)
	int cpu_num;

	cpu_num = board_fpga_read(0x3);

	/* sanity check; assume cpu numbering starts and increments from 0 */
	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
		cpu = cpu_num;
#endif

	return cpu;
}

#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
	struct board_bcsr *bcsr_data =
		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	if (pvr_460ex()) {
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
			gd->board_type = BOARD_CANYONLANDS_PCIE;
		else
			gd->board_type = BOARD_CANYONLANDS_SATA;
	} else {
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
		gd->board_type = BOARD_GLACIER;
	}

	switch (gd->board_type) {
	case BOARD_CANYONLANDS_PCIE:
	case BOARD_GLACIER:
		puts(", 2*PCIe");
		break;

	case BOARD_CANYONLANDS_SATA:
		puts(", 1*PCIe/1*SATA");
		break;
	}

	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));

	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	canyonlands_sata_init(gd->board_type);

	return (0);
}

#else	/* defined(CONFIG_ARCHES) */

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	printf("       Revision %02x.%02x ",
				board_fpga_read(0x0), board_fpga_read(0x1));

	gd->board_type = BOARD_ARCHES;

	/* Only CPU0 has access to CPLD registers */
	if (get_cpu_num() == 0) {
		u8 cfg_sw = board_cpld_read(0x1);
		printf("(FPGA=%02x, CPLD=%02x)\n",
				board_fpga_read(0x2), board_cpld_read(0x0));
		printf("       Configuration Switch %d%d%d%d\n",
				((cfg_sw >> 3) & 0x01),
				((cfg_sw >> 2) & 0x01),
				((cfg_sw >> 1) & 0x01),
				((cfg_sw >> 0) & 0x01));
	} else
		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));


	if (s != NULL)
		printf("       Serial# %s\n", s);

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
	/*
	 * Canyonlands with SATA enabled has only one PCIe slot
	 * (2nd one).
	 */
	if (gd->board_type == BOARD_CANYONLANDS_SATA)
		return 1;

	return 0;
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	/*
	 * Clear potential errors resulting from auto-calibration.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return 0;
}

#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;
	u8 val;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	if (pvr_460ex())
		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	else
		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	/*
	 * RTC/M41T62:
	 * Disable square wave output: Batterie will be drained
	 * quickly, when this output is not disabled
	 */
	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
	val &= ~0x40;
	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);

	return 0;
}

#else	/* defined(CONFIG_ARCHES) */

int misc_init_r(void)
{
	u32 eth_cfg = 0;
	u32 eth_pll;
	u32 reg;

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */

	/* enable SGMII mode */
	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
			SDR0_ETH_CFG_SGMII1_ENABLE |
			SDR0_ETH_CFG_SGMII2_ENABLE);

	/* Set EMAC for MDIO */
	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;

	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);

	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/* reset all SGMII interfaces */
	mfsdr(SDR0_SRST1,   reg);
	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
	mtsdr(SDR0_SRST1, reg);
	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	mtsdr(SDR0_SRST1,   0x00000000);

	do {
		mfsdr(SDR0_ETH_PLL, eth_pll);
	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));

	return 0;
}
#endif	/* !defined(CONFIG_ARCHES) */

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
extern int __ft_board_setup(void *blob, bd_t *bd);

int ft_board_setup(void *blob, bd_t *bd)
{
	__ft_board_setup(blob, bd);

	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
		/*
		 * When SATA is selected we need to disable the first PCIe
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
		/*
		 * When PCIe is selected we need to disable the SATA
		 * node in the device tree, so that Linux doesn't initialize
		 * it.
		 */
		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
				     "disabled", sizeof("disabled"), 1);
	}

	return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
8e1a3fe5 SR	6	*/
	7
	8	#include <common.h>
b36df561	9	#include <asm/ppc440.h>
8e1a3fe5 SR	10	#include <libfdt.h>
8e1a3fe5 SR	11	#include <fdt_support.h>
212ed906	12	#include <i2c.h>
8e1a3fe5 SR	13	#include <asm/processor.h>
	14	#include <asm/io.h>
	15	#include <asm/mmu.h>
	16	#include <asm/4xx_pcie.h>
09887762	17	#include <asm/ppc4xx-gpio.h>
06dfaeef	18	#include <asm/errno.h>
16297cfb	19	#include <usb.h>
8e1a3fe5	20
6d0f6bcf	21	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
8e1a3fe5 SR	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
98303292 SR	25	struct board_bcsr {
	26	u8 board_id;
	27	u8 cpld_rev;
	28	u8 led_user;
	29	u8 board_status;
	30	u8 reset_ctrl;
	31	u8 flash_ctrl;
	32	u8 eth_ctrl;
	33	u8 usb_ctrl;
	34	u8 irq_ctrl;
17a68444	35	};
cc8e839a SR	36
	37	#define BOARD_CANYONLANDS_PCIE 1
	38	#define BOARD_CANYONLANDS_SATA 2
	39	#define BOARD_GLACIER 3
f09f09d3 AG	40	#define BOARD_ARCHES 4
f09f09d3 AG	41
f3ed3c9b	42	/*
a47a12be	43	* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
f3ed3c9b SR	44	* board specific values.
	45	*/
	46	#if defined(CONFIG_ARCHES)
	47	u32 ddr_wrdtr(u32 default_val) {
	48	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_0_DEG \| 0x823);
	49	}
	50	#else
	51	u32 ddr_wrdtr(u32 default_val) {
	52	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
	53	}
	54
	55	u32 ddr_clktr(u32 default_val) {
	56	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
	57	}
	58	#endif
	59
f09f09d3 AG	60	#if defined(CONFIG_ARCHES)
	61	/*
	62	* FPGA read/write helper macros
	63	*/
	64	static inline int board_fpga_read(int offset)
	65	{
	66	int data;
	67
	68	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
	69
	70	return data;
	71	}
	72
	73	static inline void board_fpga_write(int offset, int data)
	74	{
	75	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
	76	}
	77
	78	/*
	79	* CPLD read/write helper macros
	80	*/
	81	static inline int board_cpld_read(int offset)
	82	{
	83	int data;
	84
	85	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	86	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
	87
	88	return data;
	89	}
	90
	91	static inline void board_cpld_write(int offset, int data)
	92	{
	93	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
	94	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
	95	}
c3fa4f0c SR	96	#else
	97	static int pvr_460ex(void)
	98	{
	99	u32 pvr = get_pvr();
	100
	101	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA) \|\|
	102	(pvr == PVR_460EX_RB))
	103	return 1;
	104
	105	return 0;
	106	}
f09f09d3	107	#endif /* defined(CONFIG_ARCHES) */
cc8e839a	108
8e1a3fe5 SR	109	int board_early_init_f(void)
8e1a3fe5 SR	110	{
f09f09d3	111	#if !defined(CONFIG_ARCHES)
8e1a3fe5	112	u32 sdr0_cust0;
17a68444 RS	113	struct board_bcsr *bcsr_data =
	114	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	115
f09f09d3	116	#endif
8e1a3fe5	117
1c2926ab	118	/*
8e1a3fe5	119	* Setup the interrupt controller polarities, triggers, etc.
1c2926ab	120	*/
952e7760 SR	121	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	122	mtdcr(UIC0ER, 0x00000000); /* disable all */
	123	mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
	124	mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
	125	mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
	126	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
	127	mtdcr(UIC0SR, 0xffffffff); /* clear all */
	128
	129	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	130	mtdcr(UIC1ER, 0x00000000); /* disable all */
	131	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	132	mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
	133	mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
	134	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
	135	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	136
	137	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	138	mtdcr(UIC2ER, 0x00000000); /* disable all */
	139	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	140	mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
	141	mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
	142	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
	143	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	144
	145	mtdcr(UIC3SR, 0xffffffff); /* clear all */
	146	mtdcr(UIC3ER, 0x00000000); /* disable all */
	147	mtdcr(UIC3CR, 0x00000000); /* all non-critical */
	148	mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
	149	mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
	150	mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
	151	mtdcr(UIC3SR, 0xffffffff); /* clear all */
8e1a3fe5	152
f09f09d3	153	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	154	/* SDR Setting - enable NDFC */
	155	mfsdr(SDR0_CUST0, sdr0_cust0);
	156	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
	157	SDR0_CUST0_NDFC_ENABLE \|
	158	SDR0_CUST0_NDFC_BW_8_BIT \|
	159	SDR0_CUST0_NDFC_ARE_MASK \|
	160	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
6d0f6bcf	161	(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
8e1a3fe5	162	mtsdr(SDR0_CUST0, sdr0_cust0);
f09f09d3	163	#endif
8e1a3fe5 SR	164
	165	/*
	166	* Configure PFC (Pin Function Control) registers
	167	* UART0: 4 pins
	168	*/
	169	mtsdr(SDR0_PFC1, 0x00040000);
	170
	171	/* Enable PCI host functionality in SDR0_PCI0 */
	172	mtsdr(SDR0_PCI0, 0xe0000000);
	173
f09f09d3	174	#if !defined(CONFIG_ARCHES)
8e1a3fe5	175	/* Enable ethernet and take out of reset */
17a68444	176	out_8(&bcsr_data->eth_ctrl, 0) ;
8e1a3fe5 SR	177
8e1a3fe5 SR	178	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
17a68444	179	out_8(&bcsr_data->flash_ctrl, 0) ;
8e1a3fe5 SR	180	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
8e1a3fe5 SR	181
41712b4e SR	182	/* Setup PLB4-AHB bridge based on the system address map */
	183	mtdcr(AHB_TOP, 0x8000004B);
	184	mtdcr(AHB_BOT, 0x8000004B);
	185
f09f09d3	186	#endif
41712b4e	187
8e1a3fe5 SR	188	return 0;
	189	}
	190
17a68444	191	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
bba67914	192	int board_usb_init(int index, enum usb_init_type init)
17a68444 RS	193	{
	194	struct board_bcsr *bcsr_data =
	195	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	196	u8 val;
	197
	198	/* Enable USB host & USB-OTG */
	199	val = in_8(&bcsr_data->usb_ctrl);
	200	val &= ~(BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	201	out_8(&bcsr_data->usb_ctrl, val);
	202
709d9481 RS	203	/*
	204	* Configure USB-STP pins as alternate and not GPIO
	205	* It seems to be neccessary to configure the STP pins as GPIO
	206	* input at powerup (perhaps while USB reset is asserted). So
	207	* we configure those pins to their "real" function now.
	208	*/
	209	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	210	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	211
17a68444 RS	212	return 0;
	213	}
	214
	215	int usb_board_stop(void)
	216	{
	217	struct board_bcsr *bcsr_data =
	218	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
	219	u8 val;
	220
	221	/* Disable USB host & USB-OTG */
	222	val = in_8(&bcsr_data->usb_ctrl);
	223	val \|= (BCSR_USBCTRL_OTG_RST \| BCSR_USBCTRL_HOST_RST);
	224	out_8(&bcsr_data->usb_ctrl, val);
	225
709d9481 RS	226	/* Reconfigure USB-STP pins as input */
	227	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	228	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
	229
17a68444 RS	230	return 0;
	231	}
	232
bba67914	233	int board_usb_cleanup(int index, enum usb_init_type init)
17a68444 RS	234	{
	235	return usb_board_stop();
	236	}
	237	#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
	238
f09f09d3	239	#if !defined(CONFIG_ARCHES)
1c2926ab SR	240	static void canyonlands_sata_init(int board_type)
	241	{
	242	u32 reg;
	243
	244	if (board_type == BOARD_CANYONLANDS_SATA) {
	245	/* Put SATA in reset */
	246	SDR_WRITE(SDR0_SRST1, 0x00020001);
	247
	248	/* Set the phy for SATA, not PCI-E port 0 */
	249	reg = SDR_READ(PESDR0_PHY_CTL_RST);
	250	SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) \| 0x00000001);
	251	reg = SDR_READ(PESDR0_L0CLK);
	252	SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) \| 0x00000007);
	253	SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
	254	SDR_WRITE(PESDR0_L0DRV, 0x00000104);
	255
	256	/* Bring SATA out of reset */
	257	SDR_WRITE(SDR0_SRST1, 0x00000000);
	258	}
	259	}
f09f09d3 AG	260	#endif /* !defined(CONFIG_ARCHES) */
	261
	262	int get_cpu_num(void)
	263	{
	264	int cpu = NA_OR_UNKNOWN_CPU;
	265
	266	#if defined(CONFIG_ARCHES)
	267	int cpu_num;
	268
	269	cpu_num = board_fpga_read(0x3);
	270
	271	/* sanity check; assume cpu numbering starts and increments from 0 */
	272	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
	273	cpu = cpu_num;
	274	#endif
	275
	276	return cpu;
	277	}
1c2926ab	278
f09f09d3	279	#if !defined(CONFIG_ARCHES)
1c2926ab	280	int checkboard(void)
8e1a3fe5	281	{
17a68444 RS	282	struct board_bcsr *bcsr_data =
17a68444 RS	283	(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
f0c0b3a9 WD	284	char buf[64];
f0c0b3a9 WD	285	int i = getenv_f("serial#", buf, sizeof(buf));
8e1a3fe5	286
c3fa4f0c	287	if (pvr_460ex()) {
8e1a3fe5	288	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
17a68444	289	if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
cc8e839a SR	290	gd->board_type = BOARD_CANYONLANDS_PCIE;
	291	else
	292	gd->board_type = BOARD_CANYONLANDS_SATA;
c3fa4f0c SR	293	} else {
	294	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	295	gd->board_type = BOARD_GLACIER;
cc8e839a SR	296	}
	297
	298	switch (gd->board_type) {
	299	case BOARD_CANYONLANDS_PCIE:
	300	case BOARD_GLACIER:
	301	puts(", 2*PCIe");
	302	break;
	303
	304	case BOARD_CANYONLANDS_SATA:
	305	puts(", 1PCIe/1SATA");
	306	break;
	307	}
	308
17a68444	309	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
8e1a3fe5	310
f0c0b3a9	311	if (i > 0) {
8e1a3fe5	312	puts(", serial# ");
f0c0b3a9	313	puts(buf);
8e1a3fe5 SR	314	}
	315	putc('\n');
	316
1c2926ab SR	317	canyonlands_sata_init(gd->board_type);
1c2926ab SR	318
8e1a3fe5 SR	319	return (0);
	320	}
	321
f09f09d3 AG	322	#else /* defined(CONFIG_ARCHES) */
	323
	324	int checkboard(void)
	325	{
	326	char *s = getenv("serial#");
	327
	328	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
	329	printf(" Revision %02x.%02x ",
	330	board_fpga_read(0x0), board_fpga_read(0x1));
	331
	332	gd->board_type = BOARD_ARCHES;
	333
	334	/* Only CPU0 has access to CPLD registers */
	335	if (get_cpu_num() == 0) {
	336	u8 cfg_sw = board_cpld_read(0x1);
	337	printf("(FPGA=%02x, CPLD=%02x)\n",
	338	board_fpga_read(0x2), board_cpld_read(0x0));
	339	printf(" Configuration Switch %d%d%d%d\n",
	340	((cfg_sw >> 3) & 0x01),
	341	((cfg_sw >> 2) & 0x01),
	342	((cfg_sw >> 1) & 0x01),
	343	((cfg_sw >> 0) & 0x01));
	344	} else
	345	printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
	346
	347
	348	if (s != NULL)
	349	printf(" Serial# %s\n", s);
	350
	351	return 0;
	352	}
	353	#endif /* !defined(CONFIG_ARCHES) */
	354
8e1a3fe5	355	#if defined(CONFIG_PCI)
b0b86746	356	int board_pcie_first(void)
8e1a3fe5	357	{
cc8e839a SR	358	/*
	359	* Canyonlands with SATA enabled has only one PCIe slot
	360	* (2nd one).
	361	*/
	362	if (gd->board_type == BOARD_CANYONLANDS_SATA)
b0b86746	363	return 1;
8e1a3fe5	364
b0b86746	365	return 0;
8e1a3fe5 SR	366	}
	367	#endif /* CONFIG_PCI */
	368
	369	int board_early_init_r (void)
	370	{
	371	/*
	372	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	373	* boot EBC mapping only supports a maximum of 16MBytes
	374	* (4.ff00.0000 - 4.ffff.ffff).
	375	* To solve this problem, the FLASH has to get remapped to another
	376	* EBC address which accepts bigger regions:
	377	*
	378	* 0xfc00.0000 -> 4.cc00.0000
8e1a3fe5 SR	379	*/
	380
	381	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
d1c3b275	382	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L \| 0xda000);
8e1a3fe5 SR	383
8e1a3fe5 SR	384	/* Remove TLB entry of boot EBC mapping */
6d0f6bcf	385	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
8e1a3fe5 SR	386
8e1a3fe5 SR	387	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
6d0f6bcf	388	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
8e1a3fe5 SR	389	TLB_WORD2_I_ENABLE);
	390
	391	/*
	392	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	393	* 0xfc00.0000 is possible
	394	*/
	395
71665ebf SR	396	/*
	397	* Clear potential errors resulting from auto-calibration.
	398	* If not done, then we could get an interrupt later on when
	399	* exceptions are enabled.
	400	*/
	401	set_mcsr(get_mcsr());
	402
8e1a3fe5 SR	403	return 0;
	404	}
	405
f09f09d3	406	#if !defined(CONFIG_ARCHES)
8e1a3fe5 SR	407	int misc_init_r(void)
	408	{
	409	u32 sdr0_srst1 = 0;
	410	u32 eth_cfg;
212ed906	411	u8 val;
8e1a3fe5 SR	412
	413	/*
	414	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	415	* This is board specific, so let's do it here.
	416	*/
	417	mfsdr(SDR0_ETH_CFG, eth_cfg);
	418	/* disable SGMII mode */
	419	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
	420	SDR0_ETH_CFG_SGMII1_ENABLE \|
	421	SDR0_ETH_CFG_SGMII0_ENABLE);
	422	/* Set the for 2 RGMII mode */
	423	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	424	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
c3fa4f0c	425	if (pvr_460ex())
4c9e8557 SR	426	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	427	else
	428	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
8e1a3fe5 SR	429	mtsdr(SDR0_ETH_CFG, eth_cfg);
	430
	431	/*
	432	* The AHB Bridge core is held in reset after power-on or reset
	433	* so enable it now
	434	*/
	435	mfsdr(SDR0_SRST1, sdr0_srst1);
	436	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	437	mtsdr(SDR0_SRST1, sdr0_srst1);
	438
212ed906 SR	439	/*
	440	* RTC/M41T62:
	441	* Disable square wave output: Batterie will be drained
	442	* quickly, when this output is not disabled
	443	*/
6d0f6bcf	444	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
212ed906	445	val &= ~0x40;
6d0f6bcf	446	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
212ed906	447
8e1a3fe5 SR	448	return 0;
	449	}
	450
f09f09d3 AG	451	#else /* defined(CONFIG_ARCHES) */
	452
	453	int misc_init_r(void)
	454	{
	455	u32 eth_cfg = 0;
	456	u32 eth_pll;
	457	u32 reg;
	458
	459	/*
	460	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	461	* This is board specific, so let's do it here.
	462	*/
	463
	464	/* enable SGMII mode */
	465	eth_cfg \|= (SDR0_ETH_CFG_SGMII0_ENABLE \|
	466	SDR0_ETH_CFG_SGMII1_ENABLE \|
	467	SDR0_ETH_CFG_SGMII2_ENABLE);
	468
	469	/* Set EMAC for MDIO */
	470	eth_cfg \|= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
	471
	472	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
	473	eth_cfg \|= (SDR0_ETH_CFG_TAHOE0_BYPASS \| SDR0_ETH_CFG_TAHOE1_BYPASS);
	474
	475	mtsdr(SDR0_ETH_CFG, eth_cfg);
	476
	477	/* reset all SGMII interfaces */
	478	mfsdr(SDR0_SRST1, reg);
	479	reg \|= (SDR0_SRST1_SGMII0 \| SDR0_SRST1_SGMII1 \| SDR0_SRST1_SGMII2);
	480	mtsdr(SDR0_SRST1, reg);
	481	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
	482	mtsdr(SDR0_SRST1, 0x00000000);
	483
	484	do {
	485	mfsdr(SDR0_ETH_PLL, eth_pll);
	486	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
	487
	488	return 0;
	489	}
	490	#endif /* !defined(CONFIG_ARCHES) */
	491
8e1a3fe5	492	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	493	extern int __ft_board_setup(void blob, bd_t bd);
26d37f00	494
e895a4b0	495	int ft_board_setup(void blob, bd_t bd)
8e1a3fe5	496	{
26d37f00	497	__ft_board_setup(blob, bd);
8e1a3fe5	498
16bedc66 SR	499	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
	500	/*
	501	* When SATA is selected we need to disable the first PCIe
	502	* node in the device tree, so that Linux doesn't initialize
	503	* it.
	504	*/
8fd4166c SR	505	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
8fd4166c SR	506	"disabled", sizeof("disabled"), 1);
16bedc66 SR	507	}
	508
	509	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
	510	/*
	511	* When PCIe is selected we need to disable the SATA
	512	* node in the device tree, so that Linux doesn't initialize
	513	* it.
	514	*/
8fd4166c SR	515	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
8fd4166c SR	516	"disabled", sizeof("disabled"), 1);
16bedc66	517	}
e895a4b0 SG	518
e895a4b0 SG	519	return 0;
8e1a3fe5 SR	520	}
8e1a3fe5 SR	521	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */