projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0a20e534 LW |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * Linaro | |
| 4 | * Linus Walleij <linus.walleij@linaro.org> | |
| 5 | * Register definitions for the System Controller (SC) and | |
| 6 | * the similar "CP Controller" found in the ARM Integrator/AP and | |
| 7 | * Integrator/CP reference designs | |
| 8 | * | |
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 0a20e534 LW |
10 | */ |
| 11 | ||
| 12 | #ifndef __ARM_SC_H | |
| 13 | #define __ARM_SC_H | |
| 14 | ||
| 15 | #define SC_BASE 0x11000000 | |
| 16 | ||
| 17 | /* | |
| 18 | * The system controller registers | |
| 19 | */ | |
| 20 | #define SC_ID_OFFSET 0x00 | |
| 21 | #define SC_OSC_OFFSET 0x04 | |
| 22 | /* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ | |
| 23 | #define SC_OSC_DIVXY (1 << 8) | |
| 24 | #define SC_CTRLS_OFFSET 0x08 | |
| 25 | #define SC_CTRLC_OFFSET 0x0C | |
| 26 | /* Set bits by writing CTRLS, clear bits by writing CTRLC */ | |
| 27 | #define SC_CTRL_SOFTRESET (1 << 0) | |
| 28 | #define SC_CTRL_FLASHVPP (1 << 1) | |
| 29 | #define SC_CTRL_FLASHWP (1 << 2) | |
| 30 | #define SC_CTRL_UART1DTR (1 << 4) | |
| 31 | #define SC_CTRL_UART1RTS (1 << 5) | |
| 32 | #define SC_CTRL_UART0DTR (1 << 6) | |
| 33 | #define SC_CTRL_UART0RTS (1 << 7) | |
| 34 | #define SC_DEC_OFFSET 0x10 | |
| 35 | #define SC_ARB_OFFSET 0x14 | |
| 36 | #define SC_PCI_OFFSET 0x18 | |
| 37 | #define SC_PCI_PCIEN (1 << 0) | |
| 38 | #define SC_PCI_PCIBINT_CLR (1 << 1) | |
| 39 | #define SC_LOCK_OFFSET 0x1C | |
| 40 | #define SC_LBFADDR_OFFSET 0x20 | |
| 41 | #define SC_LBFCODE_OFFSET 0x24 | |
| 42 | ||
| 43 | #define SC_ID (SC_BASE + SC_ID_OFFSET) | |
| 44 | #define SC_OSC (SC_BASE + SC_OSC_OFFSET) | |
| 45 | #define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET) | |
| 46 | #define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET) | |
| 47 | #define SC_DEC (SC_BASE + SC_DEC_OFFSET) | |
| 48 | #define SC_ARB (SC_BASE + SC_ARB_OFFSET) | |
| 49 | #define SC_PCI (SC_BASE + SC_PCI_OFFSET) | |
| 50 | #define SC_LOCK (SC_BASE + SC_LOCK_OFFSET) | |
| 51 | #define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET) | |
| 52 | #define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET) | |
| 53 | ||
| 54 | /* | |
| 55 | * The Integrator/CP as a smaller set of registers, at a different | |
| 56 | * offset - probably not to disturb old software. | |
| 57 | */ | |
| 58 | ||
| 59 | #define CP_BASE 0xCB000000 | |
| 60 | ||
| 61 | #define CP_IDFIELD_OFFSET 0x00 | |
| 62 | #define CP_FLASHPROG_OFFSET 0x04 | |
| 63 | #define CP_FLASHPROG_FLVPPEN (1 << 0) | |
| 64 | #define CP_FLASHPROG_FLWREN (1 << 1) | |
| 65 | #define CP_FLASHPROG_FLASHSIZE (1 << 2) | |
| 66 | #define CP_FLASHPROG_EXTRABANK (1 << 3) | |
| 67 | #define CP_INTREG_OFFSET 0x08 | |
| 68 | #define CP_DECODE_OFFSET 0x0C | |
| 69 | ||
| 70 | #define CP_IDFIELD (CP_BASE + CP_ID_OFFSET) | |
| 71 | #define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET) | |
| 72 | #define CP_INTREG (CP_BASE + CP_INTREG_OFFSET) | |
| 73 | #define CP_DECODE (CP_BASE + CP_DECODE_OFFSET) | |
| 74 | ||
| 75 | #endif |