[people/ms/u-boot.git] / board / atum8548 / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 Initializations */
	/*
	 * TLB 0, 1:	128M	Non-cacheable, guarded
	 * 0xf8000000	128M	FLASH
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 0, BOOKE_PAGESZ_64M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 2:	1G	Non-cacheable, guarded
	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 2, BOOKE_PAGESZ_1G, 1),

	/*
	 * TLB 3, 4:	512M	Non-cacheable, guarded
	 * 0xc0000000	1G	PCI2
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	64M	Non-cacheable, guarded
	 * 0xe000_0000	1M	CCSRBAR
	 * 0xe200_0000	1M	PCI1 IO
	 * 0xe210_0000	1M	PCI2 IO
	 * 0xe300_0000	1M	PCIe IO
	 */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_64M, 1),
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
80d0b6a1 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/mmu.h>
	28
	29	struct fsl_e_tlb_entry tlb_table[] = {
	30	/* TLB 0 - for temp stack in cache */
6d0f6bcf	31	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
80d0b6a1 KG	32	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
80d0b6a1 KG	33	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	34	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
80d0b6a1 KG	35	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
80d0b6a1 KG	36	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	37	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
80d0b6a1 KG	38	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
80d0b6a1 KG	39	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf	40	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
80d0b6a1 KG	41	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	42	0, 0, BOOKE_PAGESZ_4K, 0),
	43
	44	/* TLB 1 Initializations */
	45	/*
	46	* TLB 0, 1: 128M Non-cacheable, guarded
	47	* 0xf8000000 128M FLASH
	48	* Out of reset this entry is only 4K.
	49	*/
6d0f6bcf	50	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000,
80d0b6a1 KG	51	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	52	0, 0, BOOKE_PAGESZ_64M, 1),
	53
6d0f6bcf	54	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
80d0b6a1 KG	55	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	56	0, 1, BOOKE_PAGESZ_64M, 1),
	57
	58	/*
	59	* TLB 2: 1G Non-cacheable, guarded
	60	* 0x80000000 1G PCI1/PCIE 8,9,a,b
	61	*/
6d0f6bcf	62	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
80d0b6a1 KG	63	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	64	0, 2, BOOKE_PAGESZ_1G, 1),
	65
	66	/*
	67	* TLB 3, 4: 512M Non-cacheable, guarded
	68	* 0xc0000000 1G PCI2
	69	*/
6d0f6bcf	70	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
80d0b6a1 KG	71	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	72	0, 3, BOOKE_PAGESZ_256M, 1),
	73
6d0f6bcf	74	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
80d0b6a1 KG	75	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	76	0, 4, BOOKE_PAGESZ_256M, 1),
	77
	78	/*
	79	* TLB 5: 64M Non-cacheable, guarded
	80	* 0xe000_0000 1M CCSRBAR
	81	* 0xe200_0000 1M PCI1 IO
	82	* 0xe210_0000 1M PCI2 IO
	83	* 0xe300_0000 1M PCIe IO
	84	*/
6d0f6bcf	85	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
80d0b6a1 KG	86	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	87	0, 5, BOOKE_PAGESZ_64M, 1),
	88	};
	89
	90	int num_tlb_entries = ARRAY_SIZE(tlb_table);