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nitrogen6x: display: add svga display (800x600)
[people/ms/u-boot.git] / board / boundary / nitrogen6x / nitrogen6x.c
CommitLineData
d67b0d97
EN		 1/*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
d67b0d97
EN		 6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/sys_proto.h>
14#include <malloc.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/errno.h>
17#include <asm/gpio.h>
18#include <asm/imx-common/iomux-v3.h>
19#include <asm/imx-common/mxc_i2c.h>
164d9846 20#include <asm/imx-common/sata.h>
d67b0d97 21#include <asm/imx-common/boot_mode.h>
a47e4495 22#include <asm/imx-common/video.h>
d67b0d97
EN		 23#include <mmc.h>
24#include <fsl_esdhc.h>
25#include <micrel.h>
26#include <miiphy.h>
27#include <netdev.h>
d67b0d97
EN		 28#include <asm/arch/crm_regs.h>
29#include <asm/arch/mxc_hdmi.h>
30#include <i2c.h>
9fc42527
EN		 31#include <input.h>
32#include <netdev.h>
84caf0b2 33#include <usb/ehci-fsl.h>
d67b0d97
EN		 34
35DECLARE_GLOBAL_DATA_PTR;
08ce074e 36#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
d67b0d97 37
7e2173cf
BT		 38#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
d67b0d97 41
7e2173cf
BT		 42#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
d67b0d97 45
7e2173cf
BT		 46#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
d67b0d97 48
7e2173cf 49#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
d67b0d97
EN		 50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
7e2173cf
BT		 52#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
d67b0d97 54
7e2173cf
BT		 55#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
d67b0d97
EN		 57 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
58
7e2173cf
BT		 59#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
d67b0d97
EN		 61 PAD_CTL_SRE_SLOW)
62
7e2173cf
BT		 63#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
65 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
d67b0d97
EN		 66
67#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
68
69int dram_init(void)
70{
19a0f7fa 71 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
d67b0d97
EN		 72
73 return 0;
74}
75
9fc42527 76static iomux_v3_cfg_t const uart1_pads[] = {
10fda487
EN		 77 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
d67b0d97
EN		 79};
80
9fc42527 81static iomux_v3_cfg_t const uart2_pads[] = {
10fda487
EN		 82 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
d67b0d97
EN		 84};
85
86#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
87
88/* I2C1, SGTL5000 */
9fc42527 89static struct i2c_pads_info i2c_pad_info0 = {
d67b0d97
EN		 90 .scl = {
91 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
10fda487 92 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
d67b0d97
EN		 93 .gp = IMX_GPIO_NR(3, 21)
94 },
95 .sda = {
96 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
10fda487 97 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
d67b0d97
EN		 98 .gp = IMX_GPIO_NR(3, 28)
99 }
100};
101
102/* I2C2 Camera, MIPI */
9fc42527 103static struct i2c_pads_info i2c_pad_info1 = {
d67b0d97
EN		 104 .scl = {
105 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
10fda487 106 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
d67b0d97
EN		 107 .gp = IMX_GPIO_NR(4, 12)
108 },
109 .sda = {
110 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
10fda487 111 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
d67b0d97
EN		 112 .gp = IMX_GPIO_NR(4, 13)
113 }
114};
115
116/* I2C3, J15 - RGB connector */
9fc42527 117static struct i2c_pads_info i2c_pad_info2 = {
d67b0d97
EN		 118 .scl = {
119 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
10fda487 120 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
d67b0d97
EN		 121 .gp = IMX_GPIO_NR(1, 5)
122 },
123 .sda = {
124 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
10fda487 125 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
d67b0d97
EN		 126 .gp = IMX_GPIO_NR(7, 11)
127 }
128};
129
41612472
EN		 130static iomux_v3_cfg_t const usdhc2_pads[] = {
131 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137};
138
9fc42527 139static iomux_v3_cfg_t const usdhc3_pads[] = {
10fda487
EN		 140 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
d67b0d97
EN		 147};
148
9fc42527 149static iomux_v3_cfg_t const usdhc4_pads[] = {
10fda487
EN		 150 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
d67b0d97
EN		 157};
158
9fc42527 159static iomux_v3_cfg_t const enet_pads1[] = {
d67b0d97
EN		 160 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
161 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487
EN		 162 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
d67b0d97
EN		 167 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 /* pin 35 - 1 (PHY_AD2) on reset */
10fda487 170 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 171 /* pin 32 - 1 - (MODE0) all */
10fda487 172 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 173 /* pin 31 - 1 - (MODE1) all */
10fda487 174 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 175 /* pin 28 - 1 - (MODE2) all */
10fda487 176 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 177 /* pin 27 - 1 - (MODE3) all */
10fda487 178 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 179 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
10fda487 180 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 181 /* pin 42 PHY nRST */
10fda487
EN		 182 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
183 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 184};
185
9fc42527 186static iomux_v3_cfg_t const enet_pads2[] = {
10fda487
EN		 187 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
188 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
189 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
190 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
191 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
d67b0d97
EN		 192 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
193};
194
08ce074e
TK		 195static iomux_v3_cfg_t const misc_pads[] = {
196 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
10fda487
EN		 197 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
198 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
08ce074e 199 /* OTG Power enable */
10fda487 200 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
08ce074e
TK		 201};
202
d67b0d97 203/* wl1271 pads on nitrogen6x */
9fc42527 204static iomux_v3_cfg_t const wl12xx_pads[] = {
10fda487 205 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
d67b0d97 206 | MUX_PAD_CTRL(WEAK_PULLDOWN),
10fda487 207 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
d67b0d97 208 | MUX_PAD_CTRL(OUTPUT_40OHM),
10fda487 209 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
d67b0d97
EN		 210 | MUX_PAD_CTRL(OUTPUT_40OHM),
211};
212#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
213#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
214#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
215
216/* Button assignments for J14 */
217static iomux_v3_cfg_t const button_pads[] = {
218 /* Menu */
10fda487 219 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 220 /* Back */
10fda487 221 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 222 /* Labelled Search (mapped to Power under Android) */
10fda487 223 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 224 /* Home */
10fda487 225 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 226 /* Volume Down */
10fda487 227 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 228 /* Volume Up */
10fda487 229 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97
EN		 230};
231
232static void setup_iomux_enet(void)
233{
234 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
235 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
236 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
237 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
238 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
239 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
240 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
241 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
242 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
243
244 /* Need delay 10ms according to KSZ9021 spec */
245 udelay(1000 * 10);
246 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
247 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
248
249 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
adc4a2bd 250 udelay(100); /* Wait 100 us before using mii interface */
d67b0d97
EN		 251}
252
9fc42527 253static iomux_v3_cfg_t const usb_pads[] = {
10fda487 254 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 255};
256
257static void setup_iomux_uart(void)
258{
259 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
260 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
261}
262
263#ifdef CONFIG_USB_EHCI_MX6
264int board_ehci_hcd_init(int port)
265{
266 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
267
268 /* Reset USB hub */
269 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
270 mdelay(2);
271 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
272
273 return 0;
274}
08ce074e
TK		 275
276int board_ehci_power(int port, int on)
277{
278 if (port)
279 return 0;
280 gpio_set_value(GP_USB_OTG_PWR, on);
281 return 0;
282}
283
d67b0d97
EN		 284#endif
285
286#ifdef CONFIG_FSL_ESDHC
9fc42527 287static struct fsl_esdhc_cfg usdhc_cfg[2] = {
d67b0d97
EN		 288 {USDHC3_BASE_ADDR},
289 {USDHC4_BASE_ADDR},
290};
291
292int board_mmc_getcd(struct mmc *mmc)
293{
294 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
213e9e33
TK		 295 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
296 IMX_GPIO_NR(2, 6);
d67b0d97 297
213e9e33
TK		 298 gpio_direction_input(gp_cd);
299 return !gpio_get_value(gp_cd);
d67b0d97
EN		 300}
301
302int board_mmc_init(bd_t *bis)
303{
304 s32 status = 0;
305 u32 index = 0;
306
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
308 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
309
aad4659a
AR		 310 usdhc_cfg[0].max_bus_width = 4;
311 usdhc_cfg[1].max_bus_width = 4;
312
d67b0d97
EN		 313 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
314 switch (index) {
315 case 0:
316 imx_iomux_v3_setup_multiple_pads(
317 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
318 break;
319 case 1:
320 imx_iomux_v3_setup_multiple_pads(
321 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
322 break;
323 default:
324 printf("Warning: you configured more USDHC controllers"
325 "(%d) then supported by the board (%d)\n",
326 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
327 return status;
328 }
329
330 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
331 }
332
333 return status;
334}
335#endif
336
d67b0d97 337#ifdef CONFIG_MXC_SPI
9fc42527 338static iomux_v3_cfg_t const ecspi1_pads[] = {
d67b0d97 339 /* SS1 */
3b31605a 340 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 341 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
342 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
343 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
344};
345
9fc42527 346static void setup_spi(void)
d67b0d97 347{
d67b0d97
EN		 348 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
349 ARRAY_SIZE(ecspi1_pads));
350}
351#endif
352
353int board_phy_config(struct phy_device *phydev)
354{
355 /* min rx data delay */
356 ksz9021_phy_extended_write(phydev,
357 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
358 /* min tx data delay */
359 ksz9021_phy_extended_write(phydev,
360 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
361 /* max rx/tx clock delay, min rx/tx control */
362 ksz9021_phy_extended_write(phydev,
363 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
364 if (phydev->drv->config)
365 phydev->drv->config(phydev);
366
367 return 0;
368}
369
370int board_eth_init(bd_t *bis)
371{
372 uint32_t base = IMX_FEC_BASE;
373 struct mii_dev *bus = NULL;
374 struct phy_device *phydev = NULL;
375 int ret;
376
377 setup_iomux_enet();
378
379#ifdef CONFIG_FEC_MXC
380 bus = fec_get_miibus(base, -1);
381 if (!bus)
382 return 0;
383 /* scan phy 4,5,6,7 */
384 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
385 if (!phydev) {
386 free(bus);
387 return 0;
388 }
389 printf("using phy at %d\n", phydev->addr);
390 ret = fec_probe(bis, -1, base, bus, phydev);
391 if (ret) {
392 printf("FEC MXC: %s:failed\n", __func__);
393 free(phydev);
394 free(bus);
395 }
396#endif
08ce074e 397
f016f8ca 398#ifdef CONFIG_CI_UDC
08ce074e
TK		 399 /* For otg ethernet*/
400 usb_eth_initialize(bis);
401#endif
d67b0d97
EN		 402 return 0;
403}
404
405static void setup_buttons(void)
406{
407 imx_iomux_v3_setup_multiple_pads(button_pads,
408 ARRAY_SIZE(button_pads));
409}
410
d67b0d97
EN		 411#if defined(CONFIG_VIDEO_IPUV3)
412
413static iomux_v3_cfg_t const backlight_pads[] = {
414 /* Backlight on RGB connector: J15 */
10fda487 415 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 416#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
417
418 /* Backlight on LVDS connector: J6 */
10fda487 419 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 420#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
421};
422
423static iomux_v3_cfg_t const rgb_pads[] = {
424 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
425 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
10fda487
EN		 426 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
427 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
428 MX6_PAD_DI0_PIN4__GPIO4_IO20,
429 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
430 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
431 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
432 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
433 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
434 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
435 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
436 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
437 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
438 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
439 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
440 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
441 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
442 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
443 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
444 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
445 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
446 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
447 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
448 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
449 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
450 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
451 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
452 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
d67b0d97
EN		 453};
454
5ea7f0e3 455static void do_enable_hdmi(struct display_info_t const *dev)
d67b0d97 456{
5ea7f0e3 457 imx_enable_hdmi_phy();
d67b0d97
EN		 458}
459
460static int detect_i2c(struct display_info_t const *dev)
461{
462 return ((0 == i2c_set_bus_num(dev->bus))
463 &&
464 (0 == i2c_probe(dev->addr)));
465}
466
467static void enable_lvds(struct display_info_t const *dev)
468{
469 struct iomuxc *iomux = (struct iomuxc *)
470 IOMUXC_BASE_ADDR;
471 u32 reg = readl(&iomux->gpr[2]);
472 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
473 writel(reg, &iomux->gpr[2]);
474 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
475}
476
4328fb05
RW		 477static void enable_lvds_jeida(struct display_info_t const *dev)
478{
479 struct iomuxc *iomux = (struct iomuxc *)
480 IOMUXC_BASE_ADDR;
481 u32 reg = readl(&iomux->gpr[2]);
482 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
483 |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
484 writel(reg, &iomux->gpr[2]);
485 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
486}
487
d67b0d97
EN		 488static void enable_rgb(struct display_info_t const *dev)
489{
490 imx_iomux_v3_setup_multiple_pads(
491 rgb_pads,
492 ARRAY_SIZE(rgb_pads));
493 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
494}
495
a47e4495 496struct display_info_t const displays[] = {{
d67b0d97
EN		 497 .bus = -1,
498 .addr = 0,
499 .pixfmt = IPU_PIX_FMT_RGB24,
500 .detect = detect_hdmi,
5ea7f0e3 501 .enable = do_enable_hdmi,
d67b0d97
EN		 502 .mode = {
503 .name = "HDMI",
504 .refresh = 60,
505 .xres = 1024,
506 .yres = 768,
507 .pixclock = 15385,
508 .left_margin = 220,
509 .right_margin = 40,
510 .upper_margin = 21,
511 .lower_margin = 7,
512 .hsync_len = 60,
513 .vsync_len = 10,
514 .sync = FB_SYNC_EXT,
515 .vmode = FB_VMODE_NONINTERLACED
4328fb05
RW		 516} }, {
517 .bus = 0,
518 .addr = 0,
519 .pixfmt = IPU_PIX_FMT_RGB24,
520 .detect = NULL,
521 .enable = enable_lvds_jeida,
522 .mode = {
523 .name = "LDB-WXGA",
524 .refresh = 60,
525 .xres = 1280,
526 .yres = 800,
527 .pixclock = 14065,
528 .left_margin = 40,
529 .right_margin = 40,
530 .upper_margin = 3,
531 .lower_margin = 80,
532 .hsync_len = 10,
533 .vsync_len = 10,
534 .sync = FB_SYNC_EXT,
535 .vmode = FB_VMODE_NONINTERLACED
d6949e3f
EN		 536} }, {
537 .bus = 0,
538 .addr = 0,
539 .pixfmt = IPU_PIX_FMT_RGB24,
540 .detect = NULL,
541 .enable = enable_lvds,
542 .mode = {
543 .name = "LDB-WXGA-S",
544 .refresh = 60,
545 .xres = 1280,
546 .yres = 800,
547 .pixclock = 14065,
548 .left_margin = 40,
549 .right_margin = 40,
550 .upper_margin = 3,
551 .lower_margin = 80,
552 .hsync_len = 10,
553 .vsync_len = 10,
554 .sync = FB_SYNC_EXT,
555 .vmode = FB_VMODE_NONINTERLACED
d67b0d97
EN		 556} }, {
557 .bus = 2,
558 .addr = 0x4,
559 .pixfmt = IPU_PIX_FMT_LVDS666,
560 .detect = detect_i2c,
561 .enable = enable_lvds,
562 .mode = {
563 .name = "Hannstar-XGA",
564 .refresh = 60,
565 .xres = 1024,
566 .yres = 768,
567 .pixclock = 15385,
568 .left_margin = 220,
569 .right_margin = 40,
570 .upper_margin = 21,
571 .lower_margin = 7,
572 .hsync_len = 60,
573 .vsync_len = 10,
574 .sync = FB_SYNC_EXT,
575 .vmode = FB_VMODE_NONINTERLACED
4adc1127
EN		 576} }, {
577 .bus = 0,
578 .addr = 0,
579 .pixfmt = IPU_PIX_FMT_LVDS666,
580 .detect = NULL,
581 .enable = enable_lvds,
582 .mode = {
583 .name = "LG-9.7",
584 .refresh = 60,
585 .xres = 1024,
586 .yres = 768,
587 .pixclock = 15385, /* ~65MHz */
588 .left_margin = 480,
589 .right_margin = 260,
590 .upper_margin = 16,
591 .lower_margin = 6,
592 .hsync_len = 250,
593 .vsync_len = 10,
594 .sync = FB_SYNC_EXT,
595 .vmode = FB_VMODE_NONINTERLACED
d67b0d97
EN		 596} }, {
597 .bus = 2,
598 .addr = 0x38,
599 .pixfmt = IPU_PIX_FMT_LVDS666,
600 .detect = detect_i2c,
601 .enable = enable_lvds,
602 .mode = {
603 .name = "wsvga-lvds",
604 .refresh = 60,
605 .xres = 1024,
606 .yres = 600,
607 .pixclock = 15385,
608 .left_margin = 220,
609 .right_margin = 40,
610 .upper_margin = 21,
611 .lower_margin = 7,
612 .hsync_len = 60,
613 .vsync_len = 10,
614 .sync = FB_SYNC_EXT,
615 .vmode = FB_VMODE_NONINTERLACED
04edda26
EN		 616} }, {
617 .bus = 2,
618 .addr = 0x10,
619 .pixfmt = IPU_PIX_FMT_RGB666,
620 .detect = detect_i2c,
621 .enable = enable_rgb,
622 .mode = {
623 .name = "fusion7",
624 .refresh = 60,
625 .xres = 800,
626 .yres = 480,
627 .pixclock = 33898,
628 .left_margin = 96,
629 .right_margin = 24,
630 .upper_margin = 3,
631 .lower_margin = 10,
632 .hsync_len = 72,
633 .vsync_len = 7,
634 .sync = 0x40000002,
635 .vmode = FB_VMODE_NONINTERLACED
13566306
EN		 636} }, {
637 .bus = 0,
638 .addr = 0,
639 .pixfmt = IPU_PIX_FMT_RGB666,
640 .detect = NULL,
641 .enable = enable_rgb,
642 .mode = {
643 .name = "svga",
644 .refresh = 60,
645 .xres = 800,
646 .yres = 600,
647 .pixclock = 15385,
648 .left_margin = 220,
649 .right_margin = 40,
650 .upper_margin = 21,
651 .lower_margin = 7,
652 .hsync_len = 60,
653 .vsync_len = 10,
654 .sync = 0,
655 .vmode = FB_VMODE_NONINTERLACED
d67b0d97
EN		 656} }, {
657 .bus = 2,
658 .addr = 0x48,
659 .pixfmt = IPU_PIX_FMT_RGB666,
660 .detect = detect_i2c,
661 .enable = enable_rgb,
662 .mode = {
663 .name = "wvga-rgb",
664 .refresh = 57,
665 .xres = 800,
666 .yres = 480,
667 .pixclock = 37037,
668 .left_margin = 40,
669 .right_margin = 60,
670 .upper_margin = 10,
671 .lower_margin = 10,
672 .hsync_len = 20,
673 .vsync_len = 10,
674 .sync = 0,
675 .vmode = FB_VMODE_NONINTERLACED
443d4d15
EN		 676} }, {
677 .bus = 0,
678 .addr = 0,
679 .pixfmt = IPU_PIX_FMT_RGB24,
680 .detect = NULL,
681 .enable = enable_rgb,
682 .mode = {
683 .name = "qvga",
684 .refresh = 60,
685 .xres = 320,
686 .yres = 240,
687 .pixclock = 37037,
688 .left_margin = 38,
689 .right_margin = 37,
690 .upper_margin = 16,
691 .lower_margin = 15,
692 .hsync_len = 30,
693 .vsync_len = 3,
694 .sync = 0,
695 .vmode = FB_VMODE_NONINTERLACED
d67b0d97 696} } };
a47e4495 697size_t display_count = ARRAY_SIZE(displays);
d67b0d97 698
c9c86bde
EN		 699int board_cfb_skip(void)
700{
701 return NULL != getenv("novideo");
702}
703
d67b0d97
EN		 704static void setup_display(void)
705{
706 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
d67b0d97 707 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
d67b0d97
EN		 708 int reg;
709
5ea7f0e3
PKS		 710 enable_ipu_clock();
711 imx_setup_hdmi();
d67b0d97
EN		 712 /* Turn on LDB0,IPU,IPU DI0 clocks */
713 reg = __raw_readl(&mxc_ccm->CCGR3);
5ea7f0e3 714 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
d67b0d97
EN		 715 writel(reg, &mxc_ccm->CCGR3);
716
d67b0d97
EN		 717 /* set LDB0, LDB1 clk select to 011/011 */
718 reg = readl(&mxc_ccm->cs2cdr);
719 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
720 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
721 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
722 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
723 writel(reg, &mxc_ccm->cs2cdr);
724
725 reg = readl(&mxc_ccm->cscmr2);
726 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
727 writel(reg, &mxc_ccm->cscmr2);
728
729 reg = readl(&mxc_ccm->chsccdr);
d67b0d97 730 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
5ea7f0e3 731 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
d67b0d97
EN		 732 writel(reg, &mxc_ccm->chsccdr);
733
734 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
735 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
736 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
737 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
738 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
739 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
740 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
741 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
742 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
743 writel(reg, &iomux->gpr[2]);
744
745 reg = readl(&iomux->gpr[3]);
8907c2c5
EN		 746 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
747 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
d67b0d97
EN		 748 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
749 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
750 writel(reg, &iomux->gpr[3]);
751
752 /* backlights off until needed */
753 imx_iomux_v3_setup_multiple_pads(backlight_pads,
754 ARRAY_SIZE(backlight_pads));
755 gpio_direction_input(LVDS_BACKLIGHT_GP);
756 gpio_direction_input(RGB_BACKLIGHT_GP);
757}
758#endif
759
a3b527a9 760static iomux_v3_cfg_t const init_pads[] = {
693cccf4
TK		 761 /* SGTL5000 sys_mclk */
762 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
763
764 /* J5 - Camera MCLK */
765 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
766
767 /* wl1271 pads on nitrogen6x */
a3b527a9
EN		 768 /* WL12XX_WL_IRQ_GP */
769 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
770 /* WL12XX_WL_ENABLE_GP */
771 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
772 /* WL12XX_BT_ENABLE_GP */
773 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
774 /* USB otg power */
775 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
776 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
777 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
778 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
779 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
780};
781
782#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
783
784static unsigned gpios_out_low[] = {
785 /* Disable wl1271 */
786 IMX_GPIO_NR(6, 15), /* disable wireless */
787 IMX_GPIO_NR(6, 16), /* disable bluetooth */
788 IMX_GPIO_NR(3, 22), /* disable USB otg power */
789 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
790 IMX_GPIO_NR(1, 8), /* ov5642 reset */
791};
792
793static unsigned gpios_out_high[] = {
794 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
795 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
796};
797
798static void set_gpios(unsigned *p, int cnt, int val)
799{
800 int i;
801
802 for (i = 0; i < cnt; i++)
803 gpio_direction_output(*p++, val);
804}
805
d67b0d97
EN		 806int board_early_init_f(void)
807{
808 setup_iomux_uart();
809
a3b527a9
EN		 810 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
811 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
d67b0d97 812 gpio_direction_input(WL12XX_WL_IRQ_GP);
d67b0d97
EN		 813
814 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
a3b527a9 815 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
d67b0d97
EN		 816 setup_buttons();
817
818#if defined(CONFIG_VIDEO_IPUV3)
819 setup_display();
820#endif
821 return 0;
822}
823
824/*
825 * Do not overwrite the console
826 * Use always serial for U-Boot console
827 */
828int overwrite_console(void)
829{
830 return 1;
831}
832
833int board_init(void)
834{
0a11d6f2 835 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
7132869d
TK		 836
837 clrsetbits_le32(&iomuxc_regs->gpr[1],
838 IOMUXC_GPR1_OTG_ID_MASK,
839 IOMUXC_GPR1_OTG_ID_GPIO1);
840
08ce074e
TK		 841 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
842
d67b0d97
EN		 843 /* address of boot parameters */
844 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
845
846#ifdef CONFIG_MXC_SPI
847 setup_spi();
848#endif
41612472
EN		 849 imx_iomux_v3_setup_multiple_pads(
850 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
d67b0d97
EN		 851 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
852 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
853 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
854
855#ifdef CONFIG_CMD_SATA
856 setup_sata();
857#endif
858
859 return 0;
860}
861
862int checkboard(void)
863{
864 if (gpio_get_value(WL12XX_WL_IRQ_GP))
865 puts("Board: Nitrogen6X\n");
866 else
867 puts("Board: SABRE Lite\n");
868
869 return 0;
870}
871
872struct button_key {
873 char const *name;
874 unsigned gpnum;
875 char ident;
876};
877
878static struct button_key const buttons[] = {
879 {"back", IMX_GPIO_NR(2, 2), 'B'},
880 {"home", IMX_GPIO_NR(2, 4), 'H'},
881 {"menu", IMX_GPIO_NR(2, 1), 'M'},
882 {"search", IMX_GPIO_NR(2, 3), 'S'},
883 {"volup", IMX_GPIO_NR(7, 13), 'V'},
884 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
885};
886
887/*
888 * generate a null-terminated string containing the buttons pressed
889 * returns number of keys pressed
890 */
891static int read_keys(char *buf)
892{
893 int i, numpressed = 0;
894 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
895 if (!gpio_get_value(buttons[i].gpnum))
896 buf[numpressed++] = buttons[i].ident;
897 }
898 buf[numpressed] = '\0';
899 return numpressed;
900}
901
902static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
903{
904 char envvalue[ARRAY_SIZE(buttons)+1];
905 int numpressed = read_keys(envvalue);
906 setenv("keybd", envvalue);
907 return numpressed == 0;
908}
909
910U_BOOT_CMD(
911 kbd, 1, 1, do_kbd,
912 "Tests for keypresses, sets 'keybd' environment variable",
913 "Returns 0 (true) to shell if key is pressed."
914);
915
916#ifdef CONFIG_PREBOOT
917static char const kbd_magic_prefix[] = "key_magic";
918static char const kbd_command_prefix[] = "key_cmd";
919
920static void preboot_keys(void)
921{
922 int numpressed;
923 char keypress[ARRAY_SIZE(buttons)+1];
924 numpressed = read_keys(keypress);
925 if (numpressed) {
926 char *kbd_magic_keys = getenv("magic_keys");
927 char *suffix;
928 /*
929 * loop over all magic keys
930 */
931 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
932 char *keys;
933 char magic[sizeof(kbd_magic_prefix) + 1];
934 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
935 keys = getenv(magic);
936 if (keys) {
937 if (!strcmp(keys, keypress))
938 break;
939 }
940 }
941 if (*suffix) {
942 char cmd_name[sizeof(kbd_command_prefix) + 1];
943 char *cmd;
944 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
945 cmd = getenv(cmd_name);
946 if (cmd) {
947 setenv("preboot", cmd);
948 return;
949 }
950 }
951 }
952}
953#endif
954
955#ifdef CONFIG_CMD_BMODE
956static const struct boot_mode board_boot_modes[] = {
957 /* 4 bit bus width */
958 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
959 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
960 {NULL, 0},
961};
962#endif
963
964int misc_init_r(void)
965{
966#ifdef CONFIG_PREBOOT
967 preboot_keys();
968#endif
969
970#ifdef CONFIG_CMD_BMODE
971 add_board_boot_modes(board_boot_modes);
972#endif
973 return 0;
974}
"Das U-Boot" Source Tree