[people/ms/u-boot.git] / board / cloudengines / pogo_e02 / pogo_e02.c

/*
 * Copyright (C) 2012
 * David Purdy <david.c.purdy@gmail.com>
 *
 * Based on Kirkwood support:
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include "pogo_e02.h"

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
			  POGO_E02_OE_VAL_HIGH,
			  POGO_E02_OE_LOW, POGO_E02_OE_HIGH);

	/* Multi-Purpose Pins Functionality configuration */
	static const u32 kwmpp_config[] = {
		MPP0_NF_IO2,
		MPP1_NF_IO3,
		MPP2_NF_IO4,
		MPP3_NF_IO5,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_UART0_RTS,
		MPP9_UART0_CTS,
		MPP10_UART0_TXD,
		MPP11_UART0_RXD,
		MPP12_SD_CLK,
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP29_TSMP9,	/* USB Power Enable */
		MPP48_GPIO,	/* LED green */
		MPP49_GPIO,	/* LED orange */
		0
	};
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/* Boot parameters address */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
/* Configure and initialize PHY */
void reset_phy(void)
{
	u16 reg;
	u16 devadr;
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..(%s) could not read PHY dev address\n", __func__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	debug("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */
Commit	Line	Data
1d0f5fa1 DP	1	/*
	2	* Copyright (C) 2012
	3	* David Purdy <david.c.purdy@gmail.com>
	4	*
	5	* Based on Kirkwood support:
	6	* (C) Copyright 2009
	7	* Marvell Semiconductor <www.marvell.com>
	8	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
1d0f5fa1 DP	11	*/
	12
	13	#include <common.h>
	14	#include <miiphy.h>
	15	#include <asm/arch/cpu.h>
3dc23f78	16	#include <asm/arch/soc.h>
1d0f5fa1 DP	17	#include <asm/arch/mpp.h>
	18	#include "pogo_e02.h"
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	int board_early_init_f(void)
	23	{
	24	/*
	25	* default gpio configuration
	26	* There are maximum 64 gpios controlled through 2 sets of registers
	27	* the below configuration configures mainly initial LED status
	28	*/
d5c5132f SR	29	mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
	30	POGO_E02_OE_VAL_HIGH,
	31	POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
1d0f5fa1 DP	32
1d0f5fa1 DP	33	/* Multi-Purpose Pins Functionality configuration */
9d86f0c3	34	static const u32 kwmpp_config[] = {
1d0f5fa1 DP	35	MPP0_NF_IO2,
	36	MPP1_NF_IO3,
	37	MPP2_NF_IO4,
	38	MPP3_NF_IO5,
	39	MPP4_NF_IO6,
	40	MPP5_NF_IO7,
	41	MPP6_SYSRST_OUTn,
	42	MPP7_GPO,
	43	MPP8_UART0_RTS,
	44	MPP9_UART0_CTS,
	45	MPP10_UART0_TXD,
	46	MPP11_UART0_RXD,
	47	MPP12_SD_CLK,
	48	MPP13_SD_CMD,
	49	MPP14_SD_D0,
	50	MPP15_SD_D1,
	51	MPP16_SD_D2,
	52	MPP17_SD_D3,
	53	MPP18_NF_IO0,
	54	MPP19_NF_IO1,
	55	MPP29_TSMP9, /* USB Power Enable */
	56	MPP48_GPIO, /* LED green */
	57	MPP49_GPIO, /* LED orange */
	58	0
	59	};
84683638	60	kirkwood_mpp_conf(kwmpp_config, NULL);
1d0f5fa1 DP	61	return 0;
	62	}
	63
	64	int board_init(void)
	65	{
	66	/* Boot parameters address */
96c5f081	67	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
1d0f5fa1 DP	68
	69	return 0;
	70	}
	71
	72	#ifdef CONFIG_RESET_PHY_R
	73	/* Configure and initialize PHY */
	74	void reset_phy(void)
	75	{
	76	u16 reg;
	77	u16 devadr;
	78	char *name = "egiga0";
	79
	80	if (miiphy_set_current_dev(name))
	81	return;
	82
	83	/* command to read PHY dev address */
	84	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
	85	printf("Err..(%s) could not read PHY dev address\n", __func__);
	86	return;
	87	}
	88
	89	/*
	90	* Enable RGMII delay on Tx and Rx for CPU port
	91	* Ref: sec 4.7.2 of chip datasheet
	92	*/
	93	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	94	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	95	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	96	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	97	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	98
	99	/* reset the phy */
	100	miiphy_reset(name, devadr);
	101
	102	debug("88E1116 Initialized on %s\n", name);
	103	}
	104	#endif /* CONFIG_RESET_PHY_R */