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ARM: imx: cm_fx6: remove sata init code from board file
[people/ms/u-boot.git] / board / compulab / cm_fx6 / cm_fx6.c
CommitLineData
e32028a7
NK		 1/*
2 * Board functions for Compulab CM-FX6 board
3 *
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5 *
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
8d331e38 12#include <ahci.h>
3f0e935f 13#include <dm.h>
8d331e38 14#include <dwc_ahsata.h>
e32028a7 15#include <fsl_esdhc.h>
02b1343e 16#include <miiphy.h>
62d6bac6 17#include <mtd_node.h>
02b1343e 18#include <netdev.h>
4377859a 19#include <errno.h>
d6276ab1 20#include <usb.h>
02b1343e 21#include <fdt_support.h>
206f38f7 22#include <sata.h>
f82eb2fa 23#include <splash.h>
a6b0652b 24#include <asm/arch/crm_regs.h>
e32028a7 25#include <asm/arch/sys_proto.h>
0f3effb9 26#include <asm/arch/iomux.h>
deb94d61 27#include <asm/arch/mxc_hdmi.h>
552a848e
SB		 28#include <asm/mach-imx/mxc_i2c.h>
29#include <asm/mach-imx/sata.h>
30#include <asm/mach-imx/video.h>
a6b0652b 31#include <asm/io.h>
02b1343e 32#include <asm/gpio.h>
86256b79 33#include <dm/platform_data/serial_mxc.h>
8d331e38 34#include <dm/device-internal.h>
62d6bac6 35#include <jffs2/load_kernel.h>
e32028a7 36#include "common.h"
f66113c0 37#include "../common/eeprom.h"
3a236a35 38#include "../common/common.h"
e32028a7
NK		 39
40DECLARE_GLOBAL_DATA_PTR;
41
3a236a35
NK		 42#ifdef CONFIG_SPLASH_SCREEN
43static struct splash_location cm_fx6_splash_locations[] = {
44 {
45 .name = "sf",
46 .storage = SPLASH_STORAGE_SF,
870dd309 47 .flags = SPLASH_STORAGE_RAW,
3a236a35
NK		 48 .offset = 0x100000,
49 },
ec26c1ee
NK		 50 {
51 .name = "mmc_fs",
52 .storage = SPLASH_STORAGE_MMC,
53 .flags = SPLASH_STORAGE_FS,
54 .devpart = "2:1",
55 },
56 {
57 .name = "usb_fs",
58 .storage = SPLASH_STORAGE_USB,
59 .flags = SPLASH_STORAGE_FS,
60 .devpart = "0:1",
61 },
62 {
63 .name = "sata_fs",
64 .storage = SPLASH_STORAGE_SATA,
65 .flags = SPLASH_STORAGE_FS,
66 .devpart = "0:1",
67 },
3a236a35
NK		 68};
69
70int splash_screen_prepare(void)
71{
f82eb2fa
NK		 72 return splash_source_load(cm_fx6_splash_locations,
73 ARRAY_SIZE(cm_fx6_splash_locations));
3a236a35
NK		 74}
75#endif
76
deb94d61
NK		 77#ifdef CONFIG_IMX_HDMI
78static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
79{
b406f903
NK		 80 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
81 imx_setup_hdmi();
82 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
deb94d61
NK		 83 imx_enable_hdmi_phy();
84}
85
4377859a
NK		 86static struct display_info_t preset_hdmi_1024X768 = {
87 .bus = -1,
88 .addr = 0,
89 .pixfmt = IPU_PIX_FMT_RGB24,
90 .enable = cm_fx6_enable_hdmi,
91 .mode = {
92 .name = "HDMI",
93 .refresh = 60,
94 .xres = 1024,
95 .yres = 768,
96 .pixclock = 40385,
97 .left_margin = 220,
98 .right_margin = 40,
99 .upper_margin = 21,
100 .lower_margin = 7,
101 .hsync_len = 60,
102 .vsync_len = 10,
103 .sync = FB_SYNC_EXT,
104 .vmode = FB_VMODE_NONINTERLACED,
105 }
deb94d61 106};
deb94d61
NK		 107
108static void cm_fx6_setup_display(void)
109{
75dbbbfd 110 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
deb94d61
NK		 111
112 enable_ipu_clock();
75dbbbfd 113 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
deb94d61 114}
4377859a
NK		 115
116int board_video_skip(void)
117{
118 int ret;
119 struct display_info_t *preset;
00caae6d 120 char const *panel = env_get("displaytype");
33299499
NK		 121
122 if (!panel) /* Also accept panel for backward compatibility */
00caae6d 123 panel = env_get("panel");
4377859a
NK		 124
125 if (!panel)
126 return -ENOENT;
127
128 if (!strcmp(panel, "HDMI"))
129 preset = &preset_hdmi_1024X768;
130 else
131 return -EINVAL;
132
133 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
134 if (ret) {
135 printf("Can't init display %s: %d\n", preset->mode.name, ret);
136 return ret;
137 }
138
139 preset->enable(preset);
140 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
141 preset->mode.yres);
142
143 return 0;
144}
deb94d61
NK		 145#else
146static inline void cm_fx6_setup_display(void) {}
147#endif /* CONFIG_VIDEO_IPUV3 */
148
206f38f7
NK		 149#ifdef CONFIG_DWC_AHSATA
150static int cm_fx6_issd_gpios[] = {
151 /* The order of the GPIOs in the array is important! */
b65cbab1 152 CM_FX6_SATA_LDO_EN,
206f38f7
NK		 153 CM_FX6_SATA_PHY_SLP,
154 CM_FX6_SATA_NRSTDLY,
155 CM_FX6_SATA_PWREN,
156 CM_FX6_SATA_NSTANDBY1,
157 CM_FX6_SATA_NSTANDBY2,
206f38f7
NK		 158};
159
160static void cm_fx6_sata_power(int on)
161{
162 int i;
163
164 if (!on) { /* tell the iSSD that the power will be removed */
165 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
166 mdelay(10);
167 }
168
169 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
170 gpio_direction_output(cm_fx6_issd_gpios[i], on);
171 udelay(100);
172 }
173
174 if (!on) /* for compatibility lower the power loss interrupt */
175 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
176}
177
178static iomux_v3_cfg_t const sata_pads[] = {
179 /* SATA PWR */
180 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
184 /* SATA CTRL */
185 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
190};
191
8f488c1b 192static int cm_fx6_setup_issd(void)
206f38f7 193{
8f488c1b
NK		 194 int ret, i;
195
206f38f7 196 SETUP_IOMUX_PADS(sata_pads);
206f38f7 197
8f488c1b
NK		 198 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
199 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
200 if (ret)
201 return ret;
202 }
203
204 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
205 if (ret)
206 return ret;
207
208 return 0;
206f38f7
NK		 209}
210
211#define CM_FX6_SATA_INIT_RETRIES 10
8d331e38 212
8f488c1b
NK		 213#else
214static int cm_fx6_setup_issd(void) { return 0; }
206f38f7
NK		 215#endif
216
f42b2f60
NK		 217#ifdef CONFIG_SYS_I2C_MXC
218#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
219 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
220 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
221
222I2C_PADS(i2c0_pads,
223 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
224 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
225 IMX_GPIO_NR(3, 21),
226 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
227 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
228 IMX_GPIO_NR(3, 28));
229
230I2C_PADS(i2c1_pads,
231 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
232 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
233 IMX_GPIO_NR(4, 12),
234 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
235 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
236 IMX_GPIO_NR(4, 13));
237
238I2C_PADS(i2c2_pads,
239 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
240 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
241 IMX_GPIO_NR(1, 3),
242 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
243 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
244 IMX_GPIO_NR(1, 6));
245
246
edbf8b4f 247static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
f42b2f60 248{
edbf8b4f
SG		 249 int ret;
250
251 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
252 if (ret)
253 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
254
255 return ret;
256}
257
258static int cm_fx6_setup_i2c(void)
259{
260 int ret = 0, err;
261
262 /* i2c<x>_pads are wierd macro variables; we can't use an array */
263 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
264 if (err)
265 ret = err;
266 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
267 if (err)
268 ret = err;
269 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
270 if (err)
271 ret = err;
272
273 return ret;
f42b2f60
NK		 274}
275#else
edbf8b4f 276static int cm_fx6_setup_i2c(void) { return 0; }
f42b2f60
NK		 277#endif
278
0f3effb9
NK		 279#ifdef CONFIG_USB_EHCI_MX6
280#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
281 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
282 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
8f488c1b
NK		 283#define MX6_USBNC_BASEADDR 0x2184800
284#define USBNC_USB_H1_PWR_POL (1 << 9)
0f3effb9 285
8f488c1b 286static int cm_fx6_setup_usb_host(void)
0f3effb9
NK		 287{
288 int err;
289
290 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
8f488c1b
NK		 291 if (err)
292 return err;
0f3effb9 293
8f488c1b 294 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9 295 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9
NK		 296
297 return 0;
298}
299
8f488c1b 300static int cm_fx6_setup_usb_otg(void)
0f3effb9 301{
8f488c1b 302 int err;
0f3effb9
NK		 303 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
304
8f488c1b
NK		 305 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
306 if (err) {
307 printf("USB OTG pwr gpio request failed: %d\n", err);
308 return err;
0f3effb9
NK		 309 }
310
311 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
312 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
313 MUX_PAD_CTRL(WEAK_PULLDOWN));
314 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
315 /* disable ext. charger detect, or it'll affect signal quality at dp. */
316 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
317}
318
d6276ab1
NK		 319int board_usb_phy_mode(int port)
320{
321 return USB_INIT_HOST;
322}
323
0f3effb9
NK		 324int board_ehci_hcd_init(int port)
325{
8f488c1b 326 int ret;
0f3effb9
NK		 327 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
328
8f488c1b
NK		 329 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
330 if (port != 1)
331 return 0;
332
333 /* Set PWR polarity to match power switch's enable polarity */
334 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
335 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
336 if (ret)
337 return ret;
338
339 udelay(10);
340 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
341 if (ret)
342 return ret;
343
344 mdelay(1);
0f3effb9
NK		 345
346 return 0;
347}
348
349int board_ehci_power(int port, int on)
350{
351 if (port == 0)
352 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
353
354 return 0;
355}
8f488c1b
NK		 356#else
357static int cm_fx6_setup_usb_otg(void) { return 0; }
358static int cm_fx6_setup_usb_host(void) { return 0; }
0f3effb9
NK		 359#endif
360
02b1343e
NK		 361#ifdef CONFIG_FEC_MXC
362#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
363 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
364
365static int mx6_rgmii_rework(struct phy_device *phydev)
366{
367 unsigned short val;
368
369 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
370 * which cause ethernet link down/up issue, so disable SmartEEE
371 */
372 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
373 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
375 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
376 val &= ~(0x1 << 8);
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
378
379 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
381 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
382 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
383
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
385 val &= 0xffe3;
386 val |= 0x18;
387 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
388
389 /* introduce tx clock delay */
390 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
391 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
392 val |= 0x0100;
393 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
394
395 return 0;
396}
397
398int board_phy_config(struct phy_device *phydev)
399{
400 mx6_rgmii_rework(phydev);
401
402 if (phydev->drv->config)
403 return phydev->drv->config(phydev);
404
405 return 0;
406}
407
408static iomux_v3_cfg_t const enet_pads[] = {
409 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
410 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
411 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
412 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
413 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
414 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
415 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
416 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
417 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
418 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
419 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
420 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
421 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
422 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
423 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
424 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
425 MUX_PAD_CTRL(ENET_PAD_CTRL)),
426 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
427 MUX_PAD_CTRL(ENET_PAD_CTRL)),
428 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
429 MUX_PAD_CTRL(ENET_PAD_CTRL)),
430};
431
eab29802 432static int handle_mac_address(char *env_var, uint eeprom_bus)
f66113c0
NK		 433{
434 unsigned char enetaddr[6];
435 int rc;
436
35affd7a 437 rc = eth_env_get_enetaddr(env_var, enetaddr);
f66113c0
NK		 438 if (rc)
439 return 0;
440
eab29802 441 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
f66113c0
NK		 442 if (rc)
443 return rc;
444
0adb5b76 445 if (!is_valid_ethaddr(enetaddr))
f66113c0
NK		 446 return -1;
447
fd1e959e 448 return eth_env_set_enetaddr(env_var, enetaddr);
f66113c0
NK		 449}
450
eab29802
NK		 451#define SB_FX6_I2C_EEPROM_BUS 0
452#define NO_MAC_ADDR "No MAC address found for %s\n"
02b1343e
NK		 453int board_eth_init(bd_t *bis)
454{
8f488c1b
NK		 455 int err;
456
eab29802
NK		 457 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
458 printf(NO_MAC_ADDR, "primary NIC");
459
460 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
461 printf(NO_MAC_ADDR, "secondary NIC");
f66113c0 462
02b1343e
NK		 463 SETUP_IOMUX_PADS(enet_pads);
464 /* phy reset */
8f488c1b
NK		 465 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
466 if (err)
467 printf("Etnernet NRST gpio request failed: %d\n", err);
02b1343e
NK		 468 gpio_direction_output(CM_FX6_ENET_NRST, 0);
469 udelay(500);
470 gpio_set_value(CM_FX6_ENET_NRST, 1);
471 enable_enet_clk(1);
472 return cpu_eth_init(bis);
473}
474#endif
475
a6b0652b
NK		 476#ifdef CONFIG_NAND_MXS
477static iomux_v3_cfg_t const nand_pads[] = {
478 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
479 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
480 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
481 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
482 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
483 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
484 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
485 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
486 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
487 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
488 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
489 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
490 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
491 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
492};
493
494static void cm_fx6_setup_gpmi_nand(void)
495{
496 SETUP_IOMUX_PADS(nand_pads);
497 /* Enable clock roots */
498 enable_usdhc_clk(1, 3);
499 enable_usdhc_clk(1, 4);
500
501 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
502 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
503 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
504}
505#else
506static void cm_fx6_setup_gpmi_nand(void) {}
507#endif
508
e32028a7
NK		 509#ifdef CONFIG_FSL_ESDHC
510static struct fsl_esdhc_cfg usdhc_cfg[3] = {
511 {USDHC1_BASE_ADDR},
512 {USDHC2_BASE_ADDR},
513 {USDHC3_BASE_ADDR},
514};
515
516static enum mxc_clock usdhc_clk[3] = {
517 MXC_ESDHC_CLK,
518 MXC_ESDHC2_CLK,
519 MXC_ESDHC3_CLK,
520};
521
522int board_mmc_init(bd_t *bis)
523{
524 int i;
525
526 cm_fx6_set_usdhc_iomux();
527 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
528 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
529 usdhc_cfg[i].max_bus_width = 4;
530 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
531 enable_usdhc_clk(1, i);
532 }
533
534 return 0;
535}
536#endif
537
8f488c1b
NK		 538#ifdef CONFIG_MXC_SPI
539int cm_fx6_setup_ecspi(void)
540{
541 cm_fx6_set_ecspi_iomux();
542 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
543}
544#else
545int cm_fx6_setup_ecspi(void) { return 0; }
546#endif
547
02b1343e 548#ifdef CONFIG_OF_BOARD_SETUP
41855186 549#define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
62d6bac6
CS		 550
551struct node_info nodes[] = {
552 /*
553 * Both entries target the same flash chip. The st,m25p compatible
554 * is used in the vendor device trees, while upstream uses (the
f8de60bd 555 * documented) jedec,spi-nor compatible.
62d6bac6
CS		 556 */
557 { "st,m25p", MTD_DEV_TYPE_NOR, },
558 { "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
559};
560
e895a4b0 561int ft_board_setup(void *blob, bd_t *bd)
02b1343e 562{
41855186
NK		 563 u32 baseboard_rev;
564 int nodeoffset;
02b1343e 565 uint8_t enetaddr[6];
41855186
NK		 566 char baseboard_name[16];
567 int err;
02b1343e 568
ef476836 569 fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
62d6bac6 570
02b1343e 571 /* MAC addr */
35affd7a 572 if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
cc67f4a6
NK		 573 fdt_find_and_setprop(blob,
574 "/soc/aips-bus@02100000/ethernet@02188000",
575 "local-mac-address", enetaddr, 6, 1);
02b1343e 576 }
e895a4b0 577
35affd7a 578 if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
eab29802
NK		 579 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
580 enetaddr, 6, 1);
581 }
582
f8de60bd
CS		 583 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
584
41855186
NK		 585 baseboard_rev = cl_eeprom_get_board_rev(0);
586 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
587 if (err || baseboard_rev == 0)
588 return 0; /* Assume not an early revision SB-FX6m baseboard */
589
590 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
41855186
NK		 591 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
592 fdt_delprop(blob, nodeoffset, "cd-gpios");
c133c503 593 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
41855186
NK		 594 NULL, 0, 1);
595 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
596 NULL, 0, 1);
597 }
598
e895a4b0 599 return 0;
02b1343e
NK		 600}
601#endif
602
e32028a7
NK		 603int board_init(void)
604{
edbf8b4f
SG		 605 int ret;
606
e32028a7 607 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
a6b0652b 608 cm_fx6_setup_gpmi_nand();
edbf8b4f 609
8f488c1b
NK		 610 ret = cm_fx6_setup_ecspi();
611 if (ret)
612 printf("Warning: ECSPI setup failed: %d\n", ret);
613
614 ret = cm_fx6_setup_usb_otg();
615 if (ret)
616 printf("Warning: USB OTG setup failed: %d\n", ret);
617
618 ret = cm_fx6_setup_usb_host();
619 if (ret)
620 printf("Warning: USB host setup failed: %d\n", ret);
621
622 /*
623 * cm-fx6 may have iSSD not assembled and in this case it has
624 * bypasses for a (m)SATA socket on the baseboard. The socketed
625 * device is not controlled by those GPIOs. So just print a warning
626 * if the setup fails.
627 */
628 ret = cm_fx6_setup_issd();
629 if (ret)
630 printf("Warning: iSSD setup failed: %d\n", ret);
631
edbf8b4f
SG		 632 /* Warn on failure but do not abort boot */
633 ret = cm_fx6_setup_i2c();
634 if (ret)
635 printf("Warning: I2C setup failed: %d\n", ret);
a6b0652b 636
deb94d61
NK		 637 cm_fx6_setup_display();
638
4f6478d6
SG		 639 /* This should be done in the MMC driver when MX6 has a clock driver */
640#ifdef CONFIG_FSL_ESDHC
641 if (IS_ENABLED(CONFIG_BLK)) {
642 int i;
643
644 cm_fx6_set_usdhc_iomux();
645 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
646 enable_usdhc_clk(1, i);
647 }
648#endif
649
e32028a7
NK		 650 return 0;
651}
652
653int checkboard(void)
654{
655 puts("Board: CM-FX6\n");
656 return 0;
657}
658
7d1abb7d
NK		 659int misc_init_r(void)
660{
661 cl_print_pcb_info();
662
663 return 0;
664}
665
76b00aca 666int dram_init_banksize(void)
e32028a7
NK		 667{
668 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
669 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
670
671 switch (gd->ram_size) {
672 case 0x10000000: /* DDR_16BIT_256MB */
673 gd->bd->bi_dram[0].size = 0x10000000;
674 gd->bd->bi_dram[1].size = 0;
675 break;
676 case 0x20000000: /* DDR_32BIT_512MB */
677 gd->bd->bi_dram[0].size = 0x20000000;
678 gd->bd->bi_dram[1].size = 0;
679 break;
680 case 0x40000000:
681 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
682 gd->bd->bi_dram[0].size = 0x20000000;
683 gd->bd->bi_dram[1].size = 0x20000000;
684 } else { /* DDR_64BIT_1GB */
685 gd->bd->bi_dram[0].size = 0x40000000;
686 gd->bd->bi_dram[1].size = 0;
687 }
688 break;
689 case 0x80000000: /* DDR_64BIT_2GB */
690 gd->bd->bi_dram[0].size = 0x40000000;
691 gd->bd->bi_dram[1].size = 0x40000000;
692 break;
693 case 0xEFF00000: /* DDR_64BIT_4GB */
694 gd->bd->bi_dram[0].size = 0x70000000;
695 gd->bd->bi_dram[1].size = 0x7FF00000;
696 break;
697 }
76b00aca
SG		 698
699 return 0;
e32028a7
NK		 700}
701
702int dram_init(void)
703{
704 gd->ram_size = imx_ddr_size();
705 switch (gd->ram_size) {
706 case 0x10000000:
707 case 0x20000000:
708 case 0x40000000:
709 case 0x80000000:
710 break;
711 case 0xF0000000:
712 gd->ram_size -= 0x100000;
713 break;
714 default:
715 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
716 return -1;
717 }
718
719 return 0;
720}
f66113c0
NK		 721
722u32 get_board_rev(void)
723{
72898ac7 724 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
f66113c0
NK		 725}
726
3f0e935f
SG		 727static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
728 .reg = (struct mxc_uart *)UART4_BASE,
729};
730
731U_BOOT_DEVICE(cm_fx6_serial) = {
732 .name = "serial_mxc",
733 .platdata = &cm_fx6_mxc_serial_plat,
734};
8d331e38
SG		 735
736#if CONFIG_IS_ENABLED(AHCI)
737static int sata_imx_probe(struct udevice *dev)
738{
739 int i, err;
740
741 /* Make sure this gpio has logical 0 value */
742 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
743 udelay(100);
744 cm_fx6_sata_power(1);
745
746 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
747 err = setup_sata();
748 if (err) {
749 printf("SATA setup failed: %d\n", err);
750 return err;
751 }
752
753 udelay(100);
754
755 err = dwc_ahsata_probe(dev);
756 if (!err)
757 break;
758
759 /* There is no device on the SATA port */
760 if (sata_dm_port_status(0, 0) == 0)
761 break;
762
763 /* There's a device, but link not established. Retry */
764 device_remove(dev, DM_REMOVE_NORMAL);
765 }
766
767 return 0;
768}
769
770static int sata_imx_remove(struct udevice *dev)
771{
772 cm_fx6_sata_power(0);
773 mdelay(250);
774
775 return 0;
776}
777
778struct ahci_ops sata_imx_ops = {
779 .port_status = dwc_ahsata_port_status,
780 .reset = dwc_ahsata_bus_reset,
781 .scan = dwc_ahsata_scan,
782};
783
784static const struct udevice_id sata_imx_ids[] = {
785 { .compatible = "fsl,imx6q-ahci" },
786 { }
787};
788
789U_BOOT_DRIVER(sata_imx) = {
790 .name = "dwc_ahci",
791 .id = UCLASS_AHCI,
792 .of_match = sata_imx_ids,
793 .ops = &sata_imx_ops,
794 .probe = sata_imx_probe,
795 .remove = sata_imx_remove, /* reset bus to stop it */
796};
797#endif /* AHCI */
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