[people/ms/u-boot.git] / board / cpu86 / cpu86.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "cpu86.h"

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
    },

    /* Port B configuration */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
    },

    /* Port C */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
#if defined(CONFIG_SOFT_I2C)
	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
#else /* normal I/O port pins */
	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
#endif
#endif
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
    }
};

/* ------------------------------------------------------------------------- */

/* Check Board Identity:
 */
int checkboard (void)
{
	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
	return 0;
}

/* ------------------------------------------------------------------------- */

/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 *
 * This routine performs standard 8260 initialization sequence
 * and calculates the available memory size. It may be called
 * several times to try different SDRAM configurations on both
 * 60x and local buses.
 */
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
			  ulong orx, volatile uchar * base)
{
	volatile uchar c = 0xff;
	volatile uint *sdmr_ptr;
	volatile uint *orx_ptr;
	ulong maxsize, size;
	int i;

	/* We must be able to test a location outsize the maximum legal size
	 * to find out THAT we are outside; but this address still has to be
	 * mapped by the controller. That means, that the initial mapping has
	 * to be (at least) twice as large as the maximum expected size.
	 */
	maxsize = (1 + (~orx | 0x7fff)) / 2;

	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
	 * we are configuring CS1 if base != 0
	 */
	sdmr_ptr = &memctl->memc_psdmr;
	orx_ptr = &memctl->memc_or2;

	*orx_ptr = orx;

	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
	 */

	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
	*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
		*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */

	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*base = c;

	size = get_ram_size((long *)base, maxsize);

	*orx_ptr = orx | ~(size - 1);

	return (size);
}

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;

#ifndef CONFIG_SYS_RAMBOOT
	ulong size8, size9;
#endif
	long psize;

	psize = 32 * 1024 * 1024;

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
	memctl->memc_psrt = CONFIG_SYS_PSRT;

#ifndef CONFIG_SYS_RAMBOOT
	/* 60x SDRAM setup:
	 */
	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
			  (uchar *) CONFIG_SYS_SDRAM_BASE);
	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
			  (uchar *) CONFIG_SYS_SDRAM_BASE);

	if (size8 < size9) {
		psize = size9;
		printf ("(60x:9COL) ");
	} else {
		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
				  (uchar *) CONFIG_SYS_SDRAM_BASE);
		printf ("(60x:8COL) ");
	}

#endif	/* CONFIG_SYS_RAMBOOT */

	icache_enable ();

	return (psize);
}

#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
Commit	Line	Data
f8cac651 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
f8cac651 WD	6	*/
	7
	8	#include <common.h>
	9	#include <ioports.h>
	10	#include <mpc8260.h>
	11	#include "cpu86.h"
	12
	13	/*
	14	* I/O Port configuration table
	15	*
	16	* if conf is 1, then that port pin will be configured at boot time
	17	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	18	*/
	19
	20	const iop_conf_t iop_conf_tab[4][32] = {
	21
	22	/* Port A configuration */
	23	{ /* conf ppar psor pdir podr pdat */
	24	/* PA31 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII COL */
	25	/* PA30 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII CRS */
	26	/* PA29 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_ER */
	27	/* PA28 / { 1, 1, 1, 1, 0, 0 }, / FCC1 MII TX_EN */
	28	/* PA27 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_DV */
	29	/* PA26 / { 1, 1, 1, 0, 0, 0 }, / FCC1 MII RX_ER */
	30	/* PA25 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII MDIO */
	31	/* PA24 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII MDC */
	32	/* PA23 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII MDIO */
	33	/* PA22 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII MDC */
	34	/* PA21 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[3] */
	35	/* PA20 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[2] */
	36	/* PA19 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[1] */
	37	/* PA18 / { 1, 1, 0, 1, 0, 0 }, / FCC1 MII TxD[0] */
	38	/* PA17 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[0] */
	39	/* PA16 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[1] */
	40	/* PA15 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[2] */
	41	/* PA14 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RxD[3] */
	42	/* PA13 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII TXSL1 */
	43	/* PA12 / { 1, 0, 0, 1, 0, 1 }, / FCC2 MII TXSL0 */
	44	/* PA11 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII TXSL1 */
	45	/* PA10 / { 1, 0, 0, 1, 0, 1 }, / FCC1 MII TXSL0 */
	46	/* PA9 / { 0, 1, 0, 1, 0, 0 }, / SMC2 TXD */
	47	/* PA8 / { 0, 1, 0, 0, 0, 0 }, / SMC2 RXD */
	48	/* PA7 / { 0, 0, 0, 0, 0, 0 }, / PA7 */
	49	/* PA6 / { 1, 0, 0, 1, 0, 1 }, / FCC2 MII PAUSE */
	50	/* PA5 / { 1, 0, 0, 1, 0, 1 }, / FCC1 MII PAUSE */
	51	/* PA4 / { 1, 0, 0, 1, 0, 0 }, / FCC2 MII PWRDN */
	52	/* PA3 / { 1, 0, 0, 1, 0, 0 }, / FCC1 MII PWRDN */
	53	/* PA2 / { 0, 0, 0, 0, 0, 0 }, / PA2 */
	54	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FCC2 MII MDINT */
	55	/* PA0 / { 1, 0, 0, 1, 0, 0 } / FCC1 MII MDINT */
	56	},
	57
	58	/* Port B configuration */
	59	{ /* conf ppar psor pdir podr pdat */
	60	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	61	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	62	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	63	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	64	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	65	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	66	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	67	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	68	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	69	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
70	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
71	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
72	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
73	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
74	/* PB17 / { 0, 0, 0, 0, 0, 0 }, / PB17 */
75	/* PB16 / { 0, 0, 0, 0, 0, 0 }, / PB16 */
76	/* PB15 / { 0, 0, 0, 0, 0, 0 }, / PB15 */
77	/* PB14 / { 0, 0, 0, 0, 0, 0 }, / PB14 */
78	/* PB13 / { 0, 0, 0, 0, 0, 0 }, / PB13 */
79	/* PB12 / { 0, 0, 0, 0, 0, 0 }, / PB12 */
80	/* PB11 / { 0, 0, 0, 0, 0, 0 }, / PB11 */
81	/* PB10 / { 0, 0, 0, 0, 0, 0 }, / PB10 */
82	/* PB9 / { 0, 0, 0, 0, 0, 0 }, / PB9 */
83	/* PB8 / { 0, 0, 0, 0, 0, 0 }, / PB8 */
84	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / PB7 */
85	/* PB6 / { 0, 0, 0, 0, 0, 0 }, / PB6 */
86	/* PB5 / { 0, 0, 0, 0, 0, 0 }, / PB5 */
87	/* PB4 / { 0, 0, 0, 0, 0, 0 }, / PB4 */
88	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / PB3 */
89	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / PB2 */
90	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / PB1 */
91	/* PB0 / { 0, 0, 0, 0, 0, 0 } / PB0 */
92	},
93
94	/* Port C */
95	{ /* conf ppar psor pdir podr pdat */
96	/* PC31 / { 0, 0, 0, 0, 0, 0 }, / PC31 */
97	/* PC30 / { 0, 0, 0, 0, 0, 0 }, / PC30 */
98	/* PC29 / { 1, 0, 0, 0, 0, 0 }, / SCC1 CTS */
99	/* PC28 / { 1, 0, 0, 0, 0, 0 }, / SCC2 CTS */
100	/* PC27 / { 0, 0, 0, 0, 0, 0 }, / PC27 */
101	/* PC26 / { 0, 0, 0, 0, 0, 0 }, / PC26 */
102	/* PC25 / { 0, 0, 0, 0, 0, 0 }, / PC25 */
103	/* PC24 / { 0, 0, 0, 0, 0, 0 }, / PC24 */
104	/* PC23 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DACFD */
105	/* PC22 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DNFD */
106	/* PC21 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RX_CLK */
107	/* PC20 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII TX_CLK */
108	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK */
109	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII TX_CLK */
110	/* PC17 / { 0, 0, 0, 0, 0, 0 }, / PC17 */
111	/* PC16 / { 0, 0, 0, 0, 0, 0 }, / PC16 */
112	/* PC15 / { 0, 0, 0, 0, 0, 0 }, / PC15 */
113	/* PC14 / { 0, 0, 0, 0, 0, 0 }, / PC14 */
114	/* PC13 / { 0, 0, 0, 0, 0, 0 }, / PC13 */
115	/* PC12 / { 0, 0, 0, 0, 0, 0 }, / PC12 */
116	/* PC11 / { 0, 0, 0, 0, 0, 0 }, / PC11 */
117	/* PC10 / { 0, 0, 0, 0, 0, 0 }, / PC10 */
118	/* PC9 / { 0, 0, 0, 0, 0, 0 }, / FC9 */
119	/* PC8 / { 0, 0, 0, 0, 0, 0 }, / PC8 */
120	/* PC7 / { 0, 0, 0, 0, 0, 0 }, / PC7 */
121	/* PC6 / { 0, 0, 0, 0, 0, 0 }, / PC6 */
122	/* PC5 / { 0, 0, 0, 0, 0, 0 }, / PC5 */
123	/* PC4 / { 0, 0, 0, 0, 0, 0 }, / PC4 */
124	/* PC3 / { 0, 0, 0, 0, 0, 0 }, / PC3 */
125	/* PC2 / { 0, 0, 0, 0, 0, 0 }, / PC2 */
126	/* PC1 / { 0, 0, 0, 0, 0, 0 }, / PC1 */
127	/* PC0 / { 0, 0, 0, 0, 0, 0 }, / FDC37C78 DRQFD */
128	},
129
130	/* Port D */
131	{ /* conf ppar psor pdir podr pdat */
132	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 RXD */
133	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 TXD */
134	/* PD29 / { 1, 0, 0, 1, 0, 0 }, / SCC1 RTS */
135	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / SCC2 RXD */
136	/* PD27 / { 1, 1, 0, 1, 0, 0 }, / SCC2 TXD */
137	/* PD26 / { 1, 0, 0, 1, 0, 0 }, / SCC2 RTS */
138	/* PD25 / { 0, 0, 0, 0, 0, 0 }, / PD25 */
139	/* PD24 / { 0, 0, 0, 0, 0, 0 }, / PD24 */
140	/* PD23 / { 0, 0, 0, 0, 0, 0 }, / PD23 */
141	/* PD22 / { 0, 0, 0, 0, 0, 0 }, / PD22 */
142	/* PD21 / { 0, 0, 0, 0, 0, 0 }, / PD21 */
143	/* PD20 / { 0, 0, 0, 0, 0, 0 }, / PD20 */
144	/* PD19 / { 0, 0, 0, 0, 0, 0 }, / PD19 */
145	/* PD18 / { 0, 0, 0, 0, 0, 0 }, / PD18 */
146	/* PD17 / { 0, 0, 0, 0, 0, 0 }, / PD17 */
147	/* PD16 / { 0, 0, 0, 0, 0, 0 }, / PD16 */
148	#if defined(CONFIG_SOFT_I2C)
149	/* PD15 / { 1, 0, 0, 1, 1, 1 }, / I2C SDA */
150	/* PD14 / { 1, 0, 0, 1, 1, 1 }, / I2C SCL */
151	#else
152	#if defined(CONFIG_HARD_I2C)
153	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
154	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
155	#else /* normal I/O port pins */
156	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
157	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
158	#endif
159	#endif
160	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
161	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
162	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
163	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
164	/* PD9 / { 1, 1, 0, 1, 0, 0 }, / SMC1 TXD */
165	/* PD8 / { 1, 1, 0, 0, 0, 0 }, / SMC1 RXD */
166	/* PD7 / { 0, 0, 0, 0, 0, 0 }, / PD7 */
167	/* PD6 / { 0, 0, 0, 0, 0, 0 }, / PD6 */
168	/* PD5 / { 0, 0, 0, 0, 0, 0 }, / PD5 */
169	/* PD4 / { 0, 0, 0, 0, 0, 0 }, / PD4 */
170	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / PD3 */
171	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / PD2 */
172	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / PD1 */
173	/* PD0 / { 0, 0, 0, 0, 0, 0 } / PD0 */
174	}
175	};
176
177	/* ------------------------------------------------------------------------- */
178
179	/* Check Board Identity:
180	*/
181	int checkboard (void)
182	{
183	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
184	return 0;
185	}
186
187	/* ------------------------------------------------------------------------- */
188
189	/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
190	*
191	* This routine performs standard 8260 initialization sequence
192	* and calculates the available memory size. It may be called
193	* several times to try different SDRAM configurations on both
194	* 60x and local buses.
195	*/
196	static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
197	ulong orx, volatile uchar * base)
198	{
199	volatile uchar c = 0xff;
f8cac651 WD	200	volatile uint *sdmr_ptr;
f8cac651 WD	201	volatile uint *orx_ptr;
c83bf6a2	202	ulong maxsize, size;
f8cac651	203	int i;
f8cac651 WD	204
	205	/* We must be able to test a location outsize the maximum legal size
	206	* to find out THAT we are outside; but this address still has to be
	207	* mapped by the controller. That means, that the initial mapping has
	208	* to be (at least) twice as large as the maximum expected size.
	209	*/
	210	maxsize = (1 + (~orx \| 0x7fff)) / 2;
	211
6d0f6bcf	212	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
f8cac651 WD	213	* we are configuring CS1 if base != 0
	214	*/
	215	sdmr_ptr = &memctl->memc_psdmr;
	216	orx_ptr = &memctl->memc_or2;
	217
	218	*orx_ptr = orx;
	219
	220	/*
	221	* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	222	*
	223	* "At system reset, initialization software must set up the
	224	* programmable parameters in the memory controller banks registers
	225	* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	226	* system software should execute the following initialization sequence
	227	* for each SDRAM device.
	228	*
	229	* 1. Issue a PRECHARGE-ALL-BANKS command
	230	* 2. Issue eight CBR REFRESH commands
	231	* 3. Issue a MODE-SET command to initialize the mode register
	232	*
	233	* The initial commands are executed by setting P/LSDMR[OP] and
	234	* accessing the SDRAM with a single-byte transaction."
	235	*
	236	* The appropriate BRx/ORx registers have already been set when we
6d0f6bcf	237	* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
f8cac651 WD	238	*/
	239
	240	*sdmr_ptr = sdmr \| PSDMR_OP_PREA;
	241	*base = c;
	242
	243	*sdmr_ptr = sdmr \| PSDMR_OP_CBRR;
	244	for (i = 0; i < 8; i++)
	245	*base = c;
	246
	247	*sdmr_ptr = sdmr \| PSDMR_OP_MRW;
6d0f6bcf	248	(base + CONFIG_SYS_MRS_OFFS) = c; / setting MR on address lines */
f8cac651 WD	249
	250	*sdmr_ptr = sdmr \| PSDMR_OP_NORM \| PSDMR_RFEN;
	251	*base = c;
	252
c83bf6a2	253	size = get_ram_size((long *)base, maxsize);
f8cac651	254
c83bf6a2	255	*orx_ptr = orx \| ~(size - 1);
f8cac651	256
c83bf6a2	257	return (size);
f8cac651 WD	258	}
f8cac651 WD	259
9973e3c6	260	phys_size_t initdram (int board_type)
f8cac651	261	{
6d0f6bcf	262	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
f8cac651 WD	263	volatile memctl8260_t *memctl = &immap->im_memctl;
f8cac651 WD	264
6d0f6bcf	265	#ifndef CONFIG_SYS_RAMBOOT
f8cac651 WD	266	ulong size8, size9;
	267	#endif
	268	long psize;
	269
	270	psize = 32 * 1024 * 1024;
	271
6d0f6bcf JCPV	272	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
6d0f6bcf JCPV	273	memctl->memc_psrt = CONFIG_SYS_PSRT;
f8cac651	274
6d0f6bcf	275	#ifndef CONFIG_SYS_RAMBOOT
f8cac651 WD	276	/* 60x SDRAM setup:
f8cac651 WD	277	*/
6d0f6bcf JCPV	278	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
	279	(uchar *) CONFIG_SYS_SDRAM_BASE);
	280	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
	281	(uchar *) CONFIG_SYS_SDRAM_BASE);
f8cac651 WD	282
	283	if (size8 < size9) {
	284	psize = size9;
	285	printf ("(60x:9COL) ");
	286	} else {
6d0f6bcf JCPV	287	psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
6d0f6bcf JCPV	288	(uchar *) CONFIG_SYS_SDRAM_BASE);
f8cac651 WD	289	printf ("(60x:8COL) ");
	290	}
	291
6d0f6bcf	292	#endif /* CONFIG_SYS_RAMBOOT */
f8cac651 WD	293
	294	icache_enable ();
	295
	296	return (psize);
	297	}
	298
fcec2eb9	299	#if defined(CONFIG_CMD_DOC)
f8cac651 WD	300	void doc_init (void)
f8cac651 WD	301	{
6d0f6bcf	302	doc_probe (CONFIG_SYS_DOC_BASE);
f8cac651 WD	303	}
f8cac651 WD	304	#endif